28 	TSHUT_MODE_CRU = 0,
35  * 0: low active, 1: high active
38 	TSHUT_LOW_ACTIVE = 0,
48 	ADC_DECREMENT = 0,
73  * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
74  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
136  * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
137  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
164 #define TSADCV2_USER_CON			0x00
165 #define TSADCV2_AUTO_CON			0x04
166 #define TSADCV2_INT_EN				0x08
167 #define TSADCV2_INT_PD				0x0c
168 #define TSADCV3_AUTO_SRC_CON			0x0c
169 #define TSADCV3_HT_INT_EN			0x14
170 #define TSADCV3_HSHUT_GPIO_INT_EN		0x18
171 #define TSADCV3_HSHUT_CRU_INT_EN		0x1c
172 #define TSADCV3_INT_PD				0x24
173 #define TSADCV3_HSHUT_PD			0x28
174 #define TSADCV2_DATA(chn)			(0x20 + (chn) * 0x04)
175 #define TSADCV2_COMP_INT(chn)		        (0x30 + (chn) * 0x04)
176 #define TSADCV2_COMP_SHUT(chn)		        (0x40 + (chn) * 0x04)
177 #define TSADCV3_DATA(chn)			(0x2c + (chn) * 0x04)
178 #define TSADCV3_COMP_INT(chn)		        (0x6c + (chn) * 0x04)
179 #define TSADCV3_COMP_SHUT(chn)		        (0x10c + (chn) * 0x04)
180 #define TSADCV2_HIGHT_INT_DEBOUNCE		0x60
181 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE		0x64
182 #define TSADCV3_HIGHT_INT_DEBOUNCE		0x14c
183 #define TSADCV3_HIGHT_TSHUT_DEBOUNCE		0x150
184 #define TSADCV2_AUTO_PERIOD			0x68
185 #define TSADCV2_AUTO_PERIOD_HT			0x6c
186 #define TSADCV3_AUTO_PERIOD			0x154
187 #define TSADCV3_AUTO_PERIOD_HT			0x158
189 #define TSADCV2_AUTO_EN				BIT(0)
206 #define TSADCV4_INT_PD_CLEAR_MASK		0xffffffff
208 #define TSADCV2_DATA_MASK			0xfff
209 #define TSADCV3_DATA_MASK			0x3ff
210 #define TSADCV4_DATA_MASK			0x1ff
224 #define TSADCV2_USER_INTER_PD_SOC		0x340 /* 13 clocks */
225 #define TSADCV5_USER_INTER_PD_SOC		0xfc0 /* 97us, at least 90us */
227 #define GRF_SARADC_TESTBIT			0x0e644
228 #define GRF_TSADC_TESTBIT_L			0x0e648
229 #define GRF_TSADC_TESTBIT_H			0x0e64c
231 #define PX30_GRF_SOC_CON2			0x0408
233 #define RK3568_GRF_TSADC_CON			0x0600
234 #define RK3568_GRF_TSADC_ANA_REG0		(0x10001 << 0)
235 #define RK3568_GRF_TSADC_ANA_REG1		(0x10001 << 1)
236 #define RK3568_GRF_TSADC_ANA_REG2		(0x10001 << 2)
237 #define RK3568_GRF_TSADC_TSEN			(0x10001 << 8)
239 #define RK3588_GRF0_TSADC_CON			0x0100
241 #define RK3588_GRF0_TSADC_TRM			(0xff0077 << 0)
242 #define RK3588_GRF0_TSADC_SHUT_2CRU		(0x30003 << 10)
243 #define RK3588_GRF0_TSADC_SHUT_2GPIO		(0x70007 << 12)
245 #define GRF_SARADC_TESTBIT_ON			(0x10001 << 2)
246 #define GRF_TSADC_TESTBIT_H_ON			(0x10001 << 2)
247 #define GRF_TSADC_VCM_EN_L			(0x10001 << 7)
248 #define GRF_TSADC_VCM_EN_H			(0x10001 << 7)
250 #define GRF_CON_TSADC_CH_INV			(0x10001 << 1)
268 	{0, -40000},
277 	{436, 0},
307 	{0, -40000},
316 	{629, 0},
355 	{3728, 0},
381 	{0, 125000},
385 	{0, -40000},
393 	{368, 0},
423 	{0, -40000},
432 	{122, 0},
462 	{0, -40000},
471 	{470, 0},
501 	{0, -40000},
510 	{1856, 0},
540 	{0, -40000},
556 	low = 0;  in rk_tsadcv2_temp_to_code()
662 	return 0;  in rk_tsadcv2_code_to_temp()
669  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
687 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv2_initialize()
690 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv2_initialize()
706  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
761 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv3_initialize()
764 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv3_initialize()
788 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv7_initialize()
791 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv7_initialize()
947 		return 0;  in rk_tsadcv2_alarm_temp()
962 	return 0;  in rk_tsadcv2_alarm_temp()
979 		return 0;  in rk_tsadcv3_alarm_temp()
989 	return 0;  in rk_tsadcv3_alarm_temp()
1008 	return 0;  in rk_tsadcv2_tshut_temp()
1027 	return 0;  in rk_tsadcv3_tshut_temp()
1065 	.chn_offset = 0,
1089 	.chn_offset = 0,
1114 	.chn_offset = 0,
1164 	.chn_offset = 0,
1188 	.chn_offset = 0,
1213 	.chn_offset = 0,
1238 	.chn_offset = 0,
1263 	.chn_offset = 0,
1288 	.chn_offset = 0,
1372 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_thermal_alarm_irq_thread()
1469 	return 0;  in rockchip_configure_from_dt()
1500 	return 0;  in rockchip_thermal_register_sensor()
1522 	irq = platform_get_irq(pdev, 0);  in rockchip_thermal_probe()
1523 	if (irq < 0)  in rockchip_thermal_probe()
1542 	thermal->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);  in rockchip_thermal_probe()
1571 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_probe()
1590 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_probe()
1601 	return 0;  in rockchip_thermal_probe()
1609 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_remove()
1624 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_thermal_suspend()
1634 	return 0;  in rockchip_thermal_suspend()
1658 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_resume()
1674 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_thermal_resume()
1679 	return 0;  in rockchip_thermal_resume()