882 	void __iomem *controller_base = mt->thermal_base + offset;  in mtk_thermal_init_bank()  local
890 	writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);  in mtk_thermal_init_bank()
898 			controller_base + TEMP_MONCTL2);  in mtk_thermal_init_bank()
902 	       controller_base + TEMP_AHBPOLL);  in mtk_thermal_init_bank()
905 	writel(0x0, controller_base + TEMP_MSRCTL0);  in mtk_thermal_init_bank()
908 	writel(0xffffffff, controller_base + TEMP_AHBTO);  in mtk_thermal_init_bank()
911 	writel(0x0, controller_base + TEMP_MONIDET0);  in mtk_thermal_init_bank()
912 	writel(0x0, controller_base + TEMP_MONIDET1);  in mtk_thermal_init_bank()
927 	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);  in mtk_thermal_init_bank()
931 	       controller_base + TEMP_ADCMUXADDR);  in mtk_thermal_init_bank()
936 		       controller_base + TEMP_PNPMUXADDR);  in mtk_thermal_init_bank()
940 	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);  in mtk_thermal_init_bank()
944 	       controller_base + TEMP_ADCENADDR);  in mtk_thermal_init_bank()
948 	       controller_base + TEMP_ADCVALIDADDR);  in mtk_thermal_init_bank()
952 	       controller_base + TEMP_ADCVOLTADDR);  in mtk_thermal_init_bank()
955 	writel(0x0, controller_base + TEMP_RDCTRL);  in mtk_thermal_init_bank()
959 	       controller_base + TEMP_ADCVALIDMASK);  in mtk_thermal_init_bank()
962 	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);  in mtk_thermal_init_bank()
966 		controller_base + TEMP_ADCWRITECTRL);  in mtk_thermal_init_bank()
973 	       controller_base + TEMP_MONCTL0);  in mtk_thermal_init_bank()
977 	       controller_base + TEMP_ADCWRITECTRL);  in mtk_thermal_init_bank()