1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
21 #include <linux/thermal.h>
36 /* Thermal Controller Registers */
93 /* MT8173 thermal sensors */
115 /* The calibration coefficient of sensor  */
119 #define MT8173_TEMP_MIN		-20000
123  * Layout of the fuses providing the calibration data
125  * MT8183 has 6 sensors and needs 6 VTS calibration data.
126  * MT8173 has 5 sensors and needs 5 VTS calibration data.
127  * MT2701 has 3 sensors and needs 3 VTS calibration data.
128  * MT2712 has 4 sensors and needs 4 VTS calibration data.
144  * Layout of the fuses providing the calibration data
158  * Layout of the fuses providing the calibration data
187 /* MT2701 thermal sensors */
204 /* The calibration coefficient of sensor  */
207 /* MT2712 thermal sensors */
225 /* The calibration coefficient of sensor  */
238 /* The calibration coefficient of sensor  */
241 /* MT8183 thermal sensors */
264 /* The calibration coefficient of sensor  */
279 /* MT7986 thermal sensors */
285 /* The calibration coefficient of sensor  */
339 	/* Calibration values */
353 /* MT8183 thermal sensor data */
374 /* MT8173 thermal sensor data */
397 /* MT2701 thermal sensor data */
417 /* MT2712 thermal sensor data */
437 /* MT7622 thermal sensor data */
445 /* MT7986 thermal sensor data */
453 /* MT8365 thermal sensor data */
472  * The MT8173 thermal controller has four banks. Each bank can read up to
478  * The thermal core only gets the maximum temperature of all banks, so
515  * The MT2701 thermal controller has one bank, which can read up to
519  * The thermal core only gets the maximum temperature of this one bank,
546  * The MT8365 thermal controller has one bank, which can read up to
550  * The thermal core only gets the maximum temperature of this one bank,
580  * The MT2712 thermal controller has one bank, which can read up to
584  * The thermal core only gets the maximum temperature of this one bank,
639  * The MT8183 thermal controller has one bank for the current SW framework.
641  * There are two thermal controller to control the six sensor.
643  * The thermal core only gets the maximum temperature of all sensor, so
704  * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
705  * @mt:	The thermal controller
710  * calibration constants
719 	tmp /= mt->conf->cali_val + mt->o_slope;  in raw_to_mcelsius_v1()
720 	tmp /= 10000 + mt->adc_ge;  in raw_to_mcelsius_v1()
721 	tmp *= raw - mt->vts[sensno] - 3350;  in raw_to_mcelsius_v1()
724 	return mt->degc_cali * 500 - tmp;  in raw_to_mcelsius_v1()
740 	g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);  in raw_to_mcelsius_v2()
741 	g_oe = mt->adc_oe - 512;  in raw_to_mcelsius_v2()
742 	format_1 = mt->vts[VTS2] + 3105 - g_oe;  in raw_to_mcelsius_v2()
743 	format_2 = (mt->degc_cali * 10) >> 1;  in raw_to_mcelsius_v2()
746 	tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;  in raw_to_mcelsius_v2()
749 	if (mt->o_slope_sign == 0)  in raw_to_mcelsius_v2()
750 		tmp = tmp / (165 - mt->o_slope);  in raw_to_mcelsius_v2()
752 		tmp = tmp / (165 + mt->o_slope);  in raw_to_mcelsius_v2()
754 	return (format_2 - tmp) * 100;  in raw_to_mcelsius_v2()
766 	tmp /= 4096 - 512 + mt->adc_ge;  in raw_to_mcelsius_v3()
768 	tmp *= raw - mt->vts[sensno] - 2900;  in raw_to_mcelsius_v3()
770 	return mt->degc_cali * 500 - tmp;  in raw_to_mcelsius_v3()
774  * mtk_thermal_get_bank - get bank
782 	struct mtk_thermal *mt = bank->mt;  in mtk_thermal_get_bank()
785 	if (mt->conf->need_switch_bank) {  in mtk_thermal_get_bank()
786 		mutex_lock(&mt->lock);  in mtk_thermal_get_bank()
788 		val = readl(mt->thermal_base + PTPCORESEL);  in mtk_thermal_get_bank()
790 		val |= bank->id;  in mtk_thermal_get_bank()
791 		writel(val, mt->thermal_base + PTPCORESEL);  in mtk_thermal_get_bank()
796  * mtk_thermal_put_bank - release bank
803 	struct mtk_thermal *mt = bank->mt;  in mtk_thermal_put_bank()
805 	if (mt->conf->need_switch_bank)  in mtk_thermal_put_bank()
806 		mutex_unlock(&mt->lock);  in mtk_thermal_put_bank()
810  * mtk_thermal_bank_temperature - get the temperature of a bank
818 	struct mtk_thermal *mt = bank->mt;  in mtk_thermal_bank_temperature()
819 	const struct mtk_thermal_data *conf = mt->conf;  in mtk_thermal_bank_temperature()
823 	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {  in mtk_thermal_bank_temperature()
824 		raw = readl(mt->thermal_base + conf->msr[i]);  in mtk_thermal_bank_temperature()
826 		temp = mt->raw_to_mcelsius(  in mtk_thermal_bank_temperature()
827 			mt, conf->bank_data[bank->id].sensors[i], raw);  in mtk_thermal_bank_temperature()
854 	for (i = 0; i < mt->conf->num_banks; i++) {  in mtk_read_temp()
855 		struct mtk_thermal_bank *bank = &mt->banks[i];  in mtk_read_temp()
877 	struct mtk_thermal_bank *bank = &mt->banks[num];  in mtk_thermal_init_bank()
878 	const struct mtk_thermal_data *conf = mt->conf;  in mtk_thermal_init_bank()
881 	int offset = mt->conf->controller_offset[ctrl_id];  in mtk_thermal_init_bank()
882 	void __iomem *controller_base = mt->thermal_base + offset;  in mtk_thermal_init_bank()
884 	bank->id = num;  in mtk_thermal_init_bank()
885 	bank->mt = mt;  in mtk_thermal_init_bank()
915 	 * The MT8173 thermal controller does not have its own ADC. Instead it  in mtk_thermal_init_bank()
916 	 * uses AHB bus accesses to control the AUXADC. To do this the thermal  in mtk_thermal_init_bank()
919 	 * Also the thermal controller controls a mux in the APMIXEDSYS register  in mtk_thermal_init_bank()
927 	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);  in mtk_thermal_init_bank()
933 	if (mt->conf->version == MTK_THERMAL_V1) {  in mtk_thermal_init_bank()
940 	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);  in mtk_thermal_init_bank()
947 	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),  in mtk_thermal_init_bank()
951 	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),  in mtk_thermal_init_bank()
968 	for (i = 0; i < conf->bank_data[num].num_sensors; i++)  in mtk_thermal_init_bank()
969 		writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],  in mtk_thermal_init_bank()
970 		       mt->thermal_base + conf->adcpnp[i]);  in mtk_thermal_init_bank()
972 	writel((1 << conf->bank_data[num].num_sensors) - 1,  in mtk_thermal_init_bank()
997 		return -EINVAL;  in mtk_thermal_extract_efuse_v1()
999 	mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);  in mtk_thermal_extract_efuse_v1()
1001 	for (i = 0; i < mt->conf->num_sensors; i++) {  in mtk_thermal_extract_efuse_v1()
1002 		switch (mt->conf->vts_index[i]) {  in mtk_thermal_extract_efuse_v1()
1004 			mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
1007 			mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
1010 			mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);  in mtk_thermal_extract_efuse_v1()
1013 			mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);  in mtk_thermal_extract_efuse_v1()
1016 			mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);  in mtk_thermal_extract_efuse_v1()
1019 			mt->vts[VTSABB] =  in mtk_thermal_extract_efuse_v1()
1027 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
1030 		mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
1032 		mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
1040 		return -EINVAL;  in mtk_thermal_extract_efuse_v2()
1042 	mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);  in mtk_thermal_extract_efuse_v2()
1043 	mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);  in mtk_thermal_extract_efuse_v2()
1044 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);  in mtk_thermal_extract_efuse_v2()
1045 	mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);  in mtk_thermal_extract_efuse_v2()
1046 	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);  in mtk_thermal_extract_efuse_v2()
1047 	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);  in mtk_thermal_extract_efuse_v2()
1048 	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);  in mtk_thermal_extract_efuse_v2()
1049 	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);  in mtk_thermal_extract_efuse_v2()
1057 		return -EINVAL;  in mtk_thermal_extract_efuse_v3()
1059 	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);  in mtk_thermal_extract_efuse_v3()
1060 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);  in mtk_thermal_extract_efuse_v3()
1061 	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);  in mtk_thermal_extract_efuse_v3()
1062 	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);  in mtk_thermal_extract_efuse_v3()
1063 	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);  in mtk_thermal_extract_efuse_v3()
1064 	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);  in mtk_thermal_extract_efuse_v3()
1065 	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);  in mtk_thermal_extract_efuse_v3()
1068 		mt->o_slope = 0;  in mtk_thermal_extract_efuse_v3()
1082 	mt->adc_ge = 512;  in mtk_thermal_get_calibration_data()
1083 	mt->adc_oe = 512;  in mtk_thermal_get_calibration_data()
1084 	for (i = 0; i < mt->conf->num_sensors; i++)  in mtk_thermal_get_calibration_data()
1085 		mt->vts[i] = 260;  in mtk_thermal_get_calibration_data()
1086 	mt->degc_cali = 40;  in mtk_thermal_get_calibration_data()
1087 	mt->o_slope = 0;  in mtk_thermal_get_calibration_data()
1089 	cell = nvmem_cell_get(dev, "calibration-data");  in mtk_thermal_get_calibration_data()
1091 		if (PTR_ERR(cell) == -EPROBE_DEFER)  in mtk_thermal_get_calibration_data()
1104 		dev_warn(dev, "invalid calibration data\n");  in mtk_thermal_get_calibration_data()
1105 		ret = -EINVAL;  in mtk_thermal_get_calibration_data()
1109 	switch (mt->conf->version) {  in mtk_thermal_get_calibration_data()
1120 		ret = -EINVAL;  in mtk_thermal_get_calibration_data()
1125 		dev_info(dev, "Device not calibrated, using default calibration values\n");  in mtk_thermal_get_calibration_data()
1137 		.compatible = "mediatek,mt8173-thermal",
1141 		.compatible = "mediatek,mt2701-thermal",
1145 		.compatible = "mediatek,mt2712-thermal",
1149 		.compatible = "mediatek,mt7622-thermal",
1153 		.compatible = "mediatek,mt7986-thermal",
1157 		.compatible = "mediatek,mt8183-thermal",
1161 		.compatible = "mediatek,mt8365-thermal",
1173 	if (!mt->conf->apmixed_buffer_ctl_reg)  in mtk_thermal_turn_on_buffer()
1176 	tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg);  in mtk_thermal_turn_on_buffer()
1177 	tmp &= mt->conf->apmixed_buffer_ctl_mask;  in mtk_thermal_turn_on_buffer()
1178 	tmp |= mt->conf->apmixed_buffer_ctl_set;  in mtk_thermal_turn_on_buffer()
1179 	writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg);  in mtk_thermal_turn_on_buffer()
1189 	writel(0x1, mt->thermal_base + TEMP_MONCTL0);  in mtk_thermal_release_periodic_ts()
1190 	tmp = readl(mt->thermal_base + TEMP_MSRCTL1);  in mtk_thermal_release_periodic_ts()
1191 	writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);  in mtk_thermal_release_periodic_ts()
1197 	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;  in mtk_thermal_probe()
1203 	mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);  in mtk_thermal_probe()
1205 		return -ENOMEM;  in mtk_thermal_probe()
1207 	mt->conf = of_device_get_match_data(&pdev->dev);  in mtk_thermal_probe()
1209 	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);  in mtk_thermal_probe()
1210 	if (IS_ERR(mt->thermal_base))  in mtk_thermal_probe()
1211 		return PTR_ERR(mt->thermal_base);  in mtk_thermal_probe()
1213 	ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);  in mtk_thermal_probe()
1217 	mutex_init(&mt->lock);  in mtk_thermal_probe()
1219 	mt->dev = &pdev->dev;  in mtk_thermal_probe()
1223 		dev_err(&pdev->dev, "missing auxadc node\n");  in mtk_thermal_probe()
1224 		return -ENODEV;  in mtk_thermal_probe()
1233 		dev_err(&pdev->dev, "Can't get auxadc phys address\n");  in mtk_thermal_probe()
1234 		return -EINVAL;  in mtk_thermal_probe()
1239 		dev_err(&pdev->dev, "missing apmixedsys node\n");  in mtk_thermal_probe()
1240 		return -ENODEV;  in mtk_thermal_probe()
1249 		dev_err(&pdev->dev, "Can't get auxadc phys address\n");  in mtk_thermal_probe()
1250 		return -EINVAL;  in mtk_thermal_probe()
1253 	ret = device_reset_optional(&pdev->dev);  in mtk_thermal_probe()
1257 	mt->clk_auxadc = devm_clk_get_enabled(&pdev->dev, "auxadc");  in mtk_thermal_probe()
1258 	if (IS_ERR(mt->clk_auxadc)) {  in mtk_thermal_probe()
1259 		ret = PTR_ERR(mt->clk_auxadc);  in mtk_thermal_probe()
1260 		dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);  in mtk_thermal_probe()
1264 	mt->clk_peri_therm = devm_clk_get_enabled(&pdev->dev, "therm");  in mtk_thermal_probe()
1265 	if (IS_ERR(mt->clk_peri_therm)) {  in mtk_thermal_probe()
1266 		ret = PTR_ERR(mt->clk_peri_therm);  in mtk_thermal_probe()
1267 		dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);  in mtk_thermal_probe()
1273 	if (mt->conf->version != MTK_THERMAL_V1)  in mtk_thermal_probe()
1276 	if (mt->conf->version == MTK_THERMAL_V1)  in mtk_thermal_probe()
1277 		mt->raw_to_mcelsius = raw_to_mcelsius_v1;  in mtk_thermal_probe()
1278 	else if (mt->conf->version == MTK_THERMAL_V2)  in mtk_thermal_probe()
1279 		mt->raw_to_mcelsius = raw_to_mcelsius_v2;  in mtk_thermal_probe()
1281 		mt->raw_to_mcelsius = raw_to_mcelsius_v3;  in mtk_thermal_probe()
1283 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)  in mtk_thermal_probe()
1284 		for (i = 0; i < mt->conf->num_banks; i++)  in mtk_thermal_probe()
1288 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,  in mtk_thermal_probe()
1293 	ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);  in mtk_thermal_probe()
1295 		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");  in mtk_thermal_probe()
1303 		.name = "mtk-thermal",
1315 MODULE_DESCRIPTION("Mediatek thermal driver");