1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
21 #define TER			0x0	/* TMU enable */
23 #define TRITSR			0x20	/* TMU immediate temp */
24 /* TMU calibration data registers */
52 /* TMU OCOTP calibration data bitfields */
72 #define VER2_TEMP_LOW_LIMIT	-40000
100 	struct imx8mm_tmu *tmu = sensor->priv;  in imx8mm_tmu_get_temp()  local
103 	val = readl_relaxed(tmu->base + TRITSR) & TRITSR_TEMP0_VAL_MASK;  in imx8mm_tmu_get_temp()
107 	 * ERR051272: TMU: Bit 31 of registers TMU_TSCR/TMU_TRITSR/TMU_TRATSR invalid  in imx8mm_tmu_get_temp()
112 		return -EAGAIN;  in imx8mm_tmu_get_temp()
120 	struct imx8mm_tmu *tmu = sensor->priv;  in imx8mp_tmu_get_temp()  local
124 	val = readl_relaxed(tmu->base + TRITSR);  in imx8mp_tmu_get_temp()
125 	ready = test_bit(probe_status_offset(sensor->hw_id), &val);  in imx8mp_tmu_get_temp()
127 		return -EAGAIN;  in imx8mp_tmu_get_temp()
129 	val = sensor->hw_id ? FIELD_GET(TRITSR_TEMP1_VAL_MASK, val) :  in imx8mp_tmu_get_temp()
136 		return -EAGAIN;  in imx8mp_tmu_get_temp()
144 	struct imx8mm_tmu *tmu = sensor->priv;  in tmu_get_temp()  local
146 	return tmu->socdata->get_temp(sensor, temp);  in tmu_get_temp()
153 static void imx8mm_tmu_enable(struct imx8mm_tmu *tmu, bool enable)  in imx8mm_tmu_enable()  argument
157 	val = readl_relaxed(tmu->base + TER);  in imx8mm_tmu_enable()
159 	if (tmu->socdata->version == TMU_VER2)  in imx8mm_tmu_enable()
161 	writel_relaxed(val, tmu->base + TER);  in imx8mm_tmu_enable()
164 static void imx8mm_tmu_probe_sel_all(struct imx8mm_tmu *tmu)  in imx8mm_tmu_probe_sel_all()  argument
168 	val = readl_relaxed(tmu->base + TPS);  in imx8mm_tmu_probe_sel_all()
170 	writel_relaxed(val, tmu->base + TPS);  in imx8mm_tmu_probe_sel_all()
174 					 struct imx8mm_tmu *tmu)  in imx8mm_tmu_probe_set_calib_v1()  argument
176 	struct device *dev = &pdev->dev;  in imx8mm_tmu_probe_set_calib_v1()
180 	ret = nvmem_cell_read_u32(&pdev->dev, "calib", &ana0);  in imx8mm_tmu_probe_set_calib_v1()
188 	       tmu->base + TASR);  in imx8mm_tmu_probe_set_calib_v1()
193 	       tmu->base + TCALIV(0));  in imx8mm_tmu_probe_set_calib_v1()
199 					 struct imx8mm_tmu *tmu)  in imx8mm_tmu_probe_set_calib_v2()  argument
201 	struct device *dev = &pdev->dev;  in imx8mm_tmu_probe_set_calib_v2()
223 		return -EINVAL;  in imx8mm_tmu_probe_set_calib_v2()
230 		       tmu->base + TCALIV(0));  in imx8mm_tmu_probe_set_calib_v2()
232 		       tmu->base + TCALIV(1));  in imx8mm_tmu_probe_set_calib_v2()
240 	       tmu->base + TASR);  in imx8mm_tmu_probe_set_calib_v2()
247 	       tmu->base + TRIM);  in imx8mm_tmu_probe_set_calib_v2()
254 	       tmu->base + TCALIV(0));  in imx8mm_tmu_probe_set_calib_v2()
260 	       tmu->base + TCALIV(1));  in imx8mm_tmu_probe_set_calib_v2()
266 	       tmu->base + TCALIV(2));  in imx8mm_tmu_probe_set_calib_v2()
272 				      struct imx8mm_tmu *tmu)  in imx8mm_tmu_probe_set_calib()  argument
274 	struct device *dev = &pdev->dev;  in imx8mm_tmu_probe_set_calib()
282 	if (!of_property_present(pdev->dev.of_node, "nvmem-cells")) {  in imx8mm_tmu_probe_set_calib()
284 …	 "No OCOTP nvmem reference found, SoC-specific calibration not loaded. Please update your DT.\n");  in imx8mm_tmu_probe_set_calib()
288 	if (tmu->socdata->version == TMU_VER1)  in imx8mm_tmu_probe_set_calib()
289 		return imx8mm_tmu_probe_set_calib_v1(pdev, tmu);  in imx8mm_tmu_probe_set_calib()
291 	return imx8mm_tmu_probe_set_calib_v2(pdev, tmu);  in imx8mm_tmu_probe_set_calib()
297 	struct imx8mm_tmu *tmu;  in imx8mm_tmu_probe()  local
301 	data = of_device_get_match_data(&pdev->dev);  in imx8mm_tmu_probe()
303 	tmu = devm_kzalloc(&pdev->dev, struct_size(tmu, sensors,  in imx8mm_tmu_probe()
304 			   data->num_sensors), GFP_KERNEL);  in imx8mm_tmu_probe()
305 	if (!tmu)  in imx8mm_tmu_probe()
306 		return -ENOMEM;  in imx8mm_tmu_probe()
308 	tmu->socdata = data;  in imx8mm_tmu_probe()
310 	tmu->base = devm_platform_ioremap_resource(pdev, 0);  in imx8mm_tmu_probe()
311 	if (IS_ERR(tmu->base))  in imx8mm_tmu_probe()
312 		return PTR_ERR(tmu->base);  in imx8mm_tmu_probe()
314 	tmu->clk = devm_clk_get(&pdev->dev, NULL);  in imx8mm_tmu_probe()
315 	if (IS_ERR(tmu->clk))  in imx8mm_tmu_probe()
316 		return dev_err_probe(&pdev->dev, PTR_ERR(tmu->clk),  in imx8mm_tmu_probe()
317 				     "failed to get tmu clock\n");  in imx8mm_tmu_probe()
319 	ret = clk_prepare_enable(tmu->clk);  in imx8mm_tmu_probe()
321 		dev_err(&pdev->dev, "failed to enable tmu clock: %d\n", ret);  in imx8mm_tmu_probe()
326 	imx8mm_tmu_enable(tmu, false);  in imx8mm_tmu_probe()
328 	for (i = 0; i < data->num_sensors; i++) {  in imx8mm_tmu_probe()
329 		tmu->sensors[i].priv = tmu;  in imx8mm_tmu_probe()
330 		tmu->sensors[i].tzd =  in imx8mm_tmu_probe()
331 			devm_thermal_of_zone_register(&pdev->dev, i,  in imx8mm_tmu_probe()
332 						      &tmu->sensors[i],  in imx8mm_tmu_probe()
334 		if (IS_ERR(tmu->sensors[i].tzd)) {  in imx8mm_tmu_probe()
335 			ret = PTR_ERR(tmu->sensors[i].tzd);  in imx8mm_tmu_probe()
336 			dev_err(&pdev->dev,  in imx8mm_tmu_probe()
341 		tmu->sensors[i].hw_id = i;  in imx8mm_tmu_probe()
343 		devm_thermal_add_hwmon_sysfs(&pdev->dev, tmu->sensors[i].tzd);  in imx8mm_tmu_probe()
346 	platform_set_drvdata(pdev, tmu);  in imx8mm_tmu_probe()
348 	ret = imx8mm_tmu_probe_set_calib(pdev, tmu);  in imx8mm_tmu_probe()
352 	/* enable all the probes for V2 TMU */  in imx8mm_tmu_probe()
353 	if (tmu->socdata->version == TMU_VER2)  in imx8mm_tmu_probe()
354 		imx8mm_tmu_probe_sel_all(tmu);  in imx8mm_tmu_probe()
357 	imx8mm_tmu_enable(tmu, true);  in imx8mm_tmu_probe()
362 	clk_disable_unprepare(tmu->clk);  in imx8mm_tmu_probe()
368 	struct imx8mm_tmu *tmu = platform_get_drvdata(pdev);  in imx8mm_tmu_remove()  local
370 	/* disable TMU */  in imx8mm_tmu_remove()
371 	imx8mm_tmu_enable(tmu, false);  in imx8mm_tmu_remove()
373 	clk_disable_unprepare(tmu->clk);  in imx8mm_tmu_remove()
390 	{ .compatible = "fsl,imx8mm-tmu", .data = &imx8mm_tmu_data, },
391 	{ .compatible = "fsl,imx8mp-tmu", .data = &imx8mp_tmu_data, },