Lines Matching +full:high +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #define EN7581_SENSE3_EN BIT(3)
24 #define EN7581_SENSE2_EN BIT(2)
25 #define EN7581_SENSE1_EN BIT(1)
26 #define EN7581_SENSE0_EN BIT(0)
28 /* period unit calculated in BUS clock * 256 scaling-up */
34 #define EN7581_STAGE3_INT_EN BIT(31)
35 #define EN7581_STAGE2_INT_EN BIT(30)
36 #define EN7581_STAGE1_INT_EN BIT(29)
37 #define EN7581_FILTER_INT_EN_3 BIT(28)
38 #define EN7581_IMMD_INT_EN3 BIT(27)
39 #define EN7581_NOHOTINTEN3 BIT(26)
40 #define EN7581_HOFSINTEN3 BIT(25)
41 #define EN7581_LOFSINTEN3 BIT(24)
42 #define EN7581_HINTEN3 BIT(23)
43 #define EN7581_CINTEN3 BIT(22)
44 #define EN7581_FILTER_INT_EN_2 BIT(21)
45 #define EN7581_FILTER_INT_EN_1 BIT(20)
46 #define EN7581_FILTER_INT_EN_0 BIT(19)
47 #define EN7581_IMMD_INT_EN2 BIT(18)
48 #define EN7581_IMMD_INT_EN1 BIT(17)
49 #define EN7581_IMMD_INT_EN0 BIT(16)
50 #define EN7581_TIME_OUT_INT_EN BIT(15)
51 #define EN7581_NOHOTINTEN2 BIT(14)
52 #define EN7581_HOFSINTEN2 BIT(13)
53 #define EN7581_LOFSINTEN2 BIT(12)
54 #define EN7581_HINTEN2 BIT(11)
55 #define EN7581_CINTEN2 BIT(10)
56 #define EN7581_NOHOTINTEN1 BIT(9)
57 #define EN7581_HOFSINTEN1 BIT(8)
58 #define EN7581_LOFSINTEN1 BIT(7)
59 #define EN7581_HINTEN1 BIT(6)
60 #define EN7581_CINTEN1 BIT(5)
61 #define EN7581_NOHOTINTEN0 BIT(4)
63 #define EN7581_LOFSINTEN0 BIT(3) /* In documentation: BIT(2) */
64 #define EN7581_HOFSINTEN0 BIT(2) /* In documentation: BIT(3) */
66 * - Fire BIT(1) when lower than EN7581_COLD_THRE
67 * - Fire BIT(0) and BIT(5) when higher than EN7581_HOT2NORMAL_THRE or
70 #define EN7581_CINTEN0 BIT(1) /* In documentation: BIT(0) */
71 #define EN7581_HINTEN0 BIT(0) /* In documentation: BIT(1) */
73 #define EN7581_STAGE3_INT_STAT BIT(31)
74 #define EN7581_STAGE2_INT_STAT BIT(30)
75 #define EN7581_STAGE1_INT_STAT BIT(29)
76 #define EN7581_FILTER_INT_STAT_3 BIT(28)
77 #define EN7581_IMMD_INT_STS3 BIT(27)
78 #define EN7581_NOHOTINTSTS3 BIT(26)
79 #define EN7581_HOFSINTSTS3 BIT(25)
80 #define EN7581_LOFSINTSTS3 BIT(24)
81 #define EN7581_HINTSTS3 BIT(23)
82 #define EN7581_CINTSTS3 BIT(22)
83 #define EN7581_FILTER_INT_STAT_2 BIT(21)
84 #define EN7581_FILTER_INT_STAT_1 BIT(20)
85 #define EN7581_FILTER_INT_STAT_0 BIT(19)
86 #define EN7581_IMMD_INT_STS2 BIT(18)
87 #define EN7581_IMMD_INT_STS1 BIT(17)
88 #define EN7581_IMMD_INT_STS0 BIT(16)
89 #define EN7581_TIME_OUT_INT_STAT BIT(15)
90 #define EN7581_NOHOTINTSTS2 BIT(14)
91 #define EN7581_HOFSINTSTS2 BIT(13)
92 #define EN7581_LOFSINTSTS2 BIT(12)
93 #define EN7581_HINTSTS2 BIT(11)
94 #define EN7581_CINTSTS2 BIT(10)
95 #define EN7581_NOHOTINTSTS1 BIT(9)
96 #define EN7581_HOFSINTSTS1 BIT(8)
97 #define EN7581_LOFSINTSTS1 BIT(7)
98 #define EN7581_HINTSTS1 BIT(6)
99 #define EN7581_CINTSTS1 BIT(5)
100 #define EN7581_NOHOTINTSTS0 BIT(4)
102 #define EN7581_LOFSINTSTS0 BIT(3) /* In documentation: BIT(2) */
103 #define EN7581_HOFSINTSTS0 BIT(2) /* In documentation: BIT(3) */
105 * - Fire BIT(1) when lower than EN7581_COLD_THRE
106 * - Fire BIT(0) and BIT(5) when higher than EN7581_HOT2NORMAL_THRE or
111 #define EN7581_CINTSTS0 BIT(1) /* In documentation: BIT(0) */
112 #define EN7581_HINTSTS0 BIT(0) /* In documentation: BIT(1)*/
127 /* Also LOW and HIGH offset register are swapped */
147 #define EN7581_RD_CTRL_DIFF BIT(0)
149 #define EN7581_ADV_RD_VALID_POLARITY BIT(5)
156 * - 1 sample
157 * - 2 sample and make average of them
158 * - 4,6,10,16 sample, drop max and min and make average of them
184 /* Convert temp to raw value as read from ADC ((((temp / 100) - init) * slope) / 1000) + offset */
185 #define TEMP_TO_RAW(priv, temp) ((((((temp) / 100) - (priv)->init_temp) * \
186 (priv)->default_slope) / 1000) + \
187 (priv)->default_offset)
189 /* Convert raw to temp ((((temp - offset) * 1000) / slope + init) * 100) */
190 #define RAW_TO_TEMP(priv, raw) (((((raw) - (priv)->default_offset) * 1000) / \
191 (priv)->default_slope + \
192 (priv)->init_temp) * 100)
211 regmap_read(priv->chip_scu, EN7581_DOUT_TADC, &val); in airoha_get_thermal_ADC()
220 regmap_read(priv->chip_scu, EN7581_PLLRG_PROTECT, &pllrg); in airoha_init_thermal_ADC_mode()
223 regmap_write(priv->chip_scu, EN7581_PLLRG_PROTECT, EN7581_SCU_THERMAL_PROTECT_KEY); in airoha_init_thermal_ADC_mode()
225 regmap_write(priv->chip_scu, EN7581_PWD_TADC, adc_mux); in airoha_init_thermal_ADC_mode()
228 regmap_write(priv->chip_scu, EN7581_PLLRG_PROTECT, pllrg); in airoha_init_thermal_ADC_mode()
249 avg_value -= (min_value + max_value); in airoha_thermal_get_temp()
250 avg_value /= AIROHA_MAX_SAMPLES - 2; in airoha_thermal_get_temp()
257 int high) in airoha_thermal_set_trips() argument
262 if (high != INT_MAX) { in airoha_thermal_set_trips()
263 /* Validate high and clamp it a supported value */ in airoha_thermal_set_trips()
264 high = clamp_t(int, high, RAW_TO_TEMP(priv, 0), in airoha_thermal_set_trips()
267 /* We offset the high temp of 1°C to trigger correct event */ in airoha_thermal_set_trips()
268 writel(TEMP_TO_RAW(priv, high) >> 4, in airoha_thermal_set_trips()
269 priv->base + EN7581_TEMPOFFSETH); in airoha_thermal_set_trips()
274 if (low != -INT_MAX) { in airoha_thermal_set_trips()
276 low = clamp_t(int, high, RAW_TO_TEMP(priv, 0), in airoha_thermal_set_trips()
281 priv->base + EN7581_TEMPOFFSETL); in airoha_thermal_set_trips()
288 writel(EN7581_SENSE0_EN, priv->base + EN7581_TEMPMONCTL0); in airoha_thermal_set_trips()
305 status = readl(priv->base + EN7581_TEMPMONINTSTS); in airoha_thermal_irq()
321 writel(status, priv->base + EN7581_TEMPMONINTSTS); in airoha_thermal_irq()
324 thermal_zone_device_update(priv->tz, event); in airoha_thermal_irq()
339 efuse_calib_info = readl(priv->base + EN7581_EFUSE_TEMP_OFFSET_REG); in airoha_thermal_setup_adc_val()
341 priv->default_offset = FIELD_GET(EN7581_EFUSE_TEMP_OFFSET, efuse_calib_info); in airoha_thermal_setup_adc_val()
343 cpu_sensor = readl(priv->base + EN7581_EFUSE_TEMP_CPU_SENSOR_REG); in airoha_thermal_setup_adc_val()
345 priv->default_slope = EN7581_SLOPE_X100_DIO_DEFAULT; in airoha_thermal_setup_adc_val()
346 priv->init_temp = EN7581_INIT_TEMP_FTK_X10; in airoha_thermal_setup_adc_val()
348 priv->default_slope = EN7581_SLOPE_X100_DIO_AVS; in airoha_thermal_setup_adc_val()
349 priv->init_temp = EN7581_INIT_TEMP_CPK_X10; in airoha_thermal_setup_adc_val()
352 priv->default_offset = airoha_get_thermal_ADC(priv); in airoha_thermal_setup_adc_val()
353 priv->default_slope = EN7581_SLOPE_X100_DIO_DEFAULT; in airoha_thermal_setup_adc_val()
354 priv->init_temp = EN7581_INIT_TEMP_NONK_X10; in airoha_thermal_setup_adc_val()
363 priv->base + EN7581_TEMPMSRCTL0); in airoha_thermal_setup_monitor()
378 writel(priv->scu_adc_res.start + EN7581_DOUT_TADC, in airoha_thermal_setup_monitor()
379 priv->base + EN7581_TEMPADCVALIDADDR); in airoha_thermal_setup_monitor()
382 * Configure valid bit on a fake value of bit 16. The ADC outputs in airoha_thermal_setup_monitor()
386 priv->base + EN7581_TEMPADCVALIDMASK); in airoha_thermal_setup_monitor()
390 * value 4 bit to the right. Precision lost by this is minimal in airoha_thermal_setup_monitor()
395 priv->base + EN7581_TEMPADCVOLTAGESHIFT); in airoha_thermal_setup_monitor()
399 priv->base + EN7581_TEMPMONCTL1); in airoha_thermal_setup_monitor()
407 priv->base + EN7581_TEMPMONCTL2); in airoha_thermal_setup_monitor()
411 priv->base + EN7581_TEMPAHBPOLL); in airoha_thermal_setup_monitor()
418 struct device *dev = &pdev->dev; in airoha_thermal_probe()
423 return -ENOMEM; in airoha_thermal_probe()
425 priv->base = devm_platform_ioremap_resource(pdev, 0); in airoha_thermal_probe()
426 if (IS_ERR(priv->base)) in airoha_thermal_probe()
427 return PTR_ERR(priv->base); in airoha_thermal_probe()
429 chip_scu_np = of_parse_phandle(dev->of_node, "airoha,chip-scu", 0); in airoha_thermal_probe()
431 return -EINVAL; in airoha_thermal_probe()
433 priv->chip_scu = syscon_node_to_regmap(chip_scu_np); in airoha_thermal_probe()
434 if (IS_ERR(priv->chip_scu)) in airoha_thermal_probe()
435 return PTR_ERR(priv->chip_scu); in airoha_thermal_probe()
437 of_address_to_resource(chip_scu_np, 0, &priv->scu_adc_res); in airoha_thermal_probe()
444 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in airoha_thermal_probe()
446 pdev->name, priv); in airoha_thermal_probe()
456 priv->tz = devm_thermal_of_zone_register(dev, 0, priv, &thdev_ops); in airoha_thermal_probe()
457 if (IS_ERR(priv->tz)) { in airoha_thermal_probe()
459 return PTR_ERR(priv->tz); in airoha_thermal_probe()
464 /* Enable LOW and HIGH interrupt */ in airoha_thermal_probe()
466 priv->base + EN7581_TEMPMONINT); in airoha_thermal_probe()
472 { .compatible = "airoha,en7581-thermal" },
479 .name = "airoha-thermal",