Lines Matching +full:0 +full:x838
15 #define EN7581_PLLRG_PROTECT 0x268
16 #define EN7581_PWD_TADC 0x2ec
18 #define EN7581_DOUT_TADC 0x2f8
19 #define EN7581_DOUT_TADC_MASK GENMASK(15, 0)
22 #define EN7581_TEMPMONCTL0 0x800
26 #define EN7581_SENSE0_EN BIT(0)
27 #define EN7581_TEMPMONCTL1 0x804
29 #define EN7581_PERIOD_UNIT GENMASK(9, 0)
30 #define EN7581_TEMPMONCTL2 0x808
32 #define EN7581_SEN_INTERVAL GENMASK(9, 0)
33 #define EN7581_TEMPMONINT 0x80C
67 * - Fire BIT(0) and BIT(5) when higher than EN7581_HOT2NORMAL_THRE or
70 #define EN7581_CINTEN0 BIT(1) /* In documentation: BIT(0) */
71 #define EN7581_HINTEN0 BIT(0) /* In documentation: BIT(1) */
72 #define EN7581_TEMPMONINTSTS 0x810
106 * - Fire BIT(0) and BIT(5) when higher than EN7581_HOT2NORMAL_THRE or
111 #define EN7581_CINTSTS0 BIT(1) /* In documentation: BIT(0) */
112 #define EN7581_HINTSTS0 BIT(0) /* In documentation: BIT(1)*/
119 #define EN7581_TEMPH2NTHRE 0x824
121 #define EN7581_HOT2NORMAL_THRE GENMASK(11, 0)
122 #define EN7581_TEMPHTHRE 0x828
123 #define EN7581_HOT_THRE GENMASK(11, 0)
125 #define EN7581_TEMPCTHRE 0x82c
126 #define EN7581_COLD_THRE GENMASK(11, 0)
128 #define EN7581_TEMPOFFSETL 0x830 /* In documentation: 0x834 */
129 #define EN7581_LOW_OFFSET GENMASK(11, 0)
130 #define EN7581_TEMPOFFSETH 0x834 /* In documentation: 0x830 */
131 #define EN7581_HIGH_OFFSET GENMASK(11, 0)
132 #define EN7581_TEMPMSRCTL0 0x838
136 #define EN7581_MSRCTL0 GENMASK(2, 0)
137 #define EN7581_TEMPADCVALIDADDR 0x878
138 #define EN7581_ADC_VALID_ADDR GENMASK(31, 0)
139 #define EN7581_TEMPADCVOLTADDR 0x87c
140 #define EN7581_ADC_VOLT_ADDR GENMASK(31, 0)
141 #define EN7581_TEMPRDCTRL 0x880
143 * NOTICE: AHB have this set to 0 by default. Means that
147 #define EN7581_RD_CTRL_DIFF BIT(0)
148 #define EN7581_TEMPADCVALIDMASK 0x884
150 #define EN7581_ADV_RD_VALID_POS GENMASK(4, 0)
151 #define EN7581_TEMPADCVOLTAGESHIFT 0x888
152 #define EN7581_ADC_VOLTAGE_SHIFT GENMASK(4, 0)
160 #define EN7581_MSRCTL_1SAMPLE 0x0
161 #define EN7581_MSRCTL_AVG2SAMPLE 0x1
162 #define EN7581_MSRCTL_4SAMPLE_MAX_MIX_AVG2 0x2
163 #define EN7581_MSRCTL_6SAMPLE_MAX_MIX_AVG4 0x3
164 #define EN7581_MSRCTL_10SAMPLE_MAX_MIX_AVG8 0x4
165 #define EN7581_MSRCTL_18SAMPLE_MAX_MIX_AVG16 0x5
166 #define EN7581_TEMPAHBPOLL 0x840
167 #define EN7581_ADC_POLL_INTVL GENMASK(31, 0)
169 #define EN7581_EFUSE_TEMP_OFFSET_REG 0xf20 /* PTPSPARE0 */
171 #define EN7581_PTPSPARE1 0xf24 /* PTPSPARE1 */
172 #define EN7581_EFUSE_TEMP_CPU_SENSOR_REG 0xf28 /* PTPSPARE2 */
181 #define EN7581_SCU_THERMAL_PROTECT_KEY 0x12
182 #define EN7581_SCU_THERMAL_MUX_DIODE1 0x7
237 avg_value = 0; in airoha_thermal_get_temp()
241 for (i = 0; i < AIROHA_MAX_SAMPLES; i++) { in airoha_thermal_get_temp()
253 return 0; in airoha_thermal_get_temp()
264 high = clamp_t(int, high, RAW_TO_TEMP(priv, 0), in airoha_thermal_set_trips()
276 low = clamp_t(int, high, RAW_TO_TEMP(priv, 0), in airoha_thermal_set_trips()
286 /* Enable sensor 0 monitor after trip are set */ in airoha_thermal_set_trips()
290 return 0; in airoha_thermal_set_trips()
425 priv->base = devm_platform_ioremap_resource(pdev, 0); in airoha_thermal_probe()
429 chip_scu_np = of_parse_phandle(dev->of_node, "airoha,chip-scu", 0); in airoha_thermal_probe()
437 of_address_to_resource(chip_scu_np, 0, &priv->scu_adc_res); in airoha_thermal_probe()
440 irq = platform_get_irq(pdev, 0); in airoha_thermal_probe()
441 if (irq < 0) in airoha_thermal_probe()
456 priv->tz = devm_thermal_of_zone_register(dev, 0, priv, &thdev_ops); in airoha_thermal_probe()
468 return 0; in airoha_thermal_probe()