Lines Matching +full:switch +full:- +full:freq
51 u16 freq; /* Crystal frequency in kHz.*/ member
58 { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
59 { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
60 { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
61 { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
62 { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
63 { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
64 { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
65 { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
66 { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, },
67 { .freq = 25000, .xf = 10, .wb_int = 70, .wb_frac = 419430, },
68 { .freq = 26000, .xf = 11, .wb_int = 67, .wb_frac = 725937, },
69 { .freq = 30000, .xf = 12, .wb_int = 58, .wb_frac = 699050, },
70 { .freq = 38400, .xf = 13, .wb_int = 45, .wb_frac = 873813, },
71 { .freq = 40000, .xf = 14, .wb_int = 45, .wb_frac = 0, },
82 if (e->freq == crystalfreq) in pmu0_plltab_find_entry()
93 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu0_pllinit_r0()
103 crystalfreq = e->freq; in ssb_pmu0_pllinit_r0()
104 cc->pmu.crystalfreq = e->freq; in ssb_pmu0_pllinit_r0()
108 if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) { in ssb_pmu0_pllinit_r0()
113 dev_info(cc->dev->dev, "Programming PLL to %u.%03u MHz\n", in ssb_pmu0_pllinit_r0()
117 switch (bus->chip_id) { in ssb_pmu0_pllinit_r0()
133 for (i = 1500; i; i--) { in ssb_pmu0_pllinit_r0()
141 dev_emerg(cc->dev->dev, "Failed to turn the PLL off!\n"); in ssb_pmu0_pllinit_r0()
155 pllctl |= ((u32)e->wb_int << SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_IMSK; in ssb_pmu0_pllinit_r0()
156 pllctl |= ((u32)e->wb_frac << SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_FMSK; in ssb_pmu0_pllinit_r0()
157 if (e->wb_frac == 0) in ssb_pmu0_pllinit_r0()
164 …pllctl |= (((u32)e->wb_int >> 4) << SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT) & SSB_PMU0_PLLCTL2_WILD_IM… in ssb_pmu0_pllinit_r0()
170 pmuctl |= (((crystalfreq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT) in ssb_pmu0_pllinit_r0()
173 pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ; in ssb_pmu0_pllinit_r0()
178 u16 freq; /* Crystal frequency in kHz.*/ member
187 { .freq = 12000, .xf = 1, .p1div = 3, .p2div = 22, .ndiv_int = 0x9, .ndiv_frac = 0xFFFFEF, },
188 { .freq = 13000, .xf = 2, .p1div = 1, .p2div = 6, .ndiv_int = 0xb, .ndiv_frac = 0x483483, },
189 { .freq = 14400, .xf = 3, .p1div = 1, .p2div = 10, .ndiv_int = 0xa, .ndiv_frac = 0x1C71C7, },
190 { .freq = 15360, .xf = 4, .p1div = 1, .p2div = 5, .ndiv_int = 0xb, .ndiv_frac = 0x755555, },
191 { .freq = 16200, .xf = 5, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x6E9E06, },
192 { .freq = 16800, .xf = 6, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x3CF3CF, },
193 { .freq = 19200, .xf = 7, .p1div = 1, .p2div = 9, .ndiv_int = 0x5, .ndiv_frac = 0x17B425, },
194 { .freq = 19800, .xf = 8, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0xA57EB, },
195 { .freq = 20000, .xf = 9, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0, },
196 { .freq = 24000, .xf = 10, .p1div = 3, .p2div = 11, .ndiv_int = 0xa, .ndiv_frac = 0, },
197 { .freq = 25000, .xf = 11, .p1div = 5, .p2div = 16, .ndiv_int = 0xb, .ndiv_frac = 0, },
198 { .freq = 26000, .xf = 12, .p1div = 1, .p2div = 2, .ndiv_int = 0x10, .ndiv_frac = 0xEC4EC4, },
199 { .freq = 30000, .xf = 13, .p1div = 3, .p2div = 8, .ndiv_int = 0xb, .ndiv_frac = 0, },
200 { .freq = 38400, .xf = 14, .p1div = 1, .p2div = 5, .ndiv_int = 0x4, .ndiv_frac = 0x955555, },
201 { .freq = 40000, .xf = 15, .p1div = 1, .p2div = 2, .ndiv_int = 0xb, .ndiv_frac = 0, },
213 if (e->freq == crystalfreq) in pmu1_plltab_find_entry()
224 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu1_pllinit_r0()
230 if (bus->chip_id == 0x4312) { in ssb_pmu1_pllinit_r0()
232 * the default crystal settings work out-of-the-box. */ in ssb_pmu1_pllinit_r0()
233 cc->pmu.crystalfreq = 20000; in ssb_pmu1_pllinit_r0()
242 crystalfreq = e->freq; in ssb_pmu1_pllinit_r0()
243 cc->pmu.crystalfreq = e->freq; in ssb_pmu1_pllinit_r0()
247 if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) { in ssb_pmu1_pllinit_r0()
252 dev_info(cc->dev->dev, "Programming PLL to %u.%03u MHz\n", in ssb_pmu1_pllinit_r0()
256 switch (bus->chip_id) { in ssb_pmu1_pllinit_r0()
270 for (i = 1500; i; i--) { in ssb_pmu1_pllinit_r0()
278 dev_emerg(cc->dev->dev, "Failed to turn the PLL off!\n"); in ssb_pmu1_pllinit_r0()
283 pllctl |= ((u32)e->p1div << SSB_PMU1_PLLCTL0_P1DIV_SHIFT) & SSB_PMU1_PLLCTL0_P1DIV; in ssb_pmu1_pllinit_r0()
284 pllctl |= ((u32)e->p2div << SSB_PMU1_PLLCTL0_P2DIV_SHIFT) & SSB_PMU1_PLLCTL0_P2DIV; in ssb_pmu1_pllinit_r0()
290 pllctl |= ((u32)e->ndiv_int << SSB_PMU1_PLLCTL2_NDIVINT_SHIFT) & SSB_PMU1_PLLCTL2_NDIVINT; in ssb_pmu1_pllinit_r0()
297 pllctl |= ((u32)e->ndiv_frac << SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT) & SSB_PMU1_PLLCTL3_NDIVFRAC; in ssb_pmu1_pllinit_r0()
311 pmuctl |= ((((u32)e->freq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT) in ssb_pmu1_pllinit_r0()
313 pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ; in ssb_pmu1_pllinit_r0()
319 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_pll_init()
320 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */ in ssb_pmu_pll_init()
322 if (bus->bustype == SSB_BUSTYPE_SSB) { in ssb_pmu_pll_init()
330 switch (bus->chip_id) { in ssb_pmu_pll_init()
344 if (cc->pmu.rev == 2) { in ssb_pmu_pll_init()
352 dev_err(cc->dev->dev, "ERROR: PLL init unknown for device %04X\n", in ssb_pmu_pll_init()
353 bus->chip_id); in ssb_pmu_pll_init()
413 /* Adjust HT-Available dependencies. */
425 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_resources_init()
433 switch (bus->chip_id) { in ssb_pmu_resources_init()
474 dev_err(cc->dev->dev, "ERROR: PMU resource config unknown for device %04X\n", in ssb_pmu_resources_init()
475 bus->chip_id); in ssb_pmu_resources_init()
490 switch (depend_tab[i].task) { in ssb_pmu_resources_init()
516 /* https://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
521 if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU)) in ssb_pmu_init()
525 cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION); in ssb_pmu_init()
527 dev_dbg(cc->dev->dev, "Found rev %u PMU (capabilities 0x%08X)\n", in ssb_pmu_init()
528 cc->pmu.rev, pmucap); in ssb_pmu_init()
530 if (cc->pmu.rev == 1) in ssb_pmu_init()
543 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_set_ldo_voltage()
546 switch (bus->chip_id) { in ssb_pmu_set_ldo_voltage()
549 switch (id) { in ssb_pmu_set_ldo_voltage()
592 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_set_ldo_paref()
595 switch (bus->chip_id) { in ssb_pmu_set_ldo_paref()
613 chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read? in ssb_pmu_set_ldo_paref()
628 return e->freq * 1000; in ssb_pmu_get_alp_clock_clk0()
633 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_get_alp_clock()
635 switch (bus->chip_id) { in ssb_pmu_get_alp_clock()
639 dev_err(cc->dev->dev, "ERROR: PMU alp clock unknown for device %04X\n", in ssb_pmu_get_alp_clock()
640 bus->chip_id); in ssb_pmu_get_alp_clock()
647 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_get_cpu_clock()
649 switch (bus->chip_id) { in ssb_pmu_get_cpu_clock()
654 dev_err(cc->dev->dev, "ERROR: PMU cpu clock unknown for device %04X\n", in ssb_pmu_get_cpu_clock()
655 bus->chip_id); in ssb_pmu_get_cpu_clock()
662 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_get_controlclock()
664 switch (bus->chip_id) { in ssb_pmu_get_controlclock()
668 dev_err(cc->dev->dev, "ERROR: PMU controlclock unknown for device %04X\n", in ssb_pmu_get_controlclock()
669 bus->chip_id); in ssb_pmu_get_controlclock()
678 switch (cc->dev->bus->chip_id) { in ssb_pmu_spuravoid_pllupdate()
708 dev_err(cc->dev->dev, in ssb_pmu_spuravoid_pllupdate()
710 cc->dev->bus->chip_id); in ssb_pmu_spuravoid_pllupdate()