Lines Matching +full:tx +full:- +full:clk +full:- +full:tap +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
119 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
160 * struct qspi_platform_data - zynqmp qspi platform data structure
168 * struct zynqmp_qspi - Defines qspi driver instance
175 * @txbuf: Pointer to the TX buffer
193 struct clk *refclk;
194 struct clk *pclk;
214 * zynqmp_gqspi_read - For GQSPI controller read operation
221 return readl_relaxed(xqspi->regs + offset);
225 * zynqmp_gqspi_write - For GQSPI controller write operation
233 writel_relaxed(val, (xqspi->regs + offset));
237 * zynqmp_gqspi_selecttarget - For selection of target device
240 * @targetbus: To check which bus is selected- upper or lower
253 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
257 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
260 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
263 dev_warn(instanceptr->dev, "Invalid target select\n");
269 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
273 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
276 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
279 dev_warn(instanceptr->dev, "Invalid target bus\n");
284 * zynqmp_qspi_set_tapdelay: To configure qspi tap delays
293 clk_rate = clk_get_rate(xqspi->refclk);
296 if (!xqspi->has_tapdelay) {
334 * zynqmp_qspi_init_hw - Initialize the hardware
339 * - Host mode
340 * - TX threshold set to 1
341 * - RX threshold set to 1
342 * - Flash memory interface mode enabled
344 * - Disable and clear all the interrupts
345 * - Enable manual target select
346 * - Enable manual start
347 * - Deselect all the chip select lines
348 * - Set the little endian mode of TX FIFO
349 * - Set clock phase
350 * - Set clock polarity and
351 * - Enable the QSPI controller
388 /* Clear pre-scalar by default */
391 if (xqspi->ctlr->mode_bits & SPI_CPHA)
396 if (xqspi->ctlr->mode_bits & SPI_CPOL)
402 clk_rate = clk_get_rate(xqspi->refclk);
405 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > xqspi->speed_hz)
416 /* Clear the TX and RX FIFO */
441 * zynqmp_qspi_copy_read_data - Copy data to RX buffer
449 memcpy(xqspi->rxbuf, &data, size);
450 xqspi->rxbuf += size;
451 xqspi->bytes_to_receive -= size;
455 * zynqmp_qspi_chipselect - Select or deselect the chip select line
461 struct zynqmp_qspi *xqspi = spi_controller_get_devdata(qspi->controller);
469 xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
470 xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
472 xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
473 xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER;
475 genfifoentry |= xqspi->genfifobus;
476 genfifoentry |= xqspi->genfifocs;
502 dev_err(xqspi->dev, "Chip select timed out\n");
506 * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
508 * @spimode: spimode - SPI or DUAL or QUAD.
527 dev_warn(xqspi->dev, "Invalid SPI mode\n");
534 * zynqmp_qspi_config_op - Configure QSPI controller for specified
546 * obtained using the pre-scalar value, the driver sets the clock
560 req_speed_hz = op->max_freq;
562 if (xqspi->speed_hz != req_speed_hz) {
563 xqspi->speed_hz = req_speed_hz;
567 clk_rate = clk_get_rate(xqspi->refclk);
583 dev_dbg(xqspi->dev, "config speed %u\n", req_speed_hz);
588 * zynqmp_qspi_setup_op - Configure the QSPI controller
598 struct spi_controller *ctlr = qspi->controller;
601 if (ctlr->busy)
602 return -EBUSY;
610 * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
614 * @size: Number of bytes to be copied from TX buffer to TX FIFO
620 while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) {
621 if (xqspi->bytes_to_transfer >= 4) {
622 memcpy(&intermediate, xqspi->txbuf, 4);
623 xqspi->txbuf += 4;
624 xqspi->bytes_to_transfer -= 4;
627 memcpy(&intermediate, xqspi->txbuf,
628 xqspi->bytes_to_transfer);
629 xqspi->txbuf += xqspi->bytes_to_transfer;
630 xqspi->bytes_to_transfer = 0;
631 count += xqspi->bytes_to_transfer;
638 * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
648 while ((count < size) && (xqspi->bytes_to_receive > 0)) {
649 if (xqspi->bytes_to_receive >= 4) {
650 (*(u32 *)xqspi->rxbuf) =
652 xqspi->rxbuf += 4;
653 xqspi->bytes_to_receive -= 4;
657 count += xqspi->bytes_to_receive;
659 xqspi->bytes_to_receive);
660 xqspi->bytes_to_receive = 0;
666 * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
678 if (xqspi->rxbuf) {
680 if (xqspi->mode == GQSPI_MODE_DMA)
681 transfer_len = xqspi->dma_rx_bytes;
683 transfer_len = xqspi->bytes_to_receive;
685 transfer_len = xqspi->bytes_to_transfer;
688 if (xqspi->txbuf)
692 xqspi->genfifoentry = genfifoentry;
693 dev_dbg(xqspi->dev, "genfifo %05x transfer_len %u\n",
716 if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf)
721 * zynqmp_qspi_disable_dma() - Disable DMA mode
730 xqspi->mode = GQSPI_MODE_IO;
734 * zynqmp_qspi_enable_dma() - Enable DMA mode
744 xqspi->mode = GQSPI_MODE_DMA;
748 * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
758 dma_unmap_single(xqspi->dev, xqspi->dma_addr,
759 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
760 xqspi->rxbuf += xqspi->dma_rx_bytes;
761 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
762 xqspi->dma_rx_bytes = 0;
768 if (xqspi->bytes_to_receive > 0) {
773 genfifoentry = xqspi->genfifoentry;
774 genfifoentry |= xqspi->bytes_to_receive;
795 * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
799 * This function handles TX empty only.
800 * On TX empty interrupt this function reads the received data from RX FIFO
801 * and fills the TX FIFO if there is any data remaining to be transferred.
816 if (xqspi->mode == GQSPI_MODE_DMA) {
835 if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
838 complete(&xqspi->data_completion);
844 * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
853 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
855 if (xqspi->bytes_to_receive < 8 ||
859 xqspi->dma_rx_bytes = 0;
863 rx_rem = xqspi->bytes_to_receive % 4;
864 rx_bytes = (xqspi->bytes_to_receive - rx_rem);
866 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
868 if (dma_mapping_error(xqspi->dev, addr)) {
869 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
870 return -ENOMEM;
873 xqspi->dma_rx_bytes = rx_bytes;
874 xqspi->dma_addr = addr;
890 * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
891 * TX FIFO, and fills the TX FIFO with as many
903 if (xqspi->mode == GQSPI_MODE_DMA)
908 * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
931 * zynqmp_qspi_suspend - Suspend method for the QSPI driver
941 struct spi_controller *ctlr = xqspi->ctlr;
954 * zynqmp_qspi_resume - Resume method for the QSPI driver
965 struct spi_controller *ctlr = xqspi->ctlr;
975 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
986 clk_disable_unprepare(xqspi->refclk);
987 clk_disable_unprepare(xqspi->pclk);
993 * zynqmp_runtime_resume - Runtime resume method for the SPI driver
1005 ret = clk_prepare_enable(xqspi->pclk);
1011 ret = clk_prepare_enable(xqspi->refclk);
1014 clk_disable_unprepare(xqspi->pclk);
1028 bits * xqspi->speed_hz);
1034 * zynqmp_qspi_exec_op() - Initiates the QSPI transfer
1048 spi_controller_get_devdata(mem->spi->controller);
1052 u16 opcode = op->cmd.opcode;
1055 mutex_lock(&xqspi->op_lock);
1057 zynqmp_qspi_chipselect(mem->spi, false);
1058 genfifoentry |= xqspi->genfifocs;
1059 genfifoentry |= xqspi->genfifobus;
1061 if (op->cmd.opcode) {
1062 reinit_completion(&xqspi->data_completion);
1063 xqspi->txbuf = &opcode;
1064 xqspi->rxbuf = NULL;
1065 xqspi->bytes_to_transfer = op->cmd.nbytes;
1066 xqspi->bytes_to_receive = 0;
1067 zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);
1074 timeout = zynqmp_qspi_timeout(xqspi, op->cmd.buswidth,
1075 op->cmd.nbytes);
1076 if (!wait_for_completion_timeout(&xqspi->data_completion,
1078 err = -ETIMEDOUT;
1083 if (op->addr.nbytes) {
1084 xqspi->txbuf = &opaddr;
1085 for (i = 0; i < op->addr.nbytes; i++) {
1086 *(((u8 *)xqspi->txbuf) + i) = op->addr.val >>
1087 (8 * (op->addr.nbytes - i - 1));
1090 reinit_completion(&xqspi->data_completion);
1091 xqspi->rxbuf = NULL;
1092 xqspi->bytes_to_transfer = op->addr.nbytes;
1093 xqspi->bytes_to_receive = 0;
1094 zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);
1103 timeout = zynqmp_qspi_timeout(xqspi, op->addr.buswidth,
1104 op->addr.nbytes);
1105 if (!wait_for_completion_timeout(&xqspi->data_completion,
1107 err = -ETIMEDOUT;
1112 if (op->dummy.nbytes) {
1113 xqspi->txbuf = NULL;
1114 xqspi->rxbuf = NULL;
1116 * xqspi->bytes_to_transfer here represents the dummy circles
1119 xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth;
1120 xqspi->bytes_to_receive = 0;
1122 * Using op->data.buswidth instead of op->dummy.buswidth here because
1125 zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1132 if (op->data.nbytes) {
1133 reinit_completion(&xqspi->data_completion);
1134 if (op->data.dir == SPI_MEM_DATA_OUT) {
1135 xqspi->txbuf = (u8 *)op->data.buf.out;
1136 xqspi->rxbuf = NULL;
1137 xqspi->bytes_to_transfer = op->data.nbytes;
1138 xqspi->bytes_to_receive = 0;
1139 zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1150 xqspi->txbuf = NULL;
1151 xqspi->rxbuf = (u8 *)op->data.buf.in;
1152 xqspi->bytes_to_receive = op->data.nbytes;
1153 xqspi->bytes_to_transfer = 0;
1154 err = zynqmp_qspi_read_op(xqspi, op->data.buswidth,
1163 if (xqspi->mode == GQSPI_MODE_DMA) {
1174 timeout = zynqmp_qspi_timeout(xqspi, op->data.buswidth,
1175 op->data.nbytes);
1176 if (!wait_for_completion_timeout(&xqspi->data_completion, timeout))
1177 err = -ETIMEDOUT;
1182 zynqmp_qspi_chipselect(mem->spi, true);
1183 mutex_unlock(&xqspi->op_lock);
1199 { .compatible = "xlnx,zynqmp-qspi-1.0"},
1200 { .compatible = "xlnx,versal-qspi-1.0", .data = &versal_qspi_def },
1213 * zynqmp_qspi_probe - Probe method for the QSPI driver
1225 struct device *dev = &pdev->dev;
1226 struct device_node *np = dev->of_node;
1230 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*xqspi));
1232 return -ENOMEM;
1235 xqspi->dev = dev;
1236 xqspi->ctlr = ctlr;
1239 p_data = of_device_get_match_data(&pdev->dev);
1240 if (p_data && (p_data->quirks & QSPI_QUIRK_HAS_TAPDELAY))
1241 xqspi->has_tapdelay = true;
1243 xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
1244 if (IS_ERR(xqspi->regs))
1245 return PTR_ERR(xqspi->regs);
1247 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1248 if (IS_ERR(xqspi->pclk))
1249 return dev_err_probe(dev, PTR_ERR(xqspi->pclk),
1252 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1253 if (IS_ERR(xqspi->refclk))
1254 return dev_err_probe(dev, PTR_ERR(xqspi->refclk),
1257 ret = clk_prepare_enable(xqspi->pclk);
1261 ret = clk_prepare_enable(xqspi->refclk);
1267 init_completion(&xqspi->data_completion);
1269 mutex_init(&xqspi->op_lock);
1271 pm_runtime_use_autosuspend(&pdev->dev);
1272 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1273 pm_runtime_set_active(&pdev->dev);
1274 pm_runtime_enable(&pdev->dev);
1276 ret = pm_runtime_get_sync(&pdev->dev);
1278 dev_err(&pdev->dev, "Failed to pm_runtime_get_sync: %d\n", ret);
1282 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1284 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1285 xqspi->speed_hz = ctlr->max_speed_hz;
1290 xqspi->irq = platform_get_irq(pdev, 0);
1291 if (xqspi->irq < 0) {
1292 ret = xqspi->irq;
1295 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1296 0, pdev->name, xqspi);
1298 ret = -ENXIO;
1303 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1307 ret = of_property_read_u32(np, "num-cs", &num_cs);
1309 ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1311 ret = -EINVAL;
1312 dev_err(&pdev->dev, "only %d chip selects are available\n",
1316 ctlr->num_chipselect = num_cs;
1319 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1320 ctlr->mem_ops = &zynqmp_qspi_mem_ops;
1321 ctlr->mem_caps = &zynqmp_qspi_mem_caps;
1322 ctlr->setup = zynqmp_qspi_setup_op;
1323 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1324 ctlr->dev.of_node = np;
1325 ctlr->auto_runtime_pm = true;
1327 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1329 dev_err(&pdev->dev, "spi_register_controller failed\n");
1333 pm_runtime_mark_last_busy(&pdev->dev);
1334 pm_runtime_put_autosuspend(&pdev->dev);
1339 pm_runtime_disable(&pdev->dev);
1340 pm_runtime_dont_use_autosuspend(&pdev->dev);
1341 pm_runtime_put_noidle(&pdev->dev);
1342 pm_runtime_set_suspended(&pdev->dev);
1343 clk_disable_unprepare(xqspi->refclk);
1345 clk_disable_unprepare(xqspi->pclk);
1351 * zynqmp_qspi_remove - Remove method for the QSPI driver
1364 pm_runtime_get_sync(&pdev->dev);
1368 pm_runtime_disable(&pdev->dev);
1369 pm_runtime_dont_use_autosuspend(&pdev->dev);
1370 pm_runtime_put_noidle(&pdev->dev);
1371 pm_runtime_set_suspended(&pdev->dev);
1372 clk_disable_unprepare(xqspi->refclk);
1373 clk_disable_unprepare(xqspi->pclk);
1382 .name = "zynqmp-qspi",