Lines Matching +full:syscon +full:- +full:chipselects
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
15 #include <linux/dma-mapping.h>
17 #include <linux/omap-dma.h>
26 #include <linux/mfd/syscon.h>
31 #include <linux/spi/spi-mem.h>
87 #define QSPI_WLEN(n) ((n - 1) << 19)
94 #define QSPI_FLEN(n) ((n - 1) << 0)
129 return readl(qspi->base + reg); in ti_qspi_read()
135 writel(val, qspi->base + reg); in ti_qspi_write()
140 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_setup()
143 if (spi->controller->busy) { in ti_qspi_setup()
144 dev_dbg(qspi->dev, "host busy doing other transfers\n"); in ti_qspi_setup()
145 return -EBUSY; in ti_qspi_setup()
148 if (!qspi->host->max_speed_hz) { in ti_qspi_setup()
149 dev_err(qspi->dev, "spi max frequency not defined\n"); in ti_qspi_setup()
150 return -EINVAL; in ti_qspi_setup()
153 spi->max_speed_hz = min(spi->max_speed_hz, qspi->host->max_speed_hz); in ti_qspi_setup()
155 ret = pm_runtime_resume_and_get(qspi->dev); in ti_qspi_setup()
157 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); in ti_qspi_setup()
161 pm_runtime_mark_last_busy(qspi->dev); in ti_qspi_setup()
162 ret = pm_runtime_put_autosuspend(qspi->dev); in ti_qspi_setup()
164 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n"); in ti_qspi_setup()
173 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_setup_clk()
177 clk_rate = clk_get_rate(qspi->fclk); in ti_qspi_setup_clk()
178 clk_div = DIV_ROUND_UP(clk_rate, speed_hz) - 1; in ti_qspi_setup_clk()
180 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", speed_hz, clk_div); in ti_qspi_setup_clk()
182 pm_runtime_resume_and_get(qspi->dev); in ti_qspi_setup_clk()
185 if (ctx_reg->clkctrl != clk_ctrl_new) { in ti_qspi_setup_clk()
195 ctx_reg->clkctrl = clk_ctrl_new; in ti_qspi_setup_clk()
198 pm_runtime_mark_last_busy(qspi->dev); in ti_qspi_setup_clk()
199 pm_runtime_put_autosuspend(qspi->dev); in ti_qspi_setup_clk()
204 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_restore_ctx()
206 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_restore_ctx()
239 return -ETIMEDOUT; in ti_qspi_poll_wc()
250 txbuf = t->tx_buf; in qspi_write_msg()
251 cmd = qspi->cmd | QSPI_WR_SNGL; in qspi_write_msg()
252 wlen = t->bits_per_word >> 3; /* in bytes */ in qspi_write_msg()
257 return -EBUSY; in qspi_write_msg()
261 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", in qspi_write_msg()
262 cmd, qspi->dc, *txbuf); in qspi_write_msg()
267 writel(data, qspi->base + in qspi_write_msg()
270 writel(data, qspi->base + in qspi_write_msg()
273 writel(data, qspi->base + in qspi_write_msg()
276 writel(data, qspi->base + in qspi_write_msg()
281 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
282 cmd = qspi->cmd | QSPI_WR_SNGL; in qspi_write_msg()
288 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n", in qspi_write_msg()
289 cmd, qspi->dc, *txbuf); in qspi_write_msg()
290 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
293 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n", in qspi_write_msg()
294 cmd, qspi->dc, *txbuf); in qspi_write_msg()
295 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
301 dev_err(qspi->dev, "write timed out\n"); in qspi_write_msg()
302 return -ETIMEDOUT; in qspi_write_msg()
305 count -= xfer_len; in qspi_write_msg()
320 rxbuf = t->rx_buf; in qspi_read_msg()
321 cmd = qspi->cmd; in qspi_read_msg()
322 switch (t->rx_nbits) { in qspi_read_msg()
333 wlen = t->bits_per_word >> 3; /* in bytes */ in qspi_read_msg()
337 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); in qspi_read_msg()
339 return -EBUSY; in qspi_read_msg()
344 * Optimize the 8-bit words transfers, as used by in qspi_read_msg()
363 dev_err(qspi->dev, "read timed out\n"); in qspi_read_msg()
364 return -ETIMEDOUT; in qspi_read_msg()
370 * Optimize the 8-bit words transfers, as used by in qspi_read_msg()
375 rx = readl(qspi->base + QSPI_SPI_DATA_REG_3); in qspi_read_msg()
377 rx = readl(qspi->base + QSPI_SPI_DATA_REG_2); in qspi_read_msg()
379 rx = readl(qspi->base + QSPI_SPI_DATA_REG_1); in qspi_read_msg()
381 rx = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
385 rx = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
387 *rxp++ = rx >> (rx_wlen - 8); in qspi_read_msg()
389 *rxp++ = rx >> (rx_wlen - 16); in qspi_read_msg()
391 *rxp++ = rx >> (rx_wlen - 24); in qspi_read_msg()
397 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
400 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
404 count -= rxlen; in qspi_read_msg()
415 if (t->tx_buf) { in qspi_transfer_msg()
418 dev_dbg(qspi->dev, "Error while writing\n"); in qspi_transfer_msg()
423 if (t->rx_buf) { in qspi_transfer_msg()
426 dev_dbg(qspi->dev, "Error while reading\n"); in qspi_transfer_msg()
438 complete(&qspi->transfer_complete); in ti_qspi_dma_callback()
444 struct dma_chan *chan = qspi->rx_chan; in ti_qspi_dma_xfer()
453 dev_err(qspi->dev, "device_prep_dma_memcpy error\n"); in ti_qspi_dma_xfer()
454 return -EIO; in ti_qspi_dma_xfer()
457 tx->callback = ti_qspi_dma_callback; in ti_qspi_dma_xfer()
458 tx->callback_param = qspi; in ti_qspi_dma_xfer()
459 cookie = tx->tx_submit(tx); in ti_qspi_dma_xfer()
460 reinit_completion(&qspi->transfer_complete); in ti_qspi_dma_xfer()
464 dev_err(qspi->dev, "dma_submit_error %d\n", cookie); in ti_qspi_dma_xfer()
465 return -EIO; in ti_qspi_dma_xfer()
469 time_left = wait_for_completion_timeout(&qspi->transfer_complete, in ti_qspi_dma_xfer()
473 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n"); in ti_qspi_dma_xfer()
474 return -ETIMEDOUT; in ti_qspi_dma_xfer()
483 dma_addr_t dma_src = qspi->mmap_phys_base + offs; in ti_qspi_dma_bounce_buffer()
494 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr, in ti_qspi_dma_bounce_buffer()
498 memcpy(to, qspi->rx_bb_addr, xfer_len); in ti_qspi_dma_bounce_buffer()
499 readsize -= xfer_len; in ti_qspi_dma_bounce_buffer()
511 dma_addr_t dma_src = qspi->mmap_phys_base + from; in ti_qspi_dma_xfer_sg()
529 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_enable_memory_map()
532 if (qspi->ctrl_base) { in ti_qspi_enable_memory_map()
533 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_enable_memory_map()
537 qspi->mmap_enabled = true; in ti_qspi_enable_memory_map()
538 qspi->current_cs = spi_get_chipselect(spi, 0); in ti_qspi_enable_memory_map()
543 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_disable_memory_map()
546 if (qspi->ctrl_base) in ti_qspi_disable_memory_map()
547 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_disable_memory_map()
549 qspi->mmap_enabled = false; in ti_qspi_disable_memory_map()
550 qspi->current_cs = -1; in ti_qspi_disable_memory_map()
557 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_setup_mmap_read()
571 memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT | in ti_qspi_setup_mmap_read()
579 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->controller); in ti_qspi_adjust_op_size()
582 if (op->data.dir == SPI_MEM_DATA_IN) { in ti_qspi_adjust_op_size()
583 if (op->addr.val < qspi->mmap_size) { in ti_qspi_adjust_op_size()
585 if (op->addr.val + op->data.nbytes > qspi->mmap_size) { in ti_qspi_adjust_op_size()
586 max_len = qspi->mmap_size - op->addr.val; in ti_qspi_adjust_op_size()
587 op->data.nbytes = min((size_t) op->data.nbytes, in ti_qspi_adjust_op_size()
597 max_len -= 1 + op->addr.nbytes + op->dummy.nbytes; in ti_qspi_adjust_op_size()
598 op->data.nbytes = min((size_t) op->data.nbytes, in ti_qspi_adjust_op_size()
609 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->controller); in ti_qspi_exec_mem_op()
614 if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN || in ti_qspi_exec_mem_op()
615 !op->addr.nbytes || op->addr.nbytes > 4) in ti_qspi_exec_mem_op()
616 return -EOPNOTSUPP; in ti_qspi_exec_mem_op()
619 from = op->addr.val; in ti_qspi_exec_mem_op()
620 if (from + op->data.nbytes > qspi->mmap_size) in ti_qspi_exec_mem_op()
621 return -EOPNOTSUPP; in ti_qspi_exec_mem_op()
623 mutex_lock(&qspi->list_lock); in ti_qspi_exec_mem_op()
625 if (!qspi->mmap_enabled || qspi->current_cs != spi_get_chipselect(mem->spi, 0)) { in ti_qspi_exec_mem_op()
626 ti_qspi_setup_clk(qspi, mem->spi->max_speed_hz); in ti_qspi_exec_mem_op()
627 ti_qspi_enable_memory_map(mem->spi); in ti_qspi_exec_mem_op()
629 ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth, in ti_qspi_exec_mem_op()
630 op->addr.nbytes, op->dummy.nbytes); in ti_qspi_exec_mem_op()
632 if (qspi->rx_chan) { in ti_qspi_exec_mem_op()
635 if (virt_addr_valid(op->data.buf.in) && in ti_qspi_exec_mem_op()
636 !spi_controller_dma_map_mem_op_data(mem->spi->controller, op, in ti_qspi_exec_mem_op()
639 spi_controller_dma_unmap_mem_op_data(mem->spi->controller, in ti_qspi_exec_mem_op()
643 op->data.buf.in, in ti_qspi_exec_mem_op()
644 op->data.nbytes); in ti_qspi_exec_mem_op()
647 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from, in ti_qspi_exec_mem_op()
648 op->data.nbytes); in ti_qspi_exec_mem_op()
651 mutex_unlock(&qspi->list_lock); in ti_qspi_exec_mem_op()
665 struct spi_device *spi = m->spi; in ti_qspi_start_transfer_one()
672 qspi->dc = 0; in ti_qspi_start_transfer_one()
674 if (spi->mode & SPI_CPHA) in ti_qspi_start_transfer_one()
675 qspi->dc |= QSPI_CKPHA(spi_get_chipselect(spi, 0)); in ti_qspi_start_transfer_one()
676 if (spi->mode & SPI_CPOL) in ti_qspi_start_transfer_one()
677 qspi->dc |= QSPI_CKPOL(spi_get_chipselect(spi, 0)); in ti_qspi_start_transfer_one()
678 if (spi->mode & SPI_CS_HIGH) in ti_qspi_start_transfer_one()
679 qspi->dc |= QSPI_CSPOL(spi_get_chipselect(spi, 0)); in ti_qspi_start_transfer_one()
682 list_for_each_entry(t, &m->transfers, transfer_list) in ti_qspi_start_transfer_one()
683 frame_len_words += t->len / (t->bits_per_word >> 3); in ti_qspi_start_transfer_one()
687 qspi->cmd = 0; in ti_qspi_start_transfer_one()
688 qspi->cmd |= QSPI_EN_CS(spi_get_chipselect(spi, 0)); in ti_qspi_start_transfer_one()
689 qspi->cmd |= QSPI_FLEN(frame_len_words); in ti_qspi_start_transfer_one()
691 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); in ti_qspi_start_transfer_one()
693 mutex_lock(&qspi->list_lock); in ti_qspi_start_transfer_one()
695 if (qspi->mmap_enabled) in ti_qspi_start_transfer_one()
698 list_for_each_entry(t, &m->transfers, transfer_list) { in ti_qspi_start_transfer_one()
699 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) | in ti_qspi_start_transfer_one()
700 QSPI_WLEN(t->bits_per_word)); in ti_qspi_start_transfer_one()
702 wlen = t->bits_per_word >> 3; in ti_qspi_start_transfer_one()
703 transfer_len_words = min(t->len / wlen, frame_len_words); in ti_qspi_start_transfer_one()
705 ti_qspi_setup_clk(qspi, t->speed_hz); in ti_qspi_start_transfer_one()
708 dev_dbg(qspi->dev, "transfer message failed\n"); in ti_qspi_start_transfer_one()
709 mutex_unlock(&qspi->list_lock); in ti_qspi_start_transfer_one()
710 return -EINVAL; in ti_qspi_start_transfer_one()
713 m->actual_length += transfer_len_words * wlen; in ti_qspi_start_transfer_one()
714 frame_len_words -= transfer_len_words; in ti_qspi_start_transfer_one()
719 mutex_unlock(&qspi->list_lock); in ti_qspi_start_transfer_one()
721 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG); in ti_qspi_start_transfer_one()
722 m->status = status; in ti_qspi_start_transfer_one()
740 if (qspi->rx_bb_addr) in ti_qspi_dma_cleanup()
741 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE, in ti_qspi_dma_cleanup()
742 qspi->rx_bb_addr, in ti_qspi_dma_cleanup()
743 qspi->rx_bb_dma_addr); in ti_qspi_dma_cleanup()
745 if (qspi->rx_chan) in ti_qspi_dma_cleanup()
746 dma_release_channel(qspi->rx_chan); in ti_qspi_dma_cleanup()
750 {.compatible = "ti,dra7xxx-qspi" },
751 {.compatible = "ti,am4372-qspi" },
761 struct device_node *np = pdev->dev.of_node; in ti_qspi_probe()
766 host = spi_alloc_host(&pdev->dev, sizeof(*qspi)); in ti_qspi_probe()
768 return -ENOMEM; in ti_qspi_probe()
770 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD; in ti_qspi_probe()
772 host->flags = SPI_CONTROLLER_HALF_DUPLEX; in ti_qspi_probe()
773 host->setup = ti_qspi_setup; in ti_qspi_probe()
774 host->auto_runtime_pm = true; in ti_qspi_probe()
775 host->transfer_one_message = ti_qspi_start_transfer_one; in ti_qspi_probe()
776 host->dev.of_node = pdev->dev.of_node; in ti_qspi_probe()
777 host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | in ti_qspi_probe()
779 host->mem_ops = &ti_qspi_mem_ops; in ti_qspi_probe()
781 if (!of_property_read_u32(np, "num-cs", &num_cs)) in ti_qspi_probe()
782 host->num_chipselect = num_cs; in ti_qspi_probe()
785 qspi->host = host; in ti_qspi_probe()
786 qspi->dev = &pdev->dev; in ti_qspi_probe()
793 dev_err(&pdev->dev, "missing platform data\n"); in ti_qspi_probe()
794 ret = -ENODEV; in ti_qspi_probe()
804 dev_err(&pdev->dev, in ti_qspi_probe()
810 qspi->mmap_size = resource_size(res_mmap); in ti_qspi_probe()
818 mutex_init(&qspi->list_lock); in ti_qspi_probe()
820 qspi->base = devm_ioremap_resource(&pdev->dev, r); in ti_qspi_probe()
821 if (IS_ERR(qspi->base)) { in ti_qspi_probe()
822 ret = PTR_ERR(qspi->base); in ti_qspi_probe()
827 if (of_property_read_bool(np, "syscon-chipselects")) { in ti_qspi_probe()
828 qspi->ctrl_base = in ti_qspi_probe()
830 "syscon-chipselects"); in ti_qspi_probe()
831 if (IS_ERR(qspi->ctrl_base)) { in ti_qspi_probe()
832 ret = PTR_ERR(qspi->ctrl_base); in ti_qspi_probe()
836 "syscon-chipselects", in ti_qspi_probe()
837 1, &qspi->ctrl_reg); in ti_qspi_probe()
839 dev_err(&pdev->dev, in ti_qspi_probe()
845 qspi->fclk = devm_clk_get(&pdev->dev, "fck"); in ti_qspi_probe()
846 if (IS_ERR(qspi->fclk)) { in ti_qspi_probe()
847 ret = PTR_ERR(qspi->fclk); in ti_qspi_probe()
848 dev_err(&pdev->dev, "could not get clk: %d\n", ret); in ti_qspi_probe()
851 pm_runtime_use_autosuspend(&pdev->dev); in ti_qspi_probe()
852 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT); in ti_qspi_probe()
853 pm_runtime_enable(&pdev->dev); in ti_qspi_probe()
855 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq)) in ti_qspi_probe()
856 host->max_speed_hz = max_freq; in ti_qspi_probe()
861 qspi->rx_chan = dma_request_chan_by_mask(&mask); in ti_qspi_probe()
862 if (IS_ERR(qspi->rx_chan)) { in ti_qspi_probe()
863 dev_err(qspi->dev, in ti_qspi_probe()
865 qspi->rx_chan = NULL; in ti_qspi_probe()
869 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev, in ti_qspi_probe()
871 &qspi->rx_bb_dma_addr, in ti_qspi_probe()
873 if (!qspi->rx_bb_addr) { in ti_qspi_probe()
874 dev_err(qspi->dev, in ti_qspi_probe()
876 dma_release_channel(qspi->rx_chan); in ti_qspi_probe()
879 host->dma_rx = qspi->rx_chan; in ti_qspi_probe()
880 init_completion(&qspi->transfer_complete); in ti_qspi_probe()
882 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start; in ti_qspi_probe()
885 if (!qspi->rx_chan && res_mmap) { in ti_qspi_probe()
886 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); in ti_qspi_probe()
887 if (IS_ERR(qspi->mmap_base)) { in ti_qspi_probe()
888 dev_info(&pdev->dev, in ti_qspi_probe()
890 PTR_ERR(qspi->mmap_base)); in ti_qspi_probe()
891 qspi->mmap_base = NULL; in ti_qspi_probe()
892 host->mem_ops = NULL; in ti_qspi_probe()
895 qspi->mmap_enabled = false; in ti_qspi_probe()
896 qspi->current_cs = -1; in ti_qspi_probe()
898 ret = devm_spi_register_controller(&pdev->dev, host); in ti_qspi_probe()
904 pm_runtime_disable(&pdev->dev); in ti_qspi_probe()
915 rc = spi_controller_suspend(qspi->host); in ti_qspi_remove()
917 dev_alert(&pdev->dev, "spi_controller_suspend() failed (%pe)\n", in ti_qspi_remove()
922 pm_runtime_put_sync(&pdev->dev); in ti_qspi_remove()
923 pm_runtime_disable(&pdev->dev); in ti_qspi_remove()
936 .name = "ti-qspi",
947 MODULE_ALIAS("platform:ti-qspi");