Lines Matching +full:dra7xxx +full:- +full:qspi
1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI QSPI driver
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
15 #include <linux/dma-mapping.h>
17 #include <linux/omap-dma.h>
31 #include <linux/spi/spi-mem.h>
87 #define QSPI_WLEN(n) ((n - 1) << 19)
94 #define QSPI_FLEN(n) ((n - 1) << 0)
126 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, in ti_qspi_read() argument
129 return readl(qspi->base + reg); in ti_qspi_read()
132 static inline void ti_qspi_write(struct ti_qspi *qspi, in ti_qspi_write() argument
135 writel(val, qspi->base + reg); in ti_qspi_write()
140 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_setup() local
143 if (spi->controller->busy) { in ti_qspi_setup()
144 dev_dbg(qspi->dev, "host busy doing other transfers\n"); in ti_qspi_setup()
145 return -EBUSY; in ti_qspi_setup()
148 if (!qspi->host->max_speed_hz) { in ti_qspi_setup()
149 dev_err(qspi->dev, "spi max frequency not defined\n"); in ti_qspi_setup()
150 return -EINVAL; in ti_qspi_setup()
153 spi->max_speed_hz = min(spi->max_speed_hz, qspi->host->max_speed_hz); in ti_qspi_setup()
155 ret = pm_runtime_resume_and_get(qspi->dev); in ti_qspi_setup()
157 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); in ti_qspi_setup()
161 ret = pm_runtime_put_autosuspend(qspi->dev); in ti_qspi_setup()
163 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n"); in ti_qspi_setup()
170 static void ti_qspi_setup_clk(struct ti_qspi *qspi, u32 speed_hz) in ti_qspi_setup_clk() argument
172 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_setup_clk()
176 clk_rate = clk_get_rate(qspi->fclk); in ti_qspi_setup_clk()
177 clk_div = DIV_ROUND_UP(clk_rate, speed_hz) - 1; in ti_qspi_setup_clk()
179 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", speed_hz, clk_div); in ti_qspi_setup_clk()
181 pm_runtime_resume_and_get(qspi->dev); in ti_qspi_setup_clk()
184 if (ctx_reg->clkctrl != clk_ctrl_new) { in ti_qspi_setup_clk()
185 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup_clk()
190 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup_clk()
193 ti_qspi_write(qspi, clk_ctrl_new, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup_clk()
194 ctx_reg->clkctrl = clk_ctrl_new; in ti_qspi_setup_clk()
197 pm_runtime_put_autosuspend(qspi->dev); in ti_qspi_setup_clk()
200 static void ti_qspi_restore_ctx(struct ti_qspi *qspi) in ti_qspi_restore_ctx() argument
202 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_restore_ctx()
204 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_restore_ctx()
207 static inline u32 qspi_is_busy(struct ti_qspi *qspi) in qspi_is_busy() argument
212 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in qspi_is_busy()
215 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in qspi_is_busy()
218 WARN(stat & BUSY, "qspi busy\n"); in qspi_is_busy()
222 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi) in ti_qspi_poll_wc() argument
228 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in ti_qspi_poll_wc()
234 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in ti_qspi_poll_wc()
237 return -ETIMEDOUT; in ti_qspi_poll_wc()
240 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_write_msg() argument
248 txbuf = t->tx_buf; in qspi_write_msg()
249 cmd = qspi->cmd | QSPI_WR_SNGL; in qspi_write_msg()
250 wlen = t->bits_per_word >> 3; /* in bytes */ in qspi_write_msg()
254 if (qspi_is_busy(qspi)) in qspi_write_msg()
255 return -EBUSY; in qspi_write_msg()
259 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", in qspi_write_msg()
260 cmd, qspi->dc, *txbuf); in qspi_write_msg()
265 writel(data, qspi->base + in qspi_write_msg()
268 writel(data, qspi->base + in qspi_write_msg()
271 writel(data, qspi->base + in qspi_write_msg()
274 writel(data, qspi->base + in qspi_write_msg()
279 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
280 cmd = qspi->cmd | QSPI_WR_SNGL; in qspi_write_msg()
286 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n", in qspi_write_msg()
287 cmd, qspi->dc, *txbuf); in qspi_write_msg()
288 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
291 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n", in qspi_write_msg()
292 cmd, qspi->dc, *txbuf); in qspi_write_msg()
293 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
297 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); in qspi_write_msg()
298 if (ti_qspi_poll_wc(qspi)) { in qspi_write_msg()
299 dev_err(qspi->dev, "write timed out\n"); in qspi_write_msg()
300 return -ETIMEDOUT; in qspi_write_msg()
303 count -= xfer_len; in qspi_write_msg()
309 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_read_msg() argument
318 rxbuf = t->rx_buf; in qspi_read_msg()
319 cmd = qspi->cmd; in qspi_read_msg()
320 switch (t->rx_nbits) { in qspi_read_msg()
331 wlen = t->bits_per_word >> 3; /* in bytes */ in qspi_read_msg()
335 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); in qspi_read_msg()
336 if (qspi_is_busy(qspi)) in qspi_read_msg()
337 return -EBUSY; in qspi_read_msg()
342 * Optimize the 8-bit words transfers, as used by in qspi_read_msg()
359 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); in qspi_read_msg()
360 if (ti_qspi_poll_wc(qspi)) { in qspi_read_msg()
361 dev_err(qspi->dev, "read timed out\n"); in qspi_read_msg()
362 return -ETIMEDOUT; in qspi_read_msg()
368 * Optimize the 8-bit words transfers, as used by in qspi_read_msg()
373 rx = readl(qspi->base + QSPI_SPI_DATA_REG_3); in qspi_read_msg()
375 rx = readl(qspi->base + QSPI_SPI_DATA_REG_2); in qspi_read_msg()
377 rx = readl(qspi->base + QSPI_SPI_DATA_REG_1); in qspi_read_msg()
379 rx = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
383 rx = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
385 *rxp++ = rx >> (rx_wlen - 8); in qspi_read_msg()
387 *rxp++ = rx >> (rx_wlen - 16); in qspi_read_msg()
389 *rxp++ = rx >> (rx_wlen - 24); in qspi_read_msg()
395 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
398 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
402 count -= rxlen; in qspi_read_msg()
408 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_transfer_msg() argument
413 if (t->tx_buf) { in qspi_transfer_msg()
414 ret = qspi_write_msg(qspi, t, count); in qspi_transfer_msg()
416 dev_dbg(qspi->dev, "Error while writing\n"); in qspi_transfer_msg()
421 if (t->rx_buf) { in qspi_transfer_msg()
422 ret = qspi_read_msg(qspi, t, count); in qspi_transfer_msg()
424 dev_dbg(qspi->dev, "Error while reading\n"); in qspi_transfer_msg()
434 struct ti_qspi *qspi = param; in ti_qspi_dma_callback() local
436 complete(&qspi->transfer_complete); in ti_qspi_dma_callback()
439 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst, in ti_qspi_dma_xfer() argument
442 struct dma_chan *chan = qspi->rx_chan; in ti_qspi_dma_xfer()
451 dev_err(qspi->dev, "device_prep_dma_memcpy error\n"); in ti_qspi_dma_xfer()
452 return -EIO; in ti_qspi_dma_xfer()
455 tx->callback = ti_qspi_dma_callback; in ti_qspi_dma_xfer()
456 tx->callback_param = qspi; in ti_qspi_dma_xfer()
457 cookie = tx->tx_submit(tx); in ti_qspi_dma_xfer()
458 reinit_completion(&qspi->transfer_complete); in ti_qspi_dma_xfer()
462 dev_err(qspi->dev, "dma_submit_error %d\n", cookie); in ti_qspi_dma_xfer()
463 return -EIO; in ti_qspi_dma_xfer()
467 time_left = wait_for_completion_timeout(&qspi->transfer_complete, in ti_qspi_dma_xfer()
471 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n"); in ti_qspi_dma_xfer()
472 return -ETIMEDOUT; in ti_qspi_dma_xfer()
478 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs, in ti_qspi_dma_bounce_buffer() argument
481 dma_addr_t dma_src = qspi->mmap_phys_base + offs; in ti_qspi_dma_bounce_buffer()
492 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr, in ti_qspi_dma_bounce_buffer()
496 memcpy(to, qspi->rx_bb_addr, xfer_len); in ti_qspi_dma_bounce_buffer()
497 readsize -= xfer_len; in ti_qspi_dma_bounce_buffer()
505 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg, in ti_qspi_dma_xfer_sg() argument
509 dma_addr_t dma_src = qspi->mmap_phys_base + from; in ti_qspi_dma_xfer_sg()
516 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len); in ti_qspi_dma_xfer_sg()
527 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_enable_memory_map() local
529 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG); in ti_qspi_enable_memory_map()
530 if (qspi->ctrl_base) { in ti_qspi_enable_memory_map()
531 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_enable_memory_map()
535 qspi->mmap_enabled = true; in ti_qspi_enable_memory_map()
536 qspi->current_cs = spi_get_chipselect(spi, 0); in ti_qspi_enable_memory_map()
541 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_disable_memory_map() local
543 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG); in ti_qspi_disable_memory_map()
544 if (qspi->ctrl_base) in ti_qspi_disable_memory_map()
545 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_disable_memory_map()
547 qspi->mmap_enabled = false; in ti_qspi_disable_memory_map()
548 qspi->current_cs = -1; in ti_qspi_disable_memory_map()
555 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_setup_mmap_read() local
569 memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT | in ti_qspi_setup_mmap_read()
571 ti_qspi_write(qspi, memval, in ti_qspi_setup_mmap_read()
577 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->controller); in ti_qspi_adjust_op_size() local
580 if (op->data.dir == SPI_MEM_DATA_IN) { in ti_qspi_adjust_op_size()
581 if (op->addr.val < qspi->mmap_size) { in ti_qspi_adjust_op_size()
583 if (op->addr.val + op->data.nbytes > qspi->mmap_size) { in ti_qspi_adjust_op_size()
584 max_len = qspi->mmap_size - op->addr.val; in ti_qspi_adjust_op_size()
585 op->data.nbytes = min((size_t) op->data.nbytes, in ti_qspi_adjust_op_size()
592 * Adjust size to comply with the QSPI max frame length. in ti_qspi_adjust_op_size()
595 max_len -= 1 + op->addr.nbytes + op->dummy.nbytes; in ti_qspi_adjust_op_size()
596 op->data.nbytes = min((size_t) op->data.nbytes, in ti_qspi_adjust_op_size()
607 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->controller); in ti_qspi_exec_mem_op() local
612 if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN || in ti_qspi_exec_mem_op()
613 !op->addr.nbytes || op->addr.nbytes > 4) in ti_qspi_exec_mem_op()
614 return -EOPNOTSUPP; in ti_qspi_exec_mem_op()
617 from = op->addr.val; in ti_qspi_exec_mem_op()
618 if (from + op->data.nbytes > qspi->mmap_size) in ti_qspi_exec_mem_op()
619 return -EOPNOTSUPP; in ti_qspi_exec_mem_op()
621 mutex_lock(&qspi->list_lock); in ti_qspi_exec_mem_op()
623 if (!qspi->mmap_enabled || qspi->current_cs != spi_get_chipselect(mem->spi, 0)) { in ti_qspi_exec_mem_op()
624 ti_qspi_setup_clk(qspi, op->max_freq); in ti_qspi_exec_mem_op()
625 ti_qspi_enable_memory_map(mem->spi); in ti_qspi_exec_mem_op()
627 ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth, in ti_qspi_exec_mem_op()
628 op->addr.nbytes, op->dummy.nbytes); in ti_qspi_exec_mem_op()
630 if (qspi->rx_chan) { in ti_qspi_exec_mem_op()
633 if (virt_addr_valid(op->data.buf.in) && in ti_qspi_exec_mem_op()
634 !spi_controller_dma_map_mem_op_data(mem->spi->controller, op, in ti_qspi_exec_mem_op()
636 ret = ti_qspi_dma_xfer_sg(qspi, sgt, from); in ti_qspi_exec_mem_op()
637 spi_controller_dma_unmap_mem_op_data(mem->spi->controller, in ti_qspi_exec_mem_op()
640 ret = ti_qspi_dma_bounce_buffer(qspi, from, in ti_qspi_exec_mem_op()
641 op->data.buf.in, in ti_qspi_exec_mem_op()
642 op->data.nbytes); in ti_qspi_exec_mem_op()
645 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from, in ti_qspi_exec_mem_op()
646 op->data.nbytes); in ti_qspi_exec_mem_op()
649 mutex_unlock(&qspi->list_lock); in ti_qspi_exec_mem_op()
666 struct ti_qspi *qspi = spi_controller_get_devdata(host); in ti_qspi_start_transfer_one() local
667 struct spi_device *spi = m->spi; in ti_qspi_start_transfer_one()
674 qspi->dc = 0; in ti_qspi_start_transfer_one()
676 if (spi->mode & SPI_CPHA) in ti_qspi_start_transfer_one()
677 qspi->dc |= QSPI_CKPHA(spi_get_chipselect(spi, 0)); in ti_qspi_start_transfer_one()
678 if (spi->mode & SPI_CPOL) in ti_qspi_start_transfer_one()
679 qspi->dc |= QSPI_CKPOL(spi_get_chipselect(spi, 0)); in ti_qspi_start_transfer_one()
680 if (spi->mode & SPI_CS_HIGH) in ti_qspi_start_transfer_one()
681 qspi->dc |= QSPI_CSPOL(spi_get_chipselect(spi, 0)); in ti_qspi_start_transfer_one()
684 list_for_each_entry(t, &m->transfers, transfer_list) in ti_qspi_start_transfer_one()
685 frame_len_words += t->len / (t->bits_per_word >> 3); in ti_qspi_start_transfer_one()
689 qspi->cmd = 0; in ti_qspi_start_transfer_one()
690 qspi->cmd |= QSPI_EN_CS(spi_get_chipselect(spi, 0)); in ti_qspi_start_transfer_one()
691 qspi->cmd |= QSPI_FLEN(frame_len_words); in ti_qspi_start_transfer_one()
693 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); in ti_qspi_start_transfer_one()
695 mutex_lock(&qspi->list_lock); in ti_qspi_start_transfer_one()
697 if (qspi->mmap_enabled) in ti_qspi_start_transfer_one()
700 list_for_each_entry(t, &m->transfers, transfer_list) { in ti_qspi_start_transfer_one()
701 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) | in ti_qspi_start_transfer_one()
702 QSPI_WLEN(t->bits_per_word)); in ti_qspi_start_transfer_one()
704 wlen = t->bits_per_word >> 3; in ti_qspi_start_transfer_one()
705 transfer_len_words = min(t->len / wlen, frame_len_words); in ti_qspi_start_transfer_one()
707 ti_qspi_setup_clk(qspi, t->speed_hz); in ti_qspi_start_transfer_one()
708 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen); in ti_qspi_start_transfer_one()
710 dev_dbg(qspi->dev, "transfer message failed\n"); in ti_qspi_start_transfer_one()
711 mutex_unlock(&qspi->list_lock); in ti_qspi_start_transfer_one()
712 return -EINVAL; in ti_qspi_start_transfer_one()
715 m->actual_length += transfer_len_words * wlen; in ti_qspi_start_transfer_one()
716 frame_len_words -= transfer_len_words; in ti_qspi_start_transfer_one()
721 mutex_unlock(&qspi->list_lock); in ti_qspi_start_transfer_one()
723 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG); in ti_qspi_start_transfer_one()
724 m->status = status; in ti_qspi_start_transfer_one()
732 struct ti_qspi *qspi; in ti_qspi_runtime_resume() local
734 qspi = dev_get_drvdata(dev); in ti_qspi_runtime_resume()
735 ti_qspi_restore_ctx(qspi); in ti_qspi_runtime_resume()
740 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi) in ti_qspi_dma_cleanup() argument
742 if (qspi->rx_bb_addr) in ti_qspi_dma_cleanup()
743 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE, in ti_qspi_dma_cleanup()
744 qspi->rx_bb_addr, in ti_qspi_dma_cleanup()
745 qspi->rx_bb_dma_addr); in ti_qspi_dma_cleanup()
747 if (qspi->rx_chan) in ti_qspi_dma_cleanup()
748 dma_release_channel(qspi->rx_chan); in ti_qspi_dma_cleanup()
752 {.compatible = "ti,dra7xxx-qspi" },
753 {.compatible = "ti,am4372-qspi" },
760 struct ti_qspi *qspi; in ti_qspi_probe() local
763 struct device_node *np = pdev->dev.of_node; in ti_qspi_probe()
768 host = spi_alloc_host(&pdev->dev, sizeof(*qspi)); in ti_qspi_probe()
770 return -ENOMEM; in ti_qspi_probe()
772 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD; in ti_qspi_probe()
774 host->flags = SPI_CONTROLLER_HALF_DUPLEX; in ti_qspi_probe()
775 host->setup = ti_qspi_setup; in ti_qspi_probe()
776 host->auto_runtime_pm = true; in ti_qspi_probe()
777 host->transfer_one_message = ti_qspi_start_transfer_one; in ti_qspi_probe()
778 host->dev.of_node = pdev->dev.of_node; in ti_qspi_probe()
779 host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | in ti_qspi_probe()
781 host->mem_ops = &ti_qspi_mem_ops; in ti_qspi_probe()
782 host->mem_caps = &ti_qspi_mem_caps; in ti_qspi_probe()
784 if (!of_property_read_u32(np, "num-cs", &num_cs)) in ti_qspi_probe()
785 host->num_chipselect = num_cs; in ti_qspi_probe()
787 qspi = spi_controller_get_devdata(host); in ti_qspi_probe()
788 qspi->host = host; in ti_qspi_probe()
789 qspi->dev = &pdev->dev; in ti_qspi_probe()
790 platform_set_drvdata(pdev, qspi); in ti_qspi_probe()
796 dev_err(&pdev->dev, "missing platform data\n"); in ti_qspi_probe()
797 ret = -ENODEV; in ti_qspi_probe()
807 dev_err(&pdev->dev, in ti_qspi_probe()
813 qspi->mmap_size = resource_size(res_mmap); in ti_qspi_probe()
821 mutex_init(&qspi->list_lock); in ti_qspi_probe()
823 qspi->base = devm_ioremap_resource(&pdev->dev, r); in ti_qspi_probe()
824 if (IS_ERR(qspi->base)) { in ti_qspi_probe()
825 ret = PTR_ERR(qspi->base); in ti_qspi_probe()
830 if (of_property_present(np, "syscon-chipselects")) { in ti_qspi_probe()
831 qspi->ctrl_base = in ti_qspi_probe()
832 syscon_regmap_lookup_by_phandle_args(np, "syscon-chipselects", in ti_qspi_probe()
833 1, &qspi->ctrl_reg); in ti_qspi_probe()
834 if (IS_ERR(qspi->ctrl_base)) { in ti_qspi_probe()
835 ret = PTR_ERR(qspi->ctrl_base); in ti_qspi_probe()
840 qspi->fclk = devm_clk_get(&pdev->dev, "fck"); in ti_qspi_probe()
841 if (IS_ERR(qspi->fclk)) { in ti_qspi_probe()
842 ret = PTR_ERR(qspi->fclk); in ti_qspi_probe()
843 dev_err(&pdev->dev, "could not get clk: %d\n", ret); in ti_qspi_probe()
846 pm_runtime_use_autosuspend(&pdev->dev); in ti_qspi_probe()
847 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT); in ti_qspi_probe()
848 pm_runtime_enable(&pdev->dev); in ti_qspi_probe()
850 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq)) in ti_qspi_probe()
851 host->max_speed_hz = max_freq; in ti_qspi_probe()
856 qspi->rx_chan = dma_request_chan_by_mask(&mask); in ti_qspi_probe()
857 if (IS_ERR(qspi->rx_chan)) { in ti_qspi_probe()
858 dev_err(qspi->dev, in ti_qspi_probe()
860 qspi->rx_chan = NULL; in ti_qspi_probe()
863 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev, in ti_qspi_probe()
865 &qspi->rx_bb_dma_addr, in ti_qspi_probe()
867 if (!qspi->rx_bb_addr) { in ti_qspi_probe()
868 dev_err(qspi->dev, in ti_qspi_probe()
870 dma_release_channel(qspi->rx_chan); in ti_qspi_probe()
873 host->dma_rx = qspi->rx_chan; in ti_qspi_probe()
874 init_completion(&qspi->transfer_complete); in ti_qspi_probe()
876 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start; in ti_qspi_probe()
879 if (!qspi->rx_chan && res_mmap) { in ti_qspi_probe()
880 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); in ti_qspi_probe()
881 if (IS_ERR(qspi->mmap_base)) { in ti_qspi_probe()
882 dev_info(&pdev->dev, in ti_qspi_probe()
884 PTR_ERR(qspi->mmap_base)); in ti_qspi_probe()
885 qspi->mmap_base = NULL; in ti_qspi_probe()
886 host->mem_ops = NULL; in ti_qspi_probe()
889 qspi->mmap_enabled = false; in ti_qspi_probe()
890 qspi->current_cs = -1; in ti_qspi_probe()
892 ret = devm_spi_register_controller(&pdev->dev, host); in ti_qspi_probe()
896 ti_qspi_dma_cleanup(qspi); in ti_qspi_probe()
898 pm_runtime_disable(&pdev->dev); in ti_qspi_probe()
906 struct ti_qspi *qspi = platform_get_drvdata(pdev); in ti_qspi_remove() local
909 rc = spi_controller_suspend(qspi->host); in ti_qspi_remove()
911 dev_alert(&pdev->dev, "spi_controller_suspend() failed (%pe)\n", in ti_qspi_remove()
916 pm_runtime_put_sync(&pdev->dev); in ti_qspi_remove()
917 pm_runtime_disable(&pdev->dev); in ti_qspi_remove()
919 ti_qspi_dma_cleanup(qspi); in ti_qspi_remove()
930 .name = "ti-qspi",
940 MODULE_DESCRIPTION("TI QSPI controller driver");
941 MODULE_ALIAS("platform:ti-qspi");