1 // SPDX-License-Identifier: GPL-2.0
3  * SuperH MSIOF SPI Controller Interface
7  * Copyright (C) 2014-2017 Glider bvba
14 #include <linux/dma-mapping.h>
28 #include <linux/spi/sh_msiof.h>
29 #include <linux/spi/spi.h>
71 		return ioread16(p->mapbase + reg_offs);  in sh_msiof_read()
73 		return ioread32(p->mapbase + reg_offs);  in sh_msiof_read()
83 		iowrite16(value, p->mapbase + reg_offs);  in sh_msiof_write()
86 		iowrite32(value, p->mapbase + reg_offs);  in sh_msiof_write()
94 	u32 mask = clr | set;  in sh_msiof_modify_ctr_wait()  local
102 	return readl_poll_timeout_atomic(p->mapbase + SICTR, data,  in sh_msiof_modify_ctr_wait()
103 					 (data & mask) == set, 1, 100);  in sh_msiof_modify_ctr_wait()
112 	complete(&p->done);  in sh_msiof_spi_irq()
119 	u32 mask = SICTR_TXRST | SICTR_RXRST;  in sh_msiof_spi_reset_regs()  local
123 	data |= mask;  in sh_msiof_spi_reset_regs()
126 	readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1,  in sh_msiof_spi_reset_regs()
133 	unsigned long parent_rate = clk_get_rate(p->clk);  in sh_msiof_spi_set_clk_regs()
134 	unsigned int div_pow = p->min_div_pow;  in sh_msiof_spi_set_clk_regs()
135 	u32 spi_hz = t->speed_hz;  in sh_msiof_spi_set_clk_regs()
160 		dev_err(&p->pdev->dev,  in sh_msiof_spi_set_clk_regs()
161 			"Requested SPI transfer rate %d is too low\n", spi_hz);  in sh_msiof_spi_set_clk_regs()
166 	t->effective_speed_hz = parent_rate / (brps << div_pow);  in sh_msiof_spi_set_clk_regs()
169 	scr = FIELD_PREP(SISCR_BRDV, div_pow - 1) |  in sh_msiof_spi_set_clk_regs()
170 	      FIELD_PREP(SISCR_BRPS, brps - 1);  in sh_msiof_spi_set_clk_regs()
172 	if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))  in sh_msiof_spi_set_clk_regs()
179 	 * DTDL/SYNCDL bit	: p->info->dtdl or p->info->syncdl  in sh_msiof_get_delay_bit()
197 	if (!p->info)  in sh_msiof_spi_get_dtdl_and_syncdl()
201 	if (p->info->dtdl > 200 || p->info->syncdl > 300) {  in sh_msiof_spi_get_dtdl_and_syncdl()
202 		dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");  in sh_msiof_spi_get_dtdl_and_syncdl()
207 	if ((p->info->dtdl + p->info->syncdl) % 100) {  in sh_msiof_spi_get_dtdl_and_syncdl()
208 		dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");  in sh_msiof_spi_get_dtdl_and_syncdl()
212 	val = FIELD_PREP(SIMDR1_DTDL, sh_msiof_get_delay_bit(p->info->dtdl)) |  in sh_msiof_spi_get_dtdl_and_syncdl()
214 			 sh_msiof_get_delay_bit(p->info->syncdl));  in sh_msiof_spi_get_dtdl_and_syncdl()
238 	if (spi_controller_is_target(p->ctlr)) {  in sh_msiof_spi_set_pin_regs()
246 	if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {  in sh_msiof_spi_set_pin_regs()
270 		  FIELD_PREP(SIMDR2_BITLEN1, bits - 1) |  in sh_msiof_spi_set_mode_regs()
271 		  FIELD_PREP(SIMDR2_WDLEN1, words1 - 1);  in sh_msiof_spi_set_mode_regs()
273 	if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX))  in sh_msiof_spi_set_mode_regs()
282 		u32 dr3 = FIELD_PREP(SIMDR3_BITLEN2, bits - 1) |  in sh_msiof_spi_set_mode_regs()
283 			  FIELD_PREP(SIMDR3_WDLEN2, words2 - 1);  in sh_msiof_spi_set_mode_regs()
451 static int sh_msiof_spi_setup(struct spi_device *spi)  in sh_msiof_spi_setup()  argument
454 		spi_controller_get_devdata(spi->controller);  in sh_msiof_spi_setup()
457 	if (spi_get_csgpiod(spi, 0) || spi_controller_is_target(p->ctlr))  in sh_msiof_spi_setup()
460 	if (p->native_cs_inited &&  in sh_msiof_spi_setup()
461 	    (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))  in sh_msiof_spi_setup()
467 	if (spi->mode & SPI_CS_HIGH)  in sh_msiof_spi_setup()
471 	pm_runtime_get_sync(&p->pdev->dev);  in sh_msiof_spi_setup()
476 	pm_runtime_put(&p->pdev->dev);  in sh_msiof_spi_setup()
477 	p->native_cs_high = spi->mode & SPI_CS_HIGH;  in sh_msiof_spi_setup()
478 	p->native_cs_inited = true;  in sh_msiof_spi_setup()
486 	const struct spi_device *spi = msg->spi;  in sh_msiof_prepare_message()  local
491 	if (spi_get_csgpiod(spi, 0)) {  in sh_msiof_prepare_message()
492 		ss = ctlr->unused_native_cs;  in sh_msiof_prepare_message()
493 		cs_high = p->native_cs_high;  in sh_msiof_prepare_message()
495 		ss = spi_get_chipselect(spi, 0);  in sh_msiof_prepare_message()
496 		cs_high = spi->mode & SPI_CS_HIGH;  in sh_msiof_prepare_message()
498 	sh_msiof_spi_set_pin_regs(p, ss, spi->mode & SPI_CPOL,  in sh_msiof_prepare_message()
499 				  spi->mode & SPI_CPHA, spi->mode & SPI_3WIRE,  in sh_msiof_prepare_message()
500 				  spi->mode & SPI_LSB_FIRST, cs_high);  in sh_msiof_prepare_message()
506 	bool target = spi_controller_is_target(p->ctlr);  in sh_msiof_spi_start()
526 	bool target = spi_controller_is_target(p->ctlr);  in sh_msiof_spi_stop()
546 	p->target_aborted = true;  in sh_msiof_target_abort()
547 	complete(&p->done);  in sh_msiof_target_abort()
548 	complete(&p->done_txdma);  in sh_msiof_target_abort()
555 	if (spi_controller_is_target(p->ctlr)) {  in sh_msiof_wait_for_completion()
557 		    p->target_aborted) {  in sh_msiof_wait_for_completion()
558 			dev_dbg(&p->pdev->dev, "interrupted\n");  in sh_msiof_wait_for_completion()
559 			return -EINTR;  in sh_msiof_wait_for_completion()
563 			dev_err(&p->pdev->dev, "timeout\n");  in sh_msiof_wait_for_completion()
564 			return -ETIMEDOUT;  in sh_msiof_wait_for_completion()
586 		words = min(words, p->tx_fifo_size);  in sh_msiof_spi_txrx_once()
588 		words = min(words, p->rx_fifo_size);  in sh_msiof_spi_txrx_once()
591 	fifo_shift = 32 - bits;  in sh_msiof_spi_txrx_once()
604 	reinit_completion(&p->done);  in sh_msiof_spi_txrx_once()
605 	p->target_aborted = false;  in sh_msiof_spi_txrx_once()
609 		dev_err(&p->pdev->dev, "failed to start hardware\n");  in sh_msiof_spi_txrx_once()
614 	ret = sh_msiof_wait_for_completion(p, &p->done);  in sh_msiof_spi_txrx_once()
627 		dev_err(&p->pdev->dev, "failed to shut down hardware\n");  in sh_msiof_spi_txrx_once()
659 		desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx,  in sh_msiof_dma_once()
660 					p->rx_dma_addr, len, DMA_DEV_TO_MEM,  in sh_msiof_dma_once()
663 			return -EAGAIN;  in sh_msiof_dma_once()
665 		desc_rx->callback = sh_msiof_dma_complete;  in sh_msiof_dma_once()
666 		desc_rx->callback_param = &p->done;  in sh_msiof_dma_once()
674 		dma_sync_single_for_device(p->ctlr->dma_tx->device->dev,  in sh_msiof_dma_once()
675 					   p->tx_dma_addr, len, DMA_TO_DEVICE);  in sh_msiof_dma_once()
676 		desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx,  in sh_msiof_dma_once()
677 					p->tx_dma_addr, len, DMA_MEM_TO_DEV,  in sh_msiof_dma_once()
680 			ret = -EAGAIN;  in sh_msiof_dma_once()
684 		desc_tx->callback = sh_msiof_dma_complete;  in sh_msiof_dma_once()
685 		desc_tx->callback_param = &p->done_txdma;  in sh_msiof_dma_once()
698 	/* setup msiof transfer mode registers (32-bit words) */  in sh_msiof_dma_once()
700 	words2 = len / 4 - words1;  in sh_msiof_dma_once()
705 	reinit_completion(&p->done);  in sh_msiof_dma_once()
707 		reinit_completion(&p->done_txdma);  in sh_msiof_dma_once()
708 	p->target_aborted = false;  in sh_msiof_dma_once()
712 		dma_async_issue_pending(p->ctlr->dma_rx);  in sh_msiof_dma_once()
714 		dma_async_issue_pending(p->ctlr->dma_tx);  in sh_msiof_dma_once()
718 		dev_err(&p->pdev->dev, "failed to start hardware\n");  in sh_msiof_dma_once()
724 		ret = sh_msiof_wait_for_completion(p, &p->done_txdma);  in sh_msiof_dma_once()
731 		ret = sh_msiof_wait_for_completion(p, &p->done);  in sh_msiof_dma_once()
739 		ret = sh_msiof_wait_for_completion(p, &p->done);  in sh_msiof_dma_once()
749 		dev_err(&p->pdev->dev, "failed to shut down hardware\n");  in sh_msiof_dma_once()
754 		dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev,  in sh_msiof_dma_once()
755 					p->rx_dma_addr, len, DMA_FROM_DEVICE);  in sh_msiof_dma_once()
764 		dmaengine_terminate_sync(p->ctlr->dma_tx);  in sh_msiof_dma_once()
767 		dmaengine_terminate_sync(p->ctlr->dma_rx);  in sh_msiof_dma_once()
776 		while (words--) {  in copy_bswap32()
781 		while (words--) {  in copy_bswap32()
786 		while (words--)  in copy_bswap32()
795 		while (words--) {  in copy_wswap32()
800 		while (words--) {  in copy_wswap32()
805 		while (words--)  in copy_wswap32()
816 				 struct spi_device *spi,  in sh_msiof_transfer_one()  argument
826 	const void *tx_buf = t->tx_buf;  in sh_msiof_transfer_one()
827 	void *rx_buf = t->rx_buf;  in sh_msiof_transfer_one()
828 	unsigned int len = t->len;  in sh_msiof_transfer_one()
829 	unsigned int bits = t->bits_per_word;  in sh_msiof_transfer_one()
840 	if (!spi_controller_is_target(p->ctlr))  in sh_msiof_transfer_one()
844 		max_wdlen = min(max_wdlen, p->tx_fifo_size);  in sh_msiof_transfer_one()
846 		max_wdlen = min(max_wdlen, p->rx_fifo_size);  in sh_msiof_transfer_one()
848 	while (ctlr->dma_tx && len > 15) {  in sh_msiof_transfer_one()
850 		 *  DMA supports 32-bit words only, hence pack 8-bit and 16-bit  in sh_msiof_transfer_one()
864 			copy32(p->tx_dma_page, tx_buf, l / 4);  in sh_msiof_transfer_one()
867 		if (ret == -EAGAIN) {  in sh_msiof_transfer_one()
868 			dev_warn_once(&p->pdev->dev,  in sh_msiof_transfer_one()
876 			copy32(rx_buf, p->rx_dma_page, l / 4);  in sh_msiof_transfer_one()
882 		len -= l;  in sh_msiof_transfer_one()
947 		words -= n;  in sh_msiof_transfer_one()
951 			bits = t->bits_per_word;  in sh_msiof_transfer_one()
1007 	{ .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1008 	{ .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1009 	{ .compatible = "renesas,msiof-r8a7795",   .data = &rcar_r8a7795_data },
1010 	{ .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1011 	{ .compatible = "renesas,msiof-r8a779a0",  .data = &rcar_gen3_data },
1012 	{ .compatible = "renesas,msiof-r8a779f0",  .data = &rcar_gen3_data },
1013 	{ .compatible = "renesas,rcar-gen4-msiof", .data = &rcar_gen4_data },
1014 	{ .compatible = "renesas,sh-msiof",        .data = &sh_data }, /* Deprecated */
1023 	struct device_node *np = dev->of_node;  in sh_msiof_spi_parse_dt()
1030 	info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_TARGET  in sh_msiof_spi_parse_dt()
1034 	if (info->mode == MSIOF_SPI_HOST)  in sh_msiof_spi_parse_dt()
1035 		of_property_read_u32(np, "num-cs", &num_cs);  in sh_msiof_spi_parse_dt()
1036 	of_property_read_u32(np, "renesas,tx-fifo-size",  in sh_msiof_spi_parse_dt()
1037 					&info->tx_fifo_override);  in sh_msiof_spi_parse_dt()
1038 	of_property_read_u32(np, "renesas,rx-fifo-size",  in sh_msiof_spi_parse_dt()
1039 					&info->rx_fifo_override);  in sh_msiof_spi_parse_dt()
1040 	of_property_read_u32(np, "renesas,dtdl", &info->dtdl);  in sh_msiof_spi_parse_dt()
1041 	of_property_read_u32(np, "renesas,syncdl", &info->syncdl);  in sh_msiof_spi_parse_dt()
1043 	info->num_chipselect = num_cs;  in sh_msiof_spi_parse_dt()
1057 	dma_cap_mask_t mask;  in sh_msiof_request_dma_chan()  local
1062 	dma_cap_zero(mask);  in sh_msiof_request_dma_chan()
1063 	dma_cap_set(DMA_SLAVE, mask);  in sh_msiof_request_dma_chan()
1065 	chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,  in sh_msiof_request_dma_chan()
1095 	struct platform_device *pdev = p->pdev;  in sh_msiof_request_dma()
1096 	struct device *dev = &pdev->dev;  in sh_msiof_request_dma()
1097 	const struct sh_msiof_spi_info *info = p->info;  in sh_msiof_request_dma()
1103 	if (dev->of_node) {  in sh_msiof_request_dma()
1107 	} else if (info && info->dma_tx_id && info->dma_rx_id) {  in sh_msiof_request_dma()
1108 		dma_tx_id = info->dma_tx_id;  in sh_msiof_request_dma()
1109 		dma_rx_id = info->dma_rx_id;  in sh_msiof_request_dma()
1115 	/* The DMA engine uses the second register set, if present */  in sh_msiof_request_dma()
1120 	ctlr = p->ctlr;  in sh_msiof_request_dma()
1121 	ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,  in sh_msiof_request_dma()
1122 						 dma_tx_id, res->start + SITFDR);  in sh_msiof_request_dma()
1123 	if (!ctlr->dma_tx)  in sh_msiof_request_dma()
1124 		return -ENODEV;  in sh_msiof_request_dma()
1126 	ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,  in sh_msiof_request_dma()
1127 						 dma_rx_id, res->start + SIRFDR);  in sh_msiof_request_dma()
1128 	if (!ctlr->dma_rx)  in sh_msiof_request_dma()
1131 	p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);  in sh_msiof_request_dma()
1132 	if (!p->tx_dma_page)  in sh_msiof_request_dma()
1135 	p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);  in sh_msiof_request_dma()
1136 	if (!p->rx_dma_page)  in sh_msiof_request_dma()
1139 	tx_dev = ctlr->dma_tx->device->dev;  in sh_msiof_request_dma()
1140 	p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,  in sh_msiof_request_dma()
1142 	if (dma_mapping_error(tx_dev, p->tx_dma_addr))  in sh_msiof_request_dma()
1145 	rx_dev = ctlr->dma_rx->device->dev;  in sh_msiof_request_dma()
1146 	p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,  in sh_msiof_request_dma()
1148 	if (dma_mapping_error(rx_dev, p->rx_dma_addr))  in sh_msiof_request_dma()
1155 	dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);  in sh_msiof_request_dma()
1157 	free_page((unsigned long)p->rx_dma_page);  in sh_msiof_request_dma()
1159 	free_page((unsigned long)p->tx_dma_page);  in sh_msiof_request_dma()
1161 	dma_release_channel(ctlr->dma_rx);  in sh_msiof_request_dma()
1163 	dma_release_channel(ctlr->dma_tx);  in sh_msiof_request_dma()
1164 	ctlr->dma_tx = NULL;  in sh_msiof_request_dma()
1165 	return -ENODEV;  in sh_msiof_request_dma()
1170 	struct spi_controller *ctlr = p->ctlr;  in sh_msiof_release_dma()
1172 	if (!ctlr->dma_tx)  in sh_msiof_release_dma()
1175 	dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE,  in sh_msiof_release_dma()
1177 	dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE,  in sh_msiof_release_dma()
1179 	free_page((unsigned long)p->rx_dma_page);  in sh_msiof_release_dma()
1180 	free_page((unsigned long)p->tx_dma_page);  in sh_msiof_release_dma()
1181 	dma_release_channel(ctlr->dma_rx);  in sh_msiof_release_dma()
1182 	dma_release_channel(ctlr->dma_tx);  in sh_msiof_release_dma()
1191 	struct device *dev = &pdev->dev;  in sh_msiof_spi_probe()
1196 	/* Check whether MSIOF is used as I2S mode or SPI mode by checking "port" node */  in sh_msiof_spi_probe()
1197 	struct device_node *port __free(device_node) = of_graph_get_next_port(dev->of_node, NULL);  in sh_msiof_spi_probe()
1198 	if (port) /* It was MSIOF-I2S */  in sh_msiof_spi_probe()
1199 		return -ENODEV;  in sh_msiof_spi_probe()
1205 		chipdata = (const void *)pdev->id_entry->driver_data;  in sh_msiof_spi_probe()
1211 		return -ENXIO;  in sh_msiof_spi_probe()
1214 	if (chipdata->flags & SH_MSIOF_FLAG_FIXED_DTDL_200)  in sh_msiof_spi_probe()
1215 		info->dtdl = 200;  in sh_msiof_spi_probe()
1217 	if (info->mode == MSIOF_SPI_TARGET)  in sh_msiof_spi_probe()
1222 		return -ENOMEM;  in sh_msiof_spi_probe()
1227 	p->ctlr = ctlr;  in sh_msiof_spi_probe()
1228 	p->info = info;  in sh_msiof_spi_probe()
1229 	p->min_div_pow = chipdata->min_div_pow;  in sh_msiof_spi_probe()
1231 	init_completion(&p->done);  in sh_msiof_spi_probe()
1232 	init_completion(&p->done_txdma);  in sh_msiof_spi_probe()
1234 	p->clk = devm_clk_get(dev, NULL);  in sh_msiof_spi_probe()
1235 	if (IS_ERR(p->clk)) {  in sh_msiof_spi_probe()
1237 		ret = PTR_ERR(p->clk);  in sh_msiof_spi_probe()
1247 	p->mapbase = devm_platform_ioremap_resource(pdev, 0);  in sh_msiof_spi_probe()
1248 	if (IS_ERR(p->mapbase)) {  in sh_msiof_spi_probe()
1249 		ret = PTR_ERR(p->mapbase);  in sh_msiof_spi_probe()
1259 	p->pdev = pdev;  in sh_msiof_spi_probe()
1263 	p->tx_fifo_size = chipdata->tx_fifo_size;  in sh_msiof_spi_probe()
1264 	p->rx_fifo_size = chipdata->rx_fifo_size;  in sh_msiof_spi_probe()
1265 	if (p->info->tx_fifo_override)  in sh_msiof_spi_probe()
1266 		p->tx_fifo_size = p->info->tx_fifo_override;  in sh_msiof_spi_probe()
1267 	if (p->info->rx_fifo_override)  in sh_msiof_spi_probe()
1268 		p->rx_fifo_size = p->info->rx_fifo_override;  in sh_msiof_spi_probe()
1271 	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;  in sh_msiof_spi_probe()
1272 	ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;  in sh_msiof_spi_probe()
1273 	clksrc = clk_get_rate(p->clk);  in sh_msiof_spi_probe()
1274 	ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, 1024);  in sh_msiof_spi_probe()
1275 	ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, 1 << p->min_div_pow);  in sh_msiof_spi_probe()
1276 	ctlr->flags = chipdata->ctlr_flags;  in sh_msiof_spi_probe()
1277 	ctlr->bus_num = pdev->id;  in sh_msiof_spi_probe()
1278 	ctlr->num_chipselect = p->info->num_chipselect;  in sh_msiof_spi_probe()
1279 	ctlr->dev.of_node = dev->of_node;  in sh_msiof_spi_probe()
1280 	ctlr->setup = sh_msiof_spi_setup;  in sh_msiof_spi_probe()
1281 	ctlr->prepare_message = sh_msiof_prepare_message;  in sh_msiof_spi_probe()
1282 	ctlr->target_abort = sh_msiof_target_abort;  in sh_msiof_spi_probe()
1283 	ctlr->bits_per_word_mask = chipdata->bits_per_word_mask;  in sh_msiof_spi_probe()
1284 	ctlr->auto_runtime_pm = true;  in sh_msiof_spi_probe()
1285 	ctlr->transfer_one = sh_msiof_transfer_one;  in sh_msiof_spi_probe()
1286 	ctlr->use_gpio_descriptors = true;  in sh_msiof_spi_probe()
1287 	ctlr->max_native_cs = MAX_SS;  in sh_msiof_spi_probe()
1314 	pm_runtime_disable(&pdev->dev);  in sh_msiof_spi_remove()
1327 	return spi_controller_suspend(p->ctlr);  in sh_msiof_spi_suspend()
1334 	return spi_controller_resume(p->ctlr);  in sh_msiof_spi_resume()
1352 MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver");