Lines Matching +full:no +full:- +full:cs +full:- +full:readback
1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/dma-mapping.h>
17 #include <linux/platform_data/spi-s3c64xx.h>
27 /* Registers and bit-fields */
112 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
114 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
115 #define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \
116 __ffs((sdd)->tx_fifomask))
117 #define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \
118 __ffs((sdd)->rx_fifomask))
127 #define is_polling(x) (x->cntrlr_info->polling)
139 * struct s3c64xx_spi_port_config - SPI Controller hardware info
157 * @use_32bit_io: True if the SoC allows only 32-bit register accesses.
181 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
231 void __iomem *regs = sdd->regs;
250 } while (TX_FIFO_LVL(val, sdd) && --loops);
253 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
263 } while (--loops);
266 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
283 if (dma->direction == DMA_DEV_TO_MEM)
290 spin_lock_irqsave(&sdd->lock, flags);
292 if (dma->direction == DMA_DEV_TO_MEM) {
293 sdd->state &= ~RXBUSY;
294 if (!(sdd->state & TXBUSY))
295 complete(&sdd->xfer_completion);
297 sdd->state &= ~TXBUSY;
298 if (!(sdd->state & RXBUSY))
299 complete(&sdd->xfer_completion);
302 spin_unlock_irqrestore(&sdd->lock, flags);
315 if (dma->direction == DMA_DEV_TO_MEM) {
318 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
319 config.src_addr_width = sdd->cur_bpw / 8;
324 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
325 config.dst_addr_width = sdd->cur_bpw / 8;
328 config.direction = dma->direction;
329 ret = dmaengine_slave_config(dma->ch, &config);
333 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
334 dma->direction, DMA_PREP_INTERRUPT);
336 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
337 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
338 return -ENOMEM;
341 desc->callback = s3c64xx_spi_dmacb;
342 desc->callback_param = dma;
344 dma->cookie = dmaengine_submit(desc);
345 ret = dma_submit_error(dma->cookie);
347 dev_err(&sdd->pdev->dev, "DMA submission failed");
351 dma_async_issue_pending(dma->ch);
358 spi_controller_get_devdata(spi->controller);
360 if (sdd->cntrlr_info->no_cs)
364 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
365 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
367 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG);
371 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
374 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
376 sdd->regs + S3C64XX_SPI_CS_REG);
388 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx");
389 if (IS_ERR(sdd->rx_dma.ch)) {
390 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n");
391 sdd->rx_dma.ch = NULL;
395 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx");
396 if (IS_ERR(sdd->tx_dma.ch)) {
397 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n");
398 dma_release_channel(sdd->rx_dma.ch);
399 sdd->tx_dma.ch = NULL;
400 sdd->rx_dma.ch = NULL;
404 spi->dma_rx = sdd->rx_dma.ch;
405 spi->dma_tx = sdd->tx_dma.ch;
418 if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
419 dma_release_channel(sdd->rx_dma.ch);
420 dma_release_channel(sdd->tx_dma.ch);
421 sdd->rx_dma.ch = NULL;
422 sdd->tx_dma.ch = NULL;
434 if (sdd->rx_dma.ch && sdd->tx_dma.ch)
435 return xfer->len >= sdd->fifo_depth;
448 } while (--count);
460 } while (--count);
467 void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA;
468 const void *buf = xfer->tx_buf;
469 unsigned int len = xfer->len;
471 switch (sdd->cur_bpw) {
476 if (sdd->port_conf->use_32bit_io)
482 if (sdd->port_conf->use_32bit_io)
493 void __iomem *regs = sdd->regs;
511 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
516 if (xfer->tx_buf != NULL) {
517 sdd->state |= TXBUSY;
521 ret = s3c64xx_prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
527 if (xfer->rx_buf != NULL) {
528 sdd->state |= RXBUSY;
530 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
531 && !(sdd->cur_mode & SPI_CPHA))
537 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
540 ret = s3c64xx_prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
556 void __iomem *regs = sdd->regs;
559 u32 max_fifo = sdd->fifo_depth;
566 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
575 void __iomem *regs = sdd->regs;
581 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
586 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
590 * proceed further else return -ETIMEDOUT.
597 if (val && !xfer->rx_buf) {
602 && --val) {
611 return -ETIMEDOUT;
619 void __iomem *regs = sdd->regs;
629 time_us = (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed;
635 if (RX_FIFO_LVL(status, sdd) < xfer->len)
640 if (!wait_for_completion_timeout(&sdd->xfer_completion, val))
641 return -ETIMEDOUT;
647 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
650 return -EIO;
653 if (!xfer->rx_buf) {
654 sdd->state &= ~TXBUSY;
666 loops = xfer->len / sdd->fifo_depth;
667 buf = xfer->rx_buf;
673 switch (sdd->cur_bpw) {
689 } while (loops--);
690 sdd->state &= ~RXBUSY;
697 void __iomem *regs = sdd->regs;
700 int div = sdd->port_conf->clk_div;
703 if (!sdd->port_conf->clk_from_cmu) {
715 if (sdd->cur_mode & SPI_CPOL)
718 if (sdd->cur_mode & SPI_CPHA)
728 switch (sdd->cur_bpw) {
743 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback)
750 if (sdd->port_conf->clk_from_cmu) {
751 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div);
754 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div;
759 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1)
778 struct spi_device *spi = msg->spi;
779 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
782 if (!cs)
783 /* No delay if not defined */
784 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK);
786 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
793 struct spi_controller *ctlr = spi->controller;
795 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
803 const unsigned int fifo_len = sdd->fifo_depth;
816 reinit_completion(&sdd->xfer_completion);
819 bpw = xfer->bits_per_word;
820 speed = xfer->speed_hz;
822 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
823 sdd->cur_bpw = bpw;
824 sdd->cur_speed = speed;
825 sdd->cur_mode = spi->mode;
831 if (!is_polling(sdd) && xfer->len >= fifo_len &&
832 sdd->rx_dma.ch && sdd->tx_dma.ch) {
834 } else if (xfer->len >= fifo_len) {
835 tx_buf = xfer->tx_buf;
836 rx_buf = xfer->rx_buf;
837 origin_len = xfer->len;
838 target_len = xfer->len;
839 xfer->len = fifo_len - 1;
844 if (!use_dma && xfer->len > S3C64XX_SPI_POLLING_SIZE)
848 reinit_completion(&sdd->xfer_completion);
850 rdy_lv = xfer->len;
853 * fifo_lvl up to 64 byte -> N bytes
854 * 128 byte -> RDY_LVL * 2 bytes
855 * 256 byte -> RDY_LVL * 4 bytes
862 val = readl(sdd->regs + S3C64XX_SPI_MODE_CFG);
865 writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG);
868 val = readl(sdd->regs + S3C64XX_SPI_INT_EN);
870 sdd->regs + S3C64XX_SPI_INT_EN);
874 spin_lock_irqsave(&sdd->lock, flags);
877 sdd->state &= ~RXBUSY;
878 sdd->state &= ~TXBUSY;
885 spin_unlock_irqrestore(&sdd->lock, flags);
888 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
898 dev_err(&spi->dev,
899 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n",
900 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
901 (sdd->state & RXBUSY) ? 'f' : 'p',
902 (sdd->state & TXBUSY) ? 'f' : 'p',
903 xfer->len, use_dma ? 1 : 0, status);
908 if (xfer->tx_buf && (sdd->state & TXBUSY)) {
909 dmaengine_pause(sdd->tx_dma.ch);
910 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s);
911 dmaengine_terminate_all(sdd->tx_dma.ch);
912 dev_err(&spi->dev, "TX residue: %d\n", s.residue);
915 if (xfer->rx_buf && (sdd->state & RXBUSY)) {
916 dmaengine_pause(sdd->rx_dma.ch);
917 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s);
918 dmaengine_terminate_all(sdd->rx_dma.ch);
919 dev_err(&spi->dev, "RX residue: %d\n", s.residue);
926 target_len -= xfer->len;
928 if (xfer->tx_buf)
929 xfer->tx_buf += xfer->len;
931 if (xfer->rx_buf)
932 xfer->rx_buf += xfer->len;
935 xfer->len = fifo_len - 1;
937 xfer->len = target_len;
943 xfer->tx_buf = tx_buf;
944 xfer->rx_buf = rx_buf;
945 xfer->len = origin_len;
954 struct s3c64xx_spi_csinfo *cs;
958 target_np = spi->dev.of_node;
960 dev_err(&spi->dev, "device node not found\n");
961 return ERR_PTR(-EINVAL);
964 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
965 if (!cs)
966 return ERR_PTR(-ENOMEM);
969 of_get_child_by_name(target_np, "controller-data");
971 dev_info(&spi->dev, "feedback delay set to default (0)\n");
972 return cs;
975 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
976 cs->fb_delay = fb_delay;
977 return cs;
982 * and save the configuration in a local data-structure.
988 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
993 sdd = spi_controller_get_devdata(spi->controller);
994 if (spi->dev.of_node) {
995 cs = s3c64xx_get_target_ctrldata(spi);
996 spi->controller_data = cs;
1000 if (IS_ERR(cs)) {
1001 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi_get_chipselect(spi, 0));
1002 return -ENODEV;
1006 spi_set_ctldata(spi, cs);
1008 pm_runtime_get_sync(&sdd->pdev->dev);
1010 div = sdd->port_conf->clk_div;
1013 if (!sdd->port_conf->clk_from_cmu) {
1017 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1);
1019 if (spi->max_speed_hz > speed)
1020 spi->max_speed_hz = speed;
1022 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1;
1025 psr--;
1027 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
1028 if (spi->max_speed_hz < speed) {
1032 err = -EINVAL;
1037 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
1038 if (spi->max_speed_hz >= speed) {
1039 spi->max_speed_hz = speed;
1041 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
1042 spi->max_speed_hz);
1043 err = -EINVAL;
1048 pm_runtime_mark_last_busy(&sdd->pdev->dev);
1049 pm_runtime_put_autosuspend(&sdd->pdev->dev);
1055 pm_runtime_mark_last_busy(&sdd->pdev->dev);
1056 pm_runtime_put_autosuspend(&sdd->pdev->dev);
1057 /* setup() returns with device de-selected */
1063 if (spi->dev.of_node)
1064 kfree(cs);
1071 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
1074 if (spi->dev.of_node)
1075 kfree(cs);
1083 struct spi_controller *spi = sdd->host;
1086 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
1090 dev_err(&spi->dev, "RX overrun\n");
1094 dev_err(&spi->dev, "RX underrun\n");
1098 dev_err(&spi->dev, "TX overrun\n");
1102 dev_err(&spi->dev, "TX underrun\n");
1106 complete(&sdd->xfer_completion);
1107 /* No pending clear irq, turn-off INT_EN_RX_FIFO_RDY */
1108 val = readl(sdd->regs + S3C64XX_SPI_INT_EN);
1110 sdd->regs + S3C64XX_SPI_INT_EN);
1114 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1115 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1122 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1123 void __iomem *regs = sdd->regs;
1126 sdd->cur_speed = 0;
1128 if (sci->no_cs)
1129 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
1130 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
1131 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
1133 /* Disable Interrupts - we use Polling if not DMA mode */
1136 if (!sdd->port_conf->clk_from_cmu)
1137 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1168 return ERR_PTR(-ENOMEM);
1170 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1172 sci->src_clk_nr = 0;
1174 sci->src_clk_nr = temp;
1177 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1179 sci->num_cs = 1;
1181 sci->num_cs = temp;
1184 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1185 sci->polling = !of_property_present(dev->of_node, "dmas");
1200 if (pdev->dev.of_node)
1201 return of_device_get_match_data(&pdev->dev);
1203 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data;
1209 const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf;
1212 if (port_conf->rx_fifomask && port_conf->tx_fifomask)
1215 if (pdev->dev.of_node) {
1216 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1218 return dev_err_probe(&pdev->dev, ret,
1220 sdd->port_id = ret;
1222 if (pdev->id < 0)
1223 return dev_err_probe(&pdev->dev, -EINVAL,
1225 sdd->port_id = pdev->id;
1233 const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf;
1235 if (port_conf->rx_fifomask)
1236 sdd->rx_fifomask = port_conf->rx_fifomask;
1238 sdd->rx_fifomask = FIFO_LVL_MASK(sdd) <<
1239 port_conf->rx_lvl_offset;
1241 if (port_conf->tx_fifomask)
1242 sdd->tx_fifomask = port_conf->tx_fifomask;
1244 sdd->tx_fifomask = FIFO_LVL_MASK(sdd) <<
1252 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1257 if (!sci && pdev->dev.of_node) {
1258 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1264 return dev_err_probe(&pdev->dev, -ENODEV,
1271 host = devm_spi_alloc_host(&pdev->dev, sizeof(*sdd));
1273 return dev_err_probe(&pdev->dev, -ENOMEM,
1279 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1280 sdd->host = host;
1281 sdd->cntrlr_info = sci;
1282 sdd->pdev = pdev;
1288 if (sdd->port_conf->fifo_depth)
1289 sdd->fifo_depth = sdd->port_conf->fifo_depth;
1290 else if (of_property_read_u32(pdev->dev.of_node, "fifo-depth",
1291 &sdd->fifo_depth))
1292 sdd->fifo_depth = FIFO_DEPTH(sdd);
1296 sdd->cur_bpw = 8;
1298 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1299 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1301 host->dev.of_node = pdev->dev.of_node;
1302 host->bus_num = -1;
1303 host->setup = s3c64xx_spi_setup;
1304 host->cleanup = s3c64xx_spi_cleanup;
1305 host->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1306 host->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1307 host->prepare_message = s3c64xx_spi_prepare_message;
1308 host->transfer_one = s3c64xx_spi_transfer_one;
1309 host->max_transfer_size = s3c64xx_spi_max_transfer_size;
1310 host->num_chipselect = sci->num_cs;
1311 host->use_gpio_descriptors = true;
1312 host->dma_alignment = 8;
1313 host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1315 /* the spi->mode bits understood by this driver: */
1316 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1317 if (sdd->port_conf->has_loopback)
1318 host->mode_bits |= SPI_LOOP;
1319 host->auto_runtime_pm = true;
1321 host->can_dma = s3c64xx_spi_can_dma;
1323 sdd->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
1324 if (IS_ERR(sdd->regs))
1325 return PTR_ERR(sdd->regs);
1326 sdd->sfr_start = mem_res->start;
1328 if (sci->cfg_gpio && sci->cfg_gpio())
1329 return dev_err_probe(&pdev->dev, -EBUSY,
1333 sdd->clk = devm_clk_get_enabled(&pdev->dev, "spi");
1334 if (IS_ERR(sdd->clk))
1335 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->clk),
1338 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1339 sdd->src_clk = devm_clk_get_enabled(&pdev->dev, clk_name);
1340 if (IS_ERR(sdd->src_clk))
1341 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->src_clk),
1345 if (sdd->port_conf->clk_ioclk) {
1346 sdd->ioclk = devm_clk_get_enabled(&pdev->dev, "spi_ioclk");
1347 if (IS_ERR(sdd->ioclk))
1348 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->ioclk),
1352 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1353 pm_runtime_use_autosuspend(&pdev->dev);
1354 pm_runtime_set_active(&pdev->dev);
1355 pm_runtime_enable(&pdev->dev);
1356 pm_runtime_get_sync(&pdev->dev);
1361 spin_lock_init(&sdd->lock);
1362 init_completion(&sdd->xfer_completion);
1364 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1365 "spi-s3c64xx", sdd);
1367 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1374 sdd->regs + S3C64XX_SPI_INT_EN);
1376 ret = devm_spi_register_controller(&pdev->dev, host);
1378 dev_err(&pdev->dev, "cannot register SPI host: %d\n", ret);
1382 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n",
1383 host->bus_num, host->num_chipselect);
1384 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1385 mem_res, sdd->fifo_depth);
1387 pm_runtime_mark_last_busy(&pdev->dev);
1388 pm_runtime_put_autosuspend(&pdev->dev);
1393 pm_runtime_put_noidle(&pdev->dev);
1394 pm_runtime_disable(&pdev->dev);
1395 pm_runtime_set_suspended(&pdev->dev);
1405 pm_runtime_get_sync(&pdev->dev);
1407 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1410 dma_release_channel(sdd->rx_dma.ch);
1411 dma_release_channel(sdd->tx_dma.ch);
1414 pm_runtime_put_noidle(&pdev->dev);
1415 pm_runtime_disable(&pdev->dev);
1416 pm_runtime_set_suspended(&pdev->dev);
1434 sdd->cur_speed = 0; /* Output Clock is stopped */
1443 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1446 if (sci->cfg_gpio)
1447 sci->cfg_gpio();
1463 clk_disable_unprepare(sdd->clk);
1464 clk_disable_unprepare(sdd->src_clk);
1465 clk_disable_unprepare(sdd->ioclk);
1476 if (sdd->port_conf->clk_ioclk) {
1477 ret = clk_prepare_enable(sdd->ioclk);
1482 ret = clk_prepare_enable(sdd->src_clk);
1486 ret = clk_prepare_enable(sdd->clk);
1494 sdd->regs + S3C64XX_SPI_INT_EN);
1499 clk_disable_unprepare(sdd->src_clk);
1501 clk_disable_unprepare(sdd->ioclk);
1634 .name = "s3c2443-spi",
1637 .name = "s3c6410-spi",
1645 { .compatible = "google,gs101-spi",
1648 { .compatible = "samsung,s3c2443-spi",
1651 { .compatible = "samsung,s3c6410-spi",
1654 { .compatible = "samsung,s5pv210-spi",
1657 { .compatible = "samsung,exynos4210-spi",
1660 { .compatible = "samsung,exynos7-spi",
1663 { .compatible = "samsung,exynos5433-spi",
1666 { .compatible = "samsung,exynos850-spi",
1669 { .compatible = "samsung,exynosautov9-spi",
1672 { .compatible = "tesla,fsd-spi",
1681 .name = "s3c64xx-spi",
1689 MODULE_ALIAS("platform:s3c64xx-spi");