Lines Matching refs:cr0
535 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET in rockchip_spi_config() local
543 cr0 |= CR0_OPM_TARGET << CR0_OPM_OFFSET; in rockchip_spi_config()
546 cr0 |= rs->rsd << CR0_RSD_OFFSET; in rockchip_spi_config()
547 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; in rockchip_spi_config()
549 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; in rockchip_spi_config()
551 cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET; in rockchip_spi_config()
554 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET; in rockchip_spi_config()
556 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET; in rockchip_spi_config()
558 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET; in rockchip_spi_config()
562 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET; in rockchip_spi_config()
566 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET; in rockchip_spi_config()
570 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET; in rockchip_spi_config()
590 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); in rockchip_spi_config()
732 u32 cr0; in rockchip_spi_setup() local
741 cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0); in rockchip_spi_setup()
743 cr0 &= ~(0x3 << CR0_SCPH_OFFSET); in rockchip_spi_setup()
744 cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET); in rockchip_spi_setup()
746 cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET; in rockchip_spi_setup()
748 cr0 &= ~(BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET); in rockchip_spi_setup()
750 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); in rockchip_spi_setup()