Lines Matching +full:bam +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
8 #include <linux/dma-mapping.h>
118 #define SPI_MAX_XFER (SZ_64K - 64)
165 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
181 return controller->n_words * controller->w_size; in spi_qup_len()
186 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
196 if (controller->bw_speed_hz == speed_hz) in spi_qup_vote_bw()
200 ret = icc_set_bw(controller->icc_path, 0, needed_peak_bw); in spi_qup_vote_bw()
204 controller->bw_speed_hz = speed_hz; in spi_qup_vote_bw()
219 return -EIO; in spi_qup_set_state()
223 dev_dbg(controller->dev, "invalid state for %ld,us %d\n", in spi_qup_set_state()
226 cur_state = readl_relaxed(controller->base + QUP_STATE); in spi_qup_set_state()
233 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
234 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
238 writel_relaxed(cur_state, controller->base + QUP_STATE); in spi_qup_set_state()
247 return -EIO; in spi_qup_set_state()
255 u8 *rx_buf = controller->rx_buf; in spi_qup_read_from_fifo()
259 for (; num_words; num_words--) { in spi_qup_read_from_fifo()
261 word = readl_relaxed(controller->base + QUP_INPUT_FIFO); in spi_qup_read_from_fifo()
263 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_read_from_fifo()
264 controller->rx_bytes, in spi_qup_read_from_fifo()
265 controller->w_size); in spi_qup_read_from_fifo()
268 controller->rx_bytes += num_bytes; in spi_qup_read_from_fifo()
272 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) { in spi_qup_read_from_fifo()
280 shift *= (controller->w_size - i - 1); in spi_qup_read_from_fifo()
281 rx_buf[controller->rx_bytes] = word >> shift; in spi_qup_read_from_fifo()
289 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_read()
291 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes, in spi_qup_read()
292 controller->w_size); in spi_qup_read()
293 words_per_block = controller->in_blk_sz >> 2; in spi_qup_read()
298 controller->base + QUP_OPERATIONAL); in spi_qup_read()
317 remainder -= num_words; in spi_qup_read()
334 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_read()
337 controller->base + QUP_OPERATIONAL); in spi_qup_read()
343 const u8 *tx_buf = controller->tx_buf; in spi_qup_write_to_fifo()
347 for (; num_words; num_words--) { in spi_qup_write_to_fifo()
350 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_write_to_fifo()
351 controller->tx_bytes, in spi_qup_write_to_fifo()
352 controller->w_size); in spi_qup_write_to_fifo()
355 data = tx_buf[controller->tx_bytes + i]; in spi_qup_write_to_fifo()
356 word |= data << (BITS_PER_BYTE * (3 - i)); in spi_qup_write_to_fifo()
359 controller->tx_bytes += num_bytes; in spi_qup_write_to_fifo()
361 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); in spi_qup_write_to_fifo()
369 complete(&qup->done); in spi_qup_dma_done()
374 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_write()
377 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes, in spi_qup_write()
378 controller->w_size); in spi_qup_write()
379 words_per_block = controller->out_blk_sz >> 2; in spi_qup_write()
384 controller->base + QUP_OPERATIONAL); in spi_qup_write()
403 remainder -= num_words; in spi_qup_write()
424 chan = host->dma_tx; in spi_qup_prep_sg()
426 chan = host->dma_rx; in spi_qup_prep_sg()
430 return desc ? PTR_ERR(desc) : -EINVAL; in spi_qup_prep_sg()
432 desc->callback = callback; in spi_qup_prep_sg()
433 desc->callback_param = qup; in spi_qup_prep_sg()
443 if (xfer->tx_buf) in spi_qup_dma_terminate()
444 dmaengine_terminate_all(host->dma_tx); in spi_qup_dma_terminate()
445 if (xfer->rx_buf) in spi_qup_dma_terminate()
446 dmaengine_terminate_all(host->dma_rx); in spi_qup_dma_terminate()
473 struct spi_controller *host = spi->controller; in spi_qup_do_dma()
478 ret = spi_qup_vote_bw(qup, xfer->speed_hz); in spi_qup_do_dma()
480 dev_err(qup->dev, "fail to vote for ICC bandwidth: %d\n", ret); in spi_qup_do_dma()
481 return -EIO; in spi_qup_do_dma()
484 if (xfer->rx_buf) in spi_qup_do_dma()
486 else if (xfer->tx_buf) in spi_qup_do_dma()
489 rx_sgl = xfer->rx_sg.sgl; in spi_qup_do_dma()
490 tx_sgl = xfer->tx_sg.sgl; in spi_qup_do_dma()
496 qup->n_words = spi_qup_sgl_get_nents_len(rx_sgl, in spi_qup_do_dma()
497 SPI_MAX_XFER, &rx_nents) / qup->w_size; in spi_qup_do_dma()
499 qup->n_words = spi_qup_sgl_get_nents_len(tx_sgl, in spi_qup_do_dma()
500 SPI_MAX_XFER, &tx_nents) / qup->w_size; in spi_qup_do_dma()
501 if (!qup->n_words) in spi_qup_do_dma()
502 return -EIO; in spi_qup_do_dma()
511 dev_warn(qup->dev, "cannot set RUN state\n"); in spi_qup_do_dma()
519 dma_async_issue_pending(host->dma_rx); in spi_qup_do_dma()
528 dma_async_issue_pending(host->dma_tx); in spi_qup_do_dma()
531 if (!wait_for_completion_timeout(&qup->done, timeout)) in spi_qup_do_dma()
532 return -ETIMEDOUT; in spi_qup_do_dma()
534 for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl)) in spi_qup_do_dma()
536 for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl)) in spi_qup_do_dma()
547 struct spi_controller *host = spi->controller; in spi_qup_do_pio()
551 n_words = qup->n_words; in spi_qup_do_pio()
553 qup->rx_buf = xfer->rx_buf; in spi_qup_do_pio()
554 qup->tx_buf = xfer->tx_buf; in spi_qup_do_pio()
558 qup->n_words = SPI_MAX_XFER; in spi_qup_do_pio()
560 qup->n_words = n_words % SPI_MAX_XFER; in spi_qup_do_pio()
562 if (qup->tx_buf && offset) in spi_qup_do_pio()
563 qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER; in spi_qup_do_pio()
565 if (qup->rx_buf && offset) in spi_qup_do_pio()
566 qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER; in spi_qup_do_pio()
572 if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32))) in spi_qup_do_pio()
573 qup->mode = QUP_IO_M_MODE_FIFO; in spi_qup_do_pio()
581 dev_warn(qup->dev, "cannot set RUN state\n"); in spi_qup_do_pio()
587 dev_warn(qup->dev, "cannot set PAUSE state\n"); in spi_qup_do_pio()
591 if (qup->mode == QUP_IO_M_MODE_FIFO) in spi_qup_do_pio()
596 dev_warn(qup->dev, "cannot set RUN state\n"); in spi_qup_do_pio()
600 if (!wait_for_completion_timeout(&qup->done, timeout)) in spi_qup_do_pio()
601 return -ETIMEDOUT; in spi_qup_do_pio()
604 } while (iterations--); in spi_qup_do_pio()
613 remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
614 controller->tx_bytes, controller->w_size); in spi_qup_data_pending()
616 remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
617 controller->rx_bytes, controller->w_size); in spi_qup_data_pending()
628 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
629 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
630 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
632 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
633 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
637 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); in spi_qup_qup_irq()
639 dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
641 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
643 dev_warn(controller->dev, "INPUT_OVER_RUN\n"); in spi_qup_qup_irq()
645 error = -EIO; in spi_qup_qup_irq()
650 dev_warn(controller->dev, "CLK_OVER_RUN\n"); in spi_qup_qup_irq()
652 dev_warn(controller->dev, "CLK_UNDER_RUN\n"); in spi_qup_qup_irq()
654 error = -EIO; in spi_qup_qup_irq()
657 spin_lock(&controller->lock); in spi_qup_qup_irq()
658 if (!controller->error) in spi_qup_qup_irq()
659 controller->error = error; in spi_qup_qup_irq()
660 spin_unlock(&controller->lock); in spi_qup_qup_irq()
662 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
663 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
672 complete(&controller->done); in spi_qup_qup_irq()
676 complete(&controller->done); in spi_qup_qup_irq()
679 if (!spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
683 complete(&controller->done); in spi_qup_qup_irq()
692 struct spi_qup *controller = spi_controller_get_devdata(spi->controller); in spi_qup_io_prep()
695 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { in spi_qup_io_prep()
696 dev_err(controller->dev, "too big size for loopback %d > %d\n", in spi_qup_io_prep()
697 xfer->len, controller->in_fifo_sz); in spi_qup_io_prep()
698 return -EIO; in spi_qup_io_prep()
701 ret = dev_pm_opp_set_rate(controller->dev, xfer->speed_hz); in spi_qup_io_prep()
703 dev_err(controller->dev, "fail to set frequency %d", in spi_qup_io_prep()
704 xfer->speed_hz); in spi_qup_io_prep()
705 return -EIO; in spi_qup_io_prep()
708 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); in spi_qup_io_prep()
709 controller->n_words = xfer->len / controller->w_size; in spi_qup_io_prep()
711 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32))) in spi_qup_io_prep()
712 controller->mode = QUP_IO_M_MODE_FIFO; in spi_qup_io_prep()
713 else if (spi_xfer_is_dma_mapped(spi->controller, spi, xfer)) in spi_qup_io_prep()
714 controller->mode = QUP_IO_M_MODE_BAM; in spi_qup_io_prep()
716 controller->mode = QUP_IO_M_MODE_BLOCK; in spi_qup_io_prep()
724 struct spi_qup *controller = spi_controller_get_devdata(spi->controller); in spi_qup_io_config()
728 spin_lock_irqsave(&controller->lock, flags); in spi_qup_io_config()
729 controller->xfer = xfer; in spi_qup_io_config()
730 controller->error = 0; in spi_qup_io_config()
731 controller->rx_bytes = 0; in spi_qup_io_config()
732 controller->tx_bytes = 0; in spi_qup_io_config()
733 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_io_config()
737 dev_err(controller->dev, "cannot set RESET state\n"); in spi_qup_io_config()
738 return -EIO; in spi_qup_io_config()
741 switch (controller->mode) { in spi_qup_io_config()
743 writel_relaxed(controller->n_words, in spi_qup_io_config()
744 controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
745 writel_relaxed(controller->n_words, in spi_qup_io_config()
746 controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
748 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
749 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
752 writel_relaxed(controller->n_words, in spi_qup_io_config()
753 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
754 writel_relaxed(controller->n_words, in spi_qup_io_config()
755 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
756 /* must be zero for BLOCK and BAM */ in spi_qup_io_config()
757 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
758 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
760 if (!controller->qup_v1) { in spi_qup_io_config()
763 input_cnt = controller->base + QUP_MX_INPUT_CNT; in spi_qup_io_config()
767 * That case is a non-balanced transfer when there is in spi_qup_io_config()
770 if (xfer->tx_buf) in spi_qup_io_config()
773 writel_relaxed(controller->n_words, input_cnt); in spi_qup_io_config()
775 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
779 reinit_completion(&controller->done); in spi_qup_io_config()
780 writel_relaxed(controller->n_words, in spi_qup_io_config()
781 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
782 writel_relaxed(controller->n_words, in spi_qup_io_config()
783 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
784 /* must be zero for BLOCK and BAM */ in spi_qup_io_config()
785 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
786 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
789 dev_err(controller->dev, "unknown mode = %d\n", in spi_qup_io_config()
790 controller->mode); in spi_qup_io_config()
791 return -EIO; in spi_qup_io_config()
794 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
798 if (!spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
803 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
804 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
806 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
808 control = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
810 if (spi->mode & SPI_CPOL) in spi_qup_io_config()
815 writel_relaxed(control, controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
817 config = readl_relaxed(controller->base + SPI_CONFIG); in spi_qup_io_config()
819 if (spi->mode & SPI_LOOP) in spi_qup_io_config()
824 if (spi->mode & SPI_CPHA) in spi_qup_io_config()
830 * HS_MODE improves signal stability for spi-clk high rates, in spi_qup_io_config()
833 if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP)) in spi_qup_io_config()
838 writel_relaxed(config, controller->base + SPI_CONFIG); in spi_qup_io_config()
840 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_io_config()
842 config |= xfer->bits_per_word - 1; in spi_qup_io_config()
845 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_io_config()
846 if (!xfer->tx_buf) in spi_qup_io_config()
848 if (!xfer->rx_buf) in spi_qup_io_config()
852 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_io_config()
855 if (!controller->qup_v1) { in spi_qup_io_config()
860 * status change in BAM mode in spi_qup_io_config()
863 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
866 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); in spi_qup_io_config()
884 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC); in spi_qup_transfer_one()
886 xfer->len) * 8, timeout); in spi_qup_transfer_one()
889 reinit_completion(&controller->done); in spi_qup_transfer_one()
891 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
892 controller->xfer = xfer; in spi_qup_transfer_one()
893 controller->error = 0; in spi_qup_transfer_one()
894 controller->rx_bytes = 0; in spi_qup_transfer_one()
895 controller->tx_bytes = 0; in spi_qup_transfer_one()
896 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
898 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
904 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
906 ret = controller->error; in spi_qup_transfer_one()
907 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
909 if (ret && spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
922 if (xfer->rx_buf) { in spi_qup_can_dma()
923 if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) || in spi_qup_can_dma()
924 IS_ERR_OR_NULL(host->dma_rx)) in spi_qup_can_dma()
926 if (qup->qup_v1 && (xfer->len % qup->in_blk_sz)) in spi_qup_can_dma()
930 if (xfer->tx_buf) { in spi_qup_can_dma()
931 if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) || in spi_qup_can_dma()
932 IS_ERR_OR_NULL(host->dma_tx)) in spi_qup_can_dma()
934 if (qup->qup_v1 && (xfer->len % qup->out_blk_sz)) in spi_qup_can_dma()
938 n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8); in spi_qup_can_dma()
939 if (n_words <= (qup->in_fifo_sz / sizeof(u32))) in spi_qup_can_dma()
947 if (!IS_ERR_OR_NULL(host->dma_rx)) in spi_qup_release_dma()
948 dma_release_channel(host->dma_rx); in spi_qup_release_dma()
949 if (!IS_ERR_OR_NULL(host->dma_tx)) in spi_qup_release_dma()
950 dma_release_channel(host->dma_tx); in spi_qup_release_dma()
956 struct dma_slave_config *rx_conf = &spi->rx_conf, in spi_qup_init_dma()
957 *tx_conf = &spi->tx_conf; in spi_qup_init_dma()
958 struct device *dev = spi->dev; in spi_qup_init_dma()
962 host->dma_rx = dma_request_chan(dev, "rx"); in spi_qup_init_dma()
963 if (IS_ERR(host->dma_rx)) in spi_qup_init_dma()
964 return PTR_ERR(host->dma_rx); in spi_qup_init_dma()
966 host->dma_tx = dma_request_chan(dev, "tx"); in spi_qup_init_dma()
967 if (IS_ERR(host->dma_tx)) { in spi_qup_init_dma()
968 ret = PTR_ERR(host->dma_tx); in spi_qup_init_dma()
973 rx_conf->direction = DMA_DEV_TO_MEM; in spi_qup_init_dma()
974 rx_conf->device_fc = 1; in spi_qup_init_dma()
975 rx_conf->src_addr = base + QUP_INPUT_FIFO; in spi_qup_init_dma()
976 rx_conf->src_maxburst = spi->in_blk_sz; in spi_qup_init_dma()
978 tx_conf->direction = DMA_MEM_TO_DEV; in spi_qup_init_dma()
979 tx_conf->device_fc = 1; in spi_qup_init_dma()
980 tx_conf->dst_addr = base + QUP_OUTPUT_FIFO; in spi_qup_init_dma()
981 tx_conf->dst_maxburst = spi->out_blk_sz; in spi_qup_init_dma()
983 ret = dmaengine_slave_config(host->dma_rx, rx_conf); in spi_qup_init_dma()
989 ret = dmaengine_slave_config(host->dma_tx, tx_conf); in spi_qup_init_dma()
998 dma_release_channel(host->dma_tx); in spi_qup_init_dma()
1000 dma_release_channel(host->dma_rx); in spi_qup_init_dma()
1010 controller = spi_controller_get_devdata(spi->controller); in spi_qup_set_cs()
1011 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
1019 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
1034 dev = &pdev->dev; in spi_qup_probe()
1057 if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) in spi_qup_probe()
1062 return -ENXIO; in spi_qup_probe()
1071 if (ret && ret != -ENODEV) in spi_qup_probe()
1077 return -ENOMEM; in spi_qup_probe()
1080 /* use num-cs unless not present or out of range */ in spi_qup_probe()
1081 if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) || in spi_qup_probe()
1083 host->num_chipselect = SPI_NUM_CHIPSELECTS; in spi_qup_probe()
1085 host->num_chipselect = num_cs; in spi_qup_probe()
1087 host->use_gpio_descriptors = true; in spi_qup_probe()
1088 host->max_native_cs = SPI_NUM_CHIPSELECTS; in spi_qup_probe()
1089 host->bus_num = pdev->id; in spi_qup_probe()
1090 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in spi_qup_probe()
1091 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in spi_qup_probe()
1092 host->max_speed_hz = max_freq; in spi_qup_probe()
1093 host->transfer_one = spi_qup_transfer_one; in spi_qup_probe()
1094 host->dev.of_node = pdev->dev.of_node; in spi_qup_probe()
1095 host->auto_runtime_pm = true; in spi_qup_probe()
1096 host->dma_alignment = dma_get_cache_alignment(); in spi_qup_probe()
1097 host->max_dma_len = SPI_MAX_XFER; in spi_qup_probe()
1103 controller->dev = dev; in spi_qup_probe()
1104 controller->base = base; in spi_qup_probe()
1105 controller->iclk = iclk; in spi_qup_probe()
1106 controller->cclk = cclk; in spi_qup_probe()
1107 controller->icc_path = icc_path; in spi_qup_probe()
1108 controller->irq = irq; in spi_qup_probe()
1110 ret = spi_qup_init_dma(host, res->start); in spi_qup_probe()
1111 if (ret == -EPROBE_DEFER) in spi_qup_probe()
1114 host->can_dma = spi_qup_can_dma; in spi_qup_probe()
1116 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev); in spi_qup_probe()
1118 if (!controller->qup_v1) in spi_qup_probe()
1119 host->set_cs = spi_qup_set_cs; in spi_qup_probe()
1121 spin_lock_init(&controller->lock); in spi_qup_probe()
1122 init_completion(&controller->done); in spi_qup_probe()
1141 controller->out_blk_sz = size * 16; in spi_qup_probe()
1143 controller->out_blk_sz = 4; in spi_qup_probe()
1147 controller->in_blk_sz = size * 16; in spi_qup_probe()
1149 controller->in_blk_sz = 4; in spi_qup_probe()
1152 controller->out_fifo_sz = controller->out_blk_sz * (2 << size); in spi_qup_probe()
1155 controller->in_fifo_sz = controller->in_blk_sz * (2 << size); in spi_qup_probe()
1158 controller->in_blk_sz, controller->in_fifo_sz, in spi_qup_probe()
1159 controller->out_blk_sz, controller->out_fifo_sz); in spi_qup_probe()
1172 if (!controller->qup_v1) in spi_qup_probe()
1179 if (controller->qup_v1) in spi_qup_probe()
1188 IRQF_TRIGGER_HIGH, pdev->name, controller); in spi_qup_probe()
1204 pm_runtime_disable(&pdev->dev); in spi_qup_probe()
1223 config = readl(controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1225 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1227 clk_disable_unprepare(controller->cclk); in spi_qup_pm_suspend_runtime()
1229 clk_disable_unprepare(controller->iclk); in spi_qup_pm_suspend_runtime()
1241 ret = clk_prepare_enable(controller->iclk); in spi_qup_pm_resume_runtime()
1245 ret = clk_prepare_enable(controller->cclk); in spi_qup_pm_resume_runtime()
1247 clk_disable_unprepare(controller->iclk); in spi_qup_pm_resume_runtime()
1252 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1254 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1279 clk_disable_unprepare(controller->cclk); in spi_qup_suspend()
1281 clk_disable_unprepare(controller->iclk); in spi_qup_suspend()
1291 ret = clk_prepare_enable(controller->iclk); in spi_qup_resume()
1295 ret = clk_prepare_enable(controller->cclk); in spi_qup_resume()
1297 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1312 clk_disable_unprepare(controller->cclk); in spi_qup_resume()
1313 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1320 struct spi_controller *host = dev_get_drvdata(&pdev->dev); in spi_qup_remove()
1324 ret = pm_runtime_get_sync(&pdev->dev); in spi_qup_remove()
1329 dev_warn(&pdev->dev, "failed to reset controller (%pe)\n", in spi_qup_remove()
1332 clk_disable_unprepare(controller->cclk); in spi_qup_remove()
1333 clk_disable_unprepare(controller->iclk); in spi_qup_remove()
1335 dev_warn(&pdev->dev, "failed to resume, skip hw disable (%pe)\n", in spi_qup_remove()
1341 pm_runtime_put_noidle(&pdev->dev); in spi_qup_remove()
1342 pm_runtime_disable(&pdev->dev); in spi_qup_remove()
1346 { .compatible = "qcom,spi-qup-v1.1.1", .data = (void *)1, },
1347 { .compatible = "qcom,spi-qup-v2.1.1", },
1348 { .compatible = "qcom,spi-qup-v2.2.1", },