Lines Matching +full:nand +full:- +full:ecc +full:- +full:strength
2 * SPDX-License-Identifier: GPL-2.0
15 #include <linux/dma-mapping.h>
22 #include <linux/mtd/nand-qpic-common.h>
31 /* QSPI NAND config reg bits */
69 * ECC state struct
70 * @corrected: ECC corrected
72 * @failed: ECC failed
88 int strength; member
105 struct qpic_ecc *ecc; member
131 snandc->regs->read_location0 = locreg_val; in qcom_spi_set_read_loc_first()
133 snandc->regs->read_location1 = locreg_val; in qcom_spi_set_read_loc_first()
135 snandc->regs->read_location2 = locreg_val; in qcom_spi_set_read_loc_first()
137 snandc->regs->read_location3 = locreg_val; in qcom_spi_set_read_loc_first()
152 snandc->regs->read_location_last0 = locreg_val; in qcom_spi_set_read_loc_last()
154 snandc->regs->read_location_last1 = locreg_val; in qcom_spi_set_read_loc_last()
156 snandc->regs->read_location_last2 = locreg_val; in qcom_spi_set_read_loc_last()
158 snandc->regs->read_location_last3 = locreg_val; in qcom_spi_set_read_loc_last()
161 static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand) in nand_to_qcom_snand() argument
163 struct nand_ecc_engine *eng = nand->ecc.engine; in nand_to_qcom_snand()
166 return qspi->snandc; in nand_to_qcom_snand()
179 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val); in qcom_spi_init()
180 snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR); in qcom_spi_init()
181 snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT); in qcom_spi_init()
183 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0); in qcom_spi_init()
186 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val); in qcom_spi_init()
188 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0); in qcom_spi_init()
190 qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0); in qcom_spi_init()
191 qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1, in qcom_spi_init()
196 dev_err(snandc->dev, "failure in submitting spi init descriptor\n"); in qcom_spi_init()
206 struct nand_device *nand = mtd_to_nanddev(mtd); in qcom_spi_ooblayout_ecc() local
207 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); in qcom_spi_ooblayout_ecc()
208 struct qpic_ecc *qecc = snandc->qspi->ecc; in qcom_spi_ooblayout_ecc()
212 oobregion->offset = 0; in qcom_spi_ooblayout_ecc()
213 oobregion->length = qecc->bytes * (qecc->steps - 1) + in qcom_spi_ooblayout_ecc()
214 qecc->bbm_size; in qcom_spi_ooblayout_ecc()
217 oobregion->offset = qecc->bytes * (qecc->steps - 1) + in qcom_spi_ooblayout_ecc()
218 qecc->bbm_size + in qcom_spi_ooblayout_ecc()
219 qecc->steps * 4; in qcom_spi_ooblayout_ecc()
220 oobregion->length = mtd->oobsize - oobregion->offset; in qcom_spi_ooblayout_ecc()
224 return -ERANGE; in qcom_spi_ooblayout_ecc()
230 struct nand_device *nand = mtd_to_nanddev(mtd); in qcom_spi_ooblayout_free() local
231 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); in qcom_spi_ooblayout_free()
232 struct qpic_ecc *qecc = snandc->qspi->ecc; in qcom_spi_ooblayout_free()
235 return -ERANGE; in qcom_spi_ooblayout_free()
237 oobregion->length = qecc->steps * 4; in qcom_spi_ooblayout_free()
238 oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size; in qcom_spi_ooblayout_free()
244 .ecc = qcom_spi_ooblayout_ecc,
248 static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand) in qcom_spi_ecc_init_ctx_pipelined() argument
250 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); in qcom_spi_ecc_init_ctx_pipelined()
251 struct nand_ecc_props *reqs = &nand->ecc.requirements; in qcom_spi_ecc_init_ctx_pipelined()
252 struct nand_ecc_props *user = &nand->ecc.user_conf; in qcom_spi_ecc_init_ctx_pipelined()
253 struct nand_ecc_props *conf = &nand->ecc.ctx.conf; in qcom_spi_ecc_init_ctx_pipelined()
254 struct mtd_info *mtd = nanddev_to_mtd(nand); in qcom_spi_ecc_init_ctx_pipelined()
258 cwperpage = mtd->writesize / NANDC_STEP_SIZE; in qcom_spi_ecc_init_ctx_pipelined()
259 snandc->qspi->num_cw = cwperpage; in qcom_spi_ecc_init_ctx_pipelined()
263 return -ENOMEM; in qcom_spi_ecc_init_ctx_pipelined()
265 if (user->step_size && user->strength) { in qcom_spi_ecc_init_ctx_pipelined()
266 ecc_cfg->step_size = user->step_size; in qcom_spi_ecc_init_ctx_pipelined()
267 ecc_cfg->strength = user->strength; in qcom_spi_ecc_init_ctx_pipelined()
268 } else if (reqs->step_size && reqs->strength) { in qcom_spi_ecc_init_ctx_pipelined()
269 ecc_cfg->step_size = reqs->step_size; in qcom_spi_ecc_init_ctx_pipelined()
270 ecc_cfg->strength = reqs->strength; in qcom_spi_ecc_init_ctx_pipelined()
273 ecc_cfg->step_size = NANDC_STEP_SIZE; in qcom_spi_ecc_init_ctx_pipelined()
274 ecc_cfg->strength = 4; in qcom_spi_ecc_init_ctx_pipelined()
277 if (ecc_cfg->step_size != NANDC_STEP_SIZE) { in qcom_spi_ecc_init_ctx_pipelined()
278 dev_err(snandc->dev, in qcom_spi_ecc_init_ctx_pipelined()
279 "only %u bytes ECC step size is supported\n", in qcom_spi_ecc_init_ctx_pipelined()
281 ret = -EOPNOTSUPP; in qcom_spi_ecc_init_ctx_pipelined()
285 switch (ecc_cfg->strength) { in qcom_spi_ecc_init_ctx_pipelined()
287 ecc_cfg->ecc_mode = ECC_MODE_4BIT; in qcom_spi_ecc_init_ctx_pipelined()
288 ecc_cfg->ecc_bytes_hw = 7; in qcom_spi_ecc_init_ctx_pipelined()
289 ecc_cfg->spare_bytes = 4; in qcom_spi_ecc_init_ctx_pipelined()
293 ecc_cfg->ecc_mode = ECC_MODE_8BIT; in qcom_spi_ecc_init_ctx_pipelined()
294 ecc_cfg->ecc_bytes_hw = 13; in qcom_spi_ecc_init_ctx_pipelined()
295 ecc_cfg->spare_bytes = 2; in qcom_spi_ecc_init_ctx_pipelined()
299 dev_err(snandc->dev, in qcom_spi_ecc_init_ctx_pipelined()
300 "only 4 or 8 bits ECC strength is supported\n"); in qcom_spi_ecc_init_ctx_pipelined()
301 ret = -EOPNOTSUPP; in qcom_spi_ecc_init_ctx_pipelined()
305 snandc->qspi->oob_buf = kmalloc(mtd->writesize + mtd->oobsize, in qcom_spi_ecc_init_ctx_pipelined()
307 if (!snandc->qspi->oob_buf) { in qcom_spi_ecc_init_ctx_pipelined()
308 ret = -ENOMEM; in qcom_spi_ecc_init_ctx_pipelined()
312 memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize); in qcom_spi_ecc_init_ctx_pipelined()
314 nand->ecc.ctx.priv = ecc_cfg; in qcom_spi_ecc_init_ctx_pipelined()
315 snandc->qspi->mtd = mtd; in qcom_spi_ecc_init_ctx_pipelined()
317 ecc_cfg->bbm_size = 1; in qcom_spi_ecc_init_ctx_pipelined()
318 ecc_cfg->bch_enabled = true; in qcom_spi_ecc_init_ctx_pipelined()
319 ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size; in qcom_spi_ecc_init_ctx_pipelined()
321 ecc_cfg->steps = cwperpage; in qcom_spi_ecc_init_ctx_pipelined()
322 ecc_cfg->cw_data = 516; in qcom_spi_ecc_init_ctx_pipelined()
323 ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes; in qcom_spi_ecc_init_ctx_pipelined()
324 bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1; in qcom_spi_ecc_init_ctx_pipelined()
335 snandc->max_cwperpage = cwperpage; in qcom_spi_ecc_init_ctx_pipelined()
337 snandc->bam_txn = qcom_alloc_bam_transaction(snandc); in qcom_spi_ecc_init_ctx_pipelined()
338 if (!snandc->bam_txn) { in qcom_spi_ecc_init_ctx_pipelined()
339 dev_err(snandc->dev, "failed to allocate BAM transaction\n"); in qcom_spi_ecc_init_ctx_pipelined()
340 ret = -ENOMEM; in qcom_spi_ecc_init_ctx_pipelined()
344 ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | in qcom_spi_ecc_init_ctx_pipelined()
345 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) | in qcom_spi_ecc_init_ctx_pipelined()
348 FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) | in qcom_spi_ecc_init_ctx_pipelined()
351 FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes); in qcom_spi_ecc_init_ctx_pipelined()
353 ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) | in qcom_spi_ecc_init_ctx_pipelined()
359 FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled); in qcom_spi_ecc_init_ctx_pipelined()
361 ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | in qcom_spi_ecc_init_ctx_pipelined()
363 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) | in qcom_spi_ecc_init_ctx_pipelined()
366 ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) | in qcom_spi_ecc_init_ctx_pipelined()
374 ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) | in qcom_spi_ecc_init_ctx_pipelined()
376 FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) | in qcom_spi_ecc_init_ctx_pipelined()
378 FIELD_PREP(ECC_MODE_MASK, ecc_cfg->ecc_mode) | in qcom_spi_ecc_init_ctx_pipelined()
379 FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw); in qcom_spi_ecc_init_ctx_pipelined()
381 ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203); in qcom_spi_ecc_init_ctx_pipelined()
383 conf->step_size = ecc_cfg->step_size; in qcom_spi_ecc_init_ctx_pipelined()
384 conf->strength = ecc_cfg->strength; in qcom_spi_ecc_init_ctx_pipelined()
386 snandc->regs->clrflashstatus = cpu_to_le32(FS_READY_BSY_N); in qcom_spi_ecc_init_ctx_pipelined()
387 snandc->regs->clrreadstatus = cpu_to_le32(0xc0); in qcom_spi_ecc_init_ctx_pipelined()
388 snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET); in qcom_spi_ecc_init_ctx_pipelined()
389 snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET); in qcom_spi_ecc_init_ctx_pipelined()
391 dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n", in qcom_spi_ecc_init_ctx_pipelined()
392 ecc_cfg->strength, ecc_cfg->step_size); in qcom_spi_ecc_init_ctx_pipelined()
401 static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand) in qcom_spi_ecc_cleanup_ctx_pipelined() argument
403 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand); in qcom_spi_ecc_cleanup_ctx_pipelined()
408 static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand, in qcom_spi_ecc_prepare_io_req_pipelined() argument
411 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); in qcom_spi_ecc_prepare_io_req_pipelined()
412 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand); in qcom_spi_ecc_prepare_io_req_pipelined()
414 snandc->qspi->ecc = ecc_cfg; in qcom_spi_ecc_prepare_io_req_pipelined()
415 snandc->qspi->raw_rw = false; in qcom_spi_ecc_prepare_io_req_pipelined()
416 snandc->qspi->oob_rw = false; in qcom_spi_ecc_prepare_io_req_pipelined()
417 snandc->qspi->page_rw = false; in qcom_spi_ecc_prepare_io_req_pipelined()
419 if (req->datalen) in qcom_spi_ecc_prepare_io_req_pipelined()
420 snandc->qspi->page_rw = true; in qcom_spi_ecc_prepare_io_req_pipelined()
422 if (req->ooblen) in qcom_spi_ecc_prepare_io_req_pipelined()
423 snandc->qspi->oob_rw = true; in qcom_spi_ecc_prepare_io_req_pipelined()
425 if (req->mode == MTD_OPS_RAW) in qcom_spi_ecc_prepare_io_req_pipelined()
426 snandc->qspi->raw_rw = true; in qcom_spi_ecc_prepare_io_req_pipelined()
431 static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand, in qcom_spi_ecc_finish_io_req_pipelined() argument
434 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); in qcom_spi_ecc_finish_io_req_pipelined()
435 struct mtd_info *mtd = nanddev_to_mtd(nand); in qcom_spi_ecc_finish_io_req_pipelined()
437 if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ) in qcom_spi_ecc_finish_io_req_pipelined()
440 if (snandc->qspi->ecc_stats.failed) in qcom_spi_ecc_finish_io_req_pipelined()
441 mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed; in qcom_spi_ecc_finish_io_req_pipelined()
443 mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected; in qcom_spi_ecc_finish_io_req_pipelined()
445 if (snandc->qspi->ecc_stats.failed) in qcom_spi_ecc_finish_io_req_pipelined()
446 return -EBADMSG; in qcom_spi_ecc_finish_io_req_pipelined()
448 return snandc->qspi->ecc_stats.bitflips; in qcom_spi_ecc_finish_io_req_pipelined()
463 int num_cw = snandc->qspi->num_cw; in qcom_spi_set_read_loc()
465 if (cw == (num_cw - 1)) in qcom_spi_set_read_loc()
470 if (cw == (num_cw - 1)) in qcom_spi_set_read_loc()
481 __le32 *reg = &snandc->regs->read_location0; in qcom_spi_config_cw_read()
482 int num_cw = snandc->qspi->num_cw; in qcom_spi_config_cw_read()
485 if (cw == (num_cw - 1)) { in qcom_spi_config_cw_read()
486 reg = &snandc->regs->read_location_last0; in qcom_spi_config_cw_read()
491 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_config_cw_read()
492 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_config_cw_read()
506 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_block_erase()
509 snandc->buf_count = 0; in qcom_spi_block_erase()
510 snandc->buf_start = 0; in qcom_spi_block_erase()
514 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_block_erase()
515 snandc->regs->addr0 = snandc->qspi->addr1; in qcom_spi_block_erase()
516 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_block_erase()
517 snandc->regs->cfg0 = cpu_to_le32((ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) | in qcom_spi_block_erase()
519 snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw); in qcom_spi_block_erase()
520 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_block_erase()
522 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); in qcom_spi_block_erase()
523 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); in qcom_spi_block_erase()
524 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_block_erase()
528 dev_err(snandc->dev, "failure to erase block\n"); in qcom_spi_block_erase()
538 __le32 *reg = &snandc->regs->read_location0; in qcom_spi_config_single_cw_page_read()
539 int num_cw = snandc->qspi->num_cw; in qcom_spi_config_single_cw_page_read()
541 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); in qcom_spi_config_single_cw_page_read()
542 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); in qcom_spi_config_single_cw_page_read()
543 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, in qcom_spi_config_single_cw_page_read()
545 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, in qcom_spi_config_single_cw_page_read()
549 if (cw == (num_cw - 1)) { in qcom_spi_config_single_cw_page_read()
550 reg = &snandc->regs->read_location_last0; in qcom_spi_config_single_cw_page_read()
553 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_config_single_cw_page_read()
554 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_config_single_cw_page_read()
566 u32 flash = le32_to_cpu(snandc->reg_read_buf[i]); in qcom_spi_check_raw_flash_errors()
569 return -EIO; in qcom_spi_check_raw_flash_errors()
578 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_read_last_cw()
579 struct mtd_info *mtd = snandc->qspi->mtd; in qcom_spi_read_last_cw()
583 u32 num_cw = snandc->qspi->num_cw; in qcom_spi_read_last_cw()
588 size = ecc_cfg->cw_size; in qcom_spi_read_last_cw()
589 col = ecc_cfg->cw_size * (num_cw - 1); in qcom_spi_read_last_cw()
591 memset(snandc->data_buffer, 0xff, size); in qcom_spi_read_last_cw()
592 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); in qcom_spi_read_last_cw()
593 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_read_last_cw()
595 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) | in qcom_spi_read_last_cw()
597 cfg1 = ecc_cfg->cfg1_raw; in qcom_spi_read_last_cw()
600 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_read_last_cw()
601 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_read_last_cw()
602 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_read_last_cw()
603 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_read_last_cw()
604 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_read_last_cw()
606 qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1); in qcom_spi_read_last_cw()
608 qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1); in qcom_spi_read_last_cw()
610 qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0); in qcom_spi_read_last_cw()
614 dev_err(snandc->dev, "failed to read last cw\n"); in qcom_spi_read_last_cw()
622 bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); in qcom_spi_read_last_cw()
630 * This can be removed once single-byte bad block marker support in qcom_spi_read_last_cw()
633 snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos]; in qcom_spi_read_last_cw()
635 memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes); in qcom_spi_read_last_cw()
643 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_check_error()
644 int i, num_cw = snandc->qspi->num_cw; in qcom_spi_check_error()
649 snandc->qspi->ecc_stats.failed = 0; in qcom_spi_check_error()
650 snandc->qspi->ecc_stats.corrected = 0; in qcom_spi_check_error()
653 buf = (struct snandc_read_status *)snandc->reg_read_buf; in qcom_spi_check_error()
658 flash = le32_to_cpu(buf->snandc_flash); in qcom_spi_check_error()
659 buffer = le32_to_cpu(buf->snandc_buffer); in qcom_spi_check_error()
660 erased_cw = le32_to_cpu(buf->snandc_erased_cw); in qcom_spi_check_error()
663 if (ecc_cfg->bch_enabled) in qcom_spi_check_error()
687 if (stat && stat != ecc_cfg->strength) in qcom_spi_check_error()
688 dev_warn_once(snandc->dev, in qcom_spi_check_error()
691 snandc->qspi->ecc_stats.corrected += stat; in qcom_spi_check_error()
697 return -EIO; in qcom_spi_check_error()
700 snandc->qspi->ecc_stats.bitflips = max_bitflips; in qcom_spi_check_error()
702 snandc->qspi->ecc_stats.failed++; in qcom_spi_check_error()
710 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_read_cw_raw()
711 struct mtd_info *mtd = snandc->qspi->mtd; in qcom_spi_read_cw_raw()
715 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; in qcom_spi_read_cw_raw()
718 snandc->buf_count = 0; in qcom_spi_read_cw_raw()
719 snandc->buf_start = 0; in qcom_spi_read_cw_raw()
722 raw_cw = num_cw - 1; in qcom_spi_read_cw_raw()
724 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) | in qcom_spi_read_cw_raw()
726 cfg1 = ecc_cfg->cfg1_raw; in qcom_spi_read_cw_raw()
729 col = ecc_cfg->cw_size * cw; in qcom_spi_read_cw_raw()
731 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); in qcom_spi_read_cw_raw()
732 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_read_cw_raw()
733 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_read_cw_raw()
734 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_read_cw_raw()
735 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_read_cw_raw()
736 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_read_cw_raw()
737 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_read_cw_raw()
739 qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1); in qcom_spi_read_cw_raw()
741 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); in qcom_spi_read_cw_raw()
742 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); in qcom_spi_read_cw_raw()
743 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0); in qcom_spi_read_cw_raw()
745 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, in qcom_spi_read_cw_raw()
747 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, in qcom_spi_read_cw_raw()
751 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); in qcom_spi_read_cw_raw()
752 oob_size1 = ecc_cfg->bbm_size; in qcom_spi_read_cw_raw()
754 if (cw == (num_cw - 1)) { in qcom_spi_read_cw_raw()
755 data_size2 = NANDC_STEP_SIZE - data_size1 - in qcom_spi_read_cw_raw()
756 ((num_cw - 1) * 4); in qcom_spi_read_cw_raw()
757 oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw + in qcom_spi_read_cw_raw()
758 ecc_cfg->spare_bytes; in qcom_spi_read_cw_raw()
760 data_size2 = ecc_cfg->cw_data - data_size1; in qcom_spi_read_cw_raw()
761 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; in qcom_spi_read_cw_raw()
790 dev_err(snandc->dev, "failure to read raw cw %d\n", cw); in qcom_spi_read_cw_raw()
800 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_read_page_raw()
803 u32 num_cw = snandc->qspi->num_cw; in qcom_spi_read_page_raw()
805 if (snandc->qspi->page_rw) in qcom_spi_read_page_raw()
806 data_buf = op->data.buf.in; in qcom_spi_read_page_raw()
808 oob_buf = snandc->qspi->oob_buf; in qcom_spi_read_page_raw()
817 data_buf += ecc_cfg->cw_data; in qcom_spi_read_page_raw()
819 oob_buf += ecc_cfg->bytes; in qcom_spi_read_page_raw()
828 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_read_page_ecc()
831 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; in qcom_spi_read_page_ecc()
833 data_buf = op->data.buf.in; in qcom_spi_read_page_ecc()
834 oob_buf = snandc->qspi->oob_buf; in qcom_spi_read_page_ecc()
836 snandc->buf_count = 0; in qcom_spi_read_page_ecc()
837 snandc->buf_start = 0; in qcom_spi_read_page_ecc()
840 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) | in qcom_spi_read_page_ecc()
841 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); in qcom_spi_read_page_ecc()
842 cfg1 = ecc_cfg->cfg1; in qcom_spi_read_page_ecc()
843 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; in qcom_spi_read_page_ecc()
845 snandc->regs->addr0 = snandc->qspi->addr1; in qcom_spi_read_page_ecc()
846 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_read_page_ecc()
847 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_read_page_ecc()
848 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_read_page_ecc()
849 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_read_page_ecc()
850 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_read_page_ecc()
851 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_read_page_ecc()
853 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); in qcom_spi_read_page_ecc()
857 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); in qcom_spi_read_page_ecc()
858 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); in qcom_spi_read_page_ecc()
859 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, in qcom_spi_read_page_ecc()
861 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, in qcom_spi_read_page_ecc()
868 if (i == (num_cw - 1)) { in qcom_spi_read_page_ecc()
869 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); in qcom_spi_read_page_ecc()
870 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + in qcom_spi_read_page_ecc()
871 ecc_cfg->spare_bytes; in qcom_spi_read_page_ecc()
873 data_size = ecc_cfg->cw_data; in qcom_spi_read_page_ecc()
874 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; in qcom_spi_read_page_ecc()
894 for (j = 0; j < ecc_cfg->bbm_size; j++) in qcom_spi_read_page_ecc()
909 dev_err(snandc->dev, "failure to read page\n"); in qcom_spi_read_page_ecc()
919 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_read_page_oob()
922 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; in qcom_spi_read_page_oob()
924 oob_buf = op->data.buf.in; in qcom_spi_read_page_oob()
926 snandc->buf_count = 0; in qcom_spi_read_page_oob()
927 snandc->buf_start = 0; in qcom_spi_read_page_oob()
931 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) | in qcom_spi_read_page_oob()
932 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); in qcom_spi_read_page_oob()
933 cfg1 = ecc_cfg->cfg1; in qcom_spi_read_page_oob()
934 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; in qcom_spi_read_page_oob()
936 snandc->regs->addr0 = snandc->qspi->addr1; in qcom_spi_read_page_oob()
937 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_read_page_oob()
938 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_read_page_oob()
939 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_read_page_oob()
940 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_read_page_oob()
941 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_read_page_oob()
942 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_read_page_oob()
944 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); in qcom_spi_read_page_oob()
946 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); in qcom_spi_read_page_oob()
947 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); in qcom_spi_read_page_oob()
948 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, in qcom_spi_read_page_oob()
950 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, in qcom_spi_read_page_oob()
957 if (i == (num_cw - 1)) { in qcom_spi_read_page_oob()
958 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); in qcom_spi_read_page_oob()
959 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + in qcom_spi_read_page_oob()
960 ecc_cfg->spare_bytes; in qcom_spi_read_page_oob()
962 data_size = ecc_cfg->cw_data; in qcom_spi_read_page_oob()
963 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; in qcom_spi_read_page_oob()
973 for (j = 0; j < ecc_cfg->bbm_size; j++) in qcom_spi_read_page_oob()
986 dev_err(snandc->dev, "failure to read oob\n"); in qcom_spi_read_page_oob()
996 if (snandc->qspi->page_rw && snandc->qspi->raw_rw) in qcom_spi_read_page()
999 if (snandc->qspi->page_rw) in qcom_spi_read_page()
1002 if (snandc->qspi->oob_rw && snandc->qspi->raw_rw) in qcom_spi_read_page()
1005 if (snandc->qspi->oob_rw) in qcom_spi_read_page()
1013 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); in qcom_spi_config_page_write()
1014 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); in qcom_spi_config_page_write()
1015 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, in qcom_spi_config_page_write()
1021 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_config_cw_write()
1022 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_config_cw_write()
1025 qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0); in qcom_spi_config_cw_write()
1026 qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1, in qcom_spi_config_cw_write()
1033 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_program_raw()
1034 struct mtd_info *mtd = snandc->qspi->mtd; in qcom_spi_program_raw()
1037 int num_cw = snandc->qspi->num_cw; in qcom_spi_program_raw()
1040 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) | in qcom_spi_program_raw()
1041 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); in qcom_spi_program_raw()
1042 cfg1 = ecc_cfg->cfg1_raw; in qcom_spi_program_raw()
1045 data_buf = snandc->qspi->data_buf; in qcom_spi_program_raw()
1047 oob_buf = snandc->qspi->oob_buf; in qcom_spi_program_raw()
1050 snandc->buf_count = 0; in qcom_spi_program_raw()
1051 snandc->buf_start = 0; in qcom_spi_program_raw()
1055 snandc->regs->addr0 = snandc->qspi->addr1; in qcom_spi_program_raw()
1056 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_program_raw()
1057 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_program_raw()
1058 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_program_raw()
1059 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_program_raw()
1060 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_program_raw()
1061 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_program_raw()
1069 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); in qcom_spi_program_raw()
1070 oob_size1 = ecc_cfg->bbm_size; in qcom_spi_program_raw()
1072 if (i == (num_cw - 1)) { in qcom_spi_program_raw()
1073 data_size2 = NANDC_STEP_SIZE - data_size1 - in qcom_spi_program_raw()
1074 ((num_cw - 1) << 2); in qcom_spi_program_raw()
1075 oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + in qcom_spi_program_raw()
1076 ecc_cfg->spare_bytes; in qcom_spi_program_raw()
1078 data_size2 = ecc_cfg->cw_data - data_size1; in qcom_spi_program_raw()
1079 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; in qcom_spi_program_raw()
1105 dev_err(snandc->dev, "failure to write raw page\n"); in qcom_spi_program_raw()
1115 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_program_ecc()
1118 int num_cw = snandc->qspi->num_cw; in qcom_spi_program_ecc()
1121 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) | in qcom_spi_program_ecc()
1122 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); in qcom_spi_program_ecc()
1123 cfg1 = ecc_cfg->cfg1; in qcom_spi_program_ecc()
1124 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; in qcom_spi_program_ecc()
1125 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg; in qcom_spi_program_ecc()
1127 if (snandc->qspi->data_buf) in qcom_spi_program_ecc()
1128 data_buf = snandc->qspi->data_buf; in qcom_spi_program_ecc()
1130 oob_buf = snandc->qspi->oob_buf; in qcom_spi_program_ecc()
1132 snandc->buf_count = 0; in qcom_spi_program_ecc()
1133 snandc->buf_start = 0; in qcom_spi_program_ecc()
1137 snandc->regs->addr0 = snandc->qspi->addr1; in qcom_spi_program_ecc()
1138 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_program_ecc()
1139 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_program_ecc()
1140 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_program_ecc()
1141 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_program_ecc()
1142 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_program_ecc()
1143 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg); in qcom_spi_program_ecc()
1144 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_program_ecc()
1151 if (i == (num_cw - 1)) { in qcom_spi_program_ecc()
1152 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); in qcom_spi_program_ecc()
1153 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + in qcom_spi_program_ecc()
1154 ecc_cfg->spare_bytes; in qcom_spi_program_ecc()
1156 data_size = ecc_cfg->cw_data; in qcom_spi_program_ecc()
1157 oob_size = ecc_cfg->bytes; in qcom_spi_program_ecc()
1162 i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0); in qcom_spi_program_ecc()
1164 if (i == (num_cw - 1)) { in qcom_spi_program_ecc()
1166 oob_buf += ecc_cfg->bbm_size; in qcom_spi_program_ecc()
1182 dev_err(snandc->dev, "failure to write page\n"); in qcom_spi_program_ecc()
1192 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_program_oob()
1195 int num_cw = snandc->qspi->num_cw; in qcom_spi_program_oob()
1198 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) | in qcom_spi_program_oob()
1200 cfg1 = ecc_cfg->cfg1; in qcom_spi_program_oob()
1201 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; in qcom_spi_program_oob()
1202 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg; in qcom_spi_program_oob()
1204 col = ecc_cfg->cw_size * (num_cw - 1); in qcom_spi_program_oob()
1206 oob_buf = snandc->qspi->data_buf; in qcom_spi_program_oob()
1208 snandc->buf_count = 0; in qcom_spi_program_oob()
1209 snandc->buf_start = 0; in qcom_spi_program_oob()
1212 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); in qcom_spi_program_oob()
1213 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_program_oob()
1214 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_program_oob()
1215 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_program_oob()
1216 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_program_oob()
1217 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_program_oob()
1218 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg); in qcom_spi_program_oob()
1219 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_program_oob()
1222 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); in qcom_spi_program_oob()
1223 oob_size = snandc->qspi->mtd->oobavail; in qcom_spi_program_oob()
1225 memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data); in qcom_spi_program_oob()
1227 mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size, in qcom_spi_program_oob()
1228 oob_buf, 0, snandc->qspi->mtd->oobavail); in qcom_spi_program_oob()
1230 qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0); in qcom_spi_program_oob()
1235 dev_err(snandc->dev, "failure to write oob\n"); in qcom_spi_program_oob()
1245 if (snandc->qspi->page_rw && snandc->qspi->raw_rw) in qcom_spi_program_execute()
1248 if (snandc->qspi->page_rw) in qcom_spi_program_execute()
1251 if (snandc->qspi->oob_rw) in qcom_spi_program_execute()
1274 if (snandc->qspi->raw_rw) { in qcom_spi_cmd_mapping()
1298 dev_err(snandc->dev, "Opcode not supported: %u\n", opcode); in qcom_spi_cmd_mapping()
1299 return -EOPNOTSUPP; in qcom_spi_cmd_mapping()
1311 ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); in qcom_spi_write_page()
1315 if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) in qcom_spi_write_page()
1316 snandc->qspi->data_buf = (u8 *)op->data.buf.out; in qcom_spi_write_page()
1327 ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); in qcom_spi_send_cmdaddr()
1331 opcode = op->cmd.opcode; in qcom_spi_send_cmdaddr()
1337 snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16); in qcom_spi_send_cmdaddr()
1338 snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff); in qcom_spi_send_cmdaddr()
1339 snandc->qspi->cmd = cpu_to_le32(cmd); in qcom_spi_send_cmdaddr()
1342 snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16); in qcom_spi_send_cmdaddr()
1343 snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff); in qcom_spi_send_cmdaddr()
1344 snandc->qspi->cmd = cpu_to_le32(cmd); in qcom_spi_send_cmdaddr()
1347 snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16); in qcom_spi_send_cmdaddr()
1348 snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xffff); in qcom_spi_send_cmdaddr()
1349 snandc->qspi->cmd = cpu_to_le32(cmd); in qcom_spi_send_cmdaddr()
1355 snandc->buf_count = 0; in qcom_spi_send_cmdaddr()
1356 snandc->buf_start = 0; in qcom_spi_send_cmdaddr()
1360 snandc->regs->cmd = cpu_to_le32(cmd); in qcom_spi_send_cmdaddr()
1361 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_send_cmdaddr()
1362 snandc->regs->addr0 = cpu_to_le32(op->addr.val); in qcom_spi_send_cmdaddr()
1363 snandc->regs->addr1 = cpu_to_le32(0); in qcom_spi_send_cmdaddr()
1365 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); in qcom_spi_send_cmdaddr()
1366 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_send_cmdaddr()
1370 dev_err(snandc->dev, "failure in submitting cmd descriptor\n"); in qcom_spi_send_cmdaddr()
1384 snandc->buf_count = 0; in qcom_spi_io_op()
1385 snandc->buf_start = 0; in qcom_spi_io_op()
1388 opcode = op->cmd.opcode; in qcom_spi_io_op()
1392 snandc->buf_count = 4; in qcom_spi_io_op()
1397 snandc->buf_count = 4; in qcom_spi_io_op()
1402 snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out); in qcom_spi_io_op()
1403 qcom_write_reg_dma(snandc, &snandc->regs->flash_feature, in qcom_spi_io_op()
1413 return -EOPNOTSUPP; in qcom_spi_io_op()
1418 dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode); in qcom_spi_io_op()
1424 memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count); in qcom_spi_io_op()
1429 val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf); in qcom_spi_io_op()
1431 memcpy(op->data.buf.in, &val, snandc->buf_count); in qcom_spi_io_op()
1439 if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4) in qcom_spi_is_page_op()
1442 if (op->data.dir == SPI_MEM_DATA_IN) { in qcom_spi_is_page_op()
1443 if (op->addr.buswidth == 4 && op->data.buswidth == 4) in qcom_spi_is_page_op()
1446 if (op->addr.nbytes == 2 && op->addr.buswidth == 1) in qcom_spi_is_page_op()
1449 } else if (op->data.dir == SPI_MEM_DATA_OUT) { in qcom_spi_is_page_op()
1450 if (op->data.buswidth == 4) in qcom_spi_is_page_op()
1452 if (op->addr.nbytes == 2 && op->addr.buswidth == 1) in qcom_spi_is_page_op()
1464 if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1) in qcom_spi_supports_op()
1470 return ((!op->addr.nbytes || op->addr.buswidth == 1) && in qcom_spi_supports_op()
1471 (!op->dummy.nbytes || op->dummy.buswidth == 1) && in qcom_spi_supports_op()
1472 (!op->data.nbytes || op->data.buswidth == 1)); in qcom_spi_supports_op()
1477 struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller); in qcom_spi_exec_op()
1479 dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode, in qcom_spi_exec_op()
1480 op->addr.val, op->addr.buswidth, op->addr.nbytes, in qcom_spi_exec_op()
1481 op->data.buswidth, op->data.nbytes); in qcom_spi_exec_op()
1484 if (op->data.dir == SPI_MEM_DATA_IN) in qcom_spi_exec_op()
1486 if (op->data.dir == SPI_MEM_DATA_OUT) in qcom_spi_exec_op()
1501 .ecc = true,
1506 struct device *dev = &pdev->dev; in qcom_spi_probe()
1510 struct qpic_ecc *ecc; in qcom_spi_probe() local
1515 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); in qcom_spi_probe()
1516 if (!ecc) in qcom_spi_probe()
1517 return -ENOMEM; in qcom_spi_probe()
1521 return -ENOMEM; in qcom_spi_probe()
1525 return -ENOMEM; in qcom_spi_probe()
1530 qspi->snandc = snandc; in qcom_spi_probe()
1532 snandc->dev = dev; in qcom_spi_probe()
1533 snandc->qspi = qspi; in qcom_spi_probe()
1534 snandc->qspi->ctlr = ctlr; in qcom_spi_probe()
1535 snandc->qspi->ecc = ecc; in qcom_spi_probe()
1539 dev_err(&pdev->dev, "failed to get device data\n"); in qcom_spi_probe()
1540 return -ENODEV; in qcom_spi_probe()
1543 snandc->props = dev_data; in qcom_spi_probe()
1545 snandc->core_clk = devm_clk_get_enabled(dev, "core"); in qcom_spi_probe()
1546 if (IS_ERR(snandc->core_clk)) in qcom_spi_probe()
1547 return PTR_ERR(snandc->core_clk); in qcom_spi_probe()
1549 snandc->aon_clk = devm_clk_get_enabled(dev, "aon"); in qcom_spi_probe()
1550 if (IS_ERR(snandc->aon_clk)) in qcom_spi_probe()
1551 return PTR_ERR(snandc->aon_clk); in qcom_spi_probe()
1553 snandc->qspi->iomacro_clk = devm_clk_get_enabled(dev, "iom"); in qcom_spi_probe()
1554 if (IS_ERR(snandc->qspi->iomacro_clk)) in qcom_spi_probe()
1555 return PTR_ERR(snandc->qspi->iomacro_clk); in qcom_spi_probe()
1557 snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in qcom_spi_probe()
1558 if (IS_ERR(snandc->base)) in qcom_spi_probe()
1559 return PTR_ERR(snandc->base); in qcom_spi_probe()
1561 snandc->base_phys = res->start; in qcom_spi_probe()
1562 snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res), in qcom_spi_probe()
1564 if (dma_mapping_error(dev, snandc->base_dma)) in qcom_spi_probe()
1565 return -ENXIO; in qcom_spi_probe()
1575 /* setup ECC engine */ in qcom_spi_probe()
1576 snandc->qspi->ecc_eng.dev = &pdev->dev; in qcom_spi_probe()
1577 snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; in qcom_spi_probe()
1578 snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined; in qcom_spi_probe()
1579 snandc->qspi->ecc_eng.priv = snandc; in qcom_spi_probe()
1581 ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng); in qcom_spi_probe()
1583 dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret); in qcom_spi_probe()
1587 ctlr->num_chipselect = QPIC_QSPI_NUM_CS; in qcom_spi_probe()
1588 ctlr->mem_ops = &qcom_spi_mem_ops; in qcom_spi_probe()
1589 ctlr->mem_caps = &qcom_spi_mem_caps; in qcom_spi_probe()
1590 ctlr->dev.of_node = pdev->dev.of_node; in qcom_spi_probe()
1591 ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL | in qcom_spi_probe()
1596 dev_err(&pdev->dev, "spi_register_controller failed.\n"); in qcom_spi_probe()
1603 nand_ecc_unregister_on_host_hw_engine(&snandc->qspi->ecc_eng); in qcom_spi_probe()
1607 dma_unmap_resource(dev, res->start, resource_size(res), in qcom_spi_probe()
1619 nand_ecc_unregister_on_host_hw_engine(&snandc->qspi->ecc_eng); in qcom_spi_remove()
1621 dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res), in qcom_spi_remove()
1633 .compatible = "qcom,ipq9574-snand",