Lines Matching +full:tx +full:- +full:threshold
1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #include "spi-pxa2xx.h"
64 u32 threshold; member
81 /* LPSS offset from drv_data->ioaddr */
83 /* Register offsets from drv_data->lpss_base or -1 */
106 .reg_capabilities = -1,
116 .reg_capabilities = -1,
126 .reg_capabilities = -1,
135 .reg_general = -1,
138 .reg_capabilities = -1,
145 .reg_general = -1,
158 .reg_general = -1,
174 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; in lpss_get_config()
179 switch (drv_data->ssp_type) { in is_lpss_ssp()
194 return drv_data->ssp_type == QUARK_X1000_SSP; in is_quark_x1000_ssp()
199 return drv_data->ssp_type == MMP2_SSP; in is_mmp2_ssp()
204 return drv_data->ssp_type == MRFLD_SSP; in is_mrfld_ssp()
215 switch (drv_data->ssp_type) { in pxa2xx_spi_get_ssrc1_change_mask()
228 switch (drv_data->ssp_type) { in pxa2xx_spi_get_rx_default_thre()
242 switch (drv_data->ssp_type) { in pxa2xx_spi_txfifo_full()
262 switch (drv_data->ssp_type) { in pxa2xx_spi_clear_rx_thre()
277 u32 *sccr1_reg, u32 threshold) in pxa2xx_spi_set_rx_thre() argument
279 switch (drv_data->ssp_type) { in pxa2xx_spi_set_rx_thre()
281 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); in pxa2xx_spi_set_rx_thre()
284 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); in pxa2xx_spi_set_rx_thre()
287 *sccr1_reg |= SSCR1_RxTresh(threshold); in pxa2xx_spi_set_rx_thre()
295 switch (drv_data->ssp_type) { in pxa2xx_configure_sscr0()
303 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) in pxa2xx_configure_sscr0()
314 WARN_ON(!drv_data->lpss_base); in __lpss_ssp_read_priv()
315 return readl(drv_data->lpss_base + offset); in __lpss_ssp_read_priv()
321 WARN_ON(!drv_data->lpss_base); in __lpss_ssp_write_priv()
322 writel(value, drv_data->lpss_base + offset); in __lpss_ssp_write_priv()
340 * lpss_ssp_setup - perform LPSS SSP specific setup
352 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset; in lpss_ssp_setup()
356 __lpss_ssp_update_priv(drv_data, config->reg_cs_ctrl, value, value); in lpss_ssp_setup()
359 if (drv_data->controller_info->enable_dma) { in lpss_ssp_setup()
360 __lpss_ssp_update_priv(drv_data, config->reg_ssp, BIT(0), BIT(0)); in lpss_ssp_setup()
362 if (config->reg_general >= 0) { in lpss_ssp_setup()
364 __lpss_ssp_update_priv(drv_data, config->reg_general, value, value); in lpss_ssp_setup()
373 spi_controller_get_devdata(spi->controller); in lpss_ssp_select_cs()
376 cs = spi_get_chipselect(spi, 0) << config->cs_sel_shift; in lpss_ssp_select_cs()
377 if (!__lpss_ssp_update_priv(drv_data, config->reg_cs_ctrl, config->cs_sel_mask, cs)) in lpss_ssp_select_cs()
386 ndelay(1000000000 / (drv_data->controller->max_speed_hz / 2)); in lpss_ssp_select_cs()
392 spi_controller_get_devdata(spi->controller); in lpss_ssp_cs_control()
402 __lpss_ssp_update_priv(drv_data, config->reg_cs_ctrl, mask, enable ? 0 : mask); in lpss_ssp_cs_control()
403 if (config->cs_clk_stays_gated) { in lpss_ssp_cs_control()
421 spi_controller_get_devdata(spi->controller); in cs_assert()
423 if (drv_data->ssp_type == CE4100_SSP) { in cs_assert()
435 spi_controller_get_devdata(spi->controller); in cs_deassert()
438 if (drv_data->ssp_type == CE4100_SSP) in cs_deassert()
466 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); in pxa2xx_spi_flush()
478 pxa_ssp_disable(drv_data->ssp); in pxa2xx_spi_off()
483 u8 n_bytes = drv_data->n_bytes; in null_writer()
486 || (drv_data->tx == drv_data->tx_end)) in null_writer()
490 drv_data->tx += n_bytes; in null_writer()
497 u8 n_bytes = drv_data->n_bytes; in null_reader()
499 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in null_reader()
501 drv_data->rx += n_bytes; in null_reader()
504 return drv_data->rx == drv_data->rx_end; in null_reader()
510 || (drv_data->tx == drv_data->tx_end)) in u8_writer()
513 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); in u8_writer()
514 ++drv_data->tx; in u8_writer()
521 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in u8_reader()
522 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u8_reader()
523 ++drv_data->rx; in u8_reader()
526 return drv_data->rx == drv_data->rx_end; in u8_reader()
532 || (drv_data->tx == drv_data->tx_end)) in u16_writer()
535 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); in u16_writer()
536 drv_data->tx += 2; in u16_writer()
543 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in u16_reader()
544 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u16_reader()
545 drv_data->rx += 2; in u16_reader()
548 return drv_data->rx == drv_data->rx_end; in u16_reader()
554 || (drv_data->tx == drv_data->tx_end)) in u32_writer()
557 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); in u32_writer()
558 drv_data->tx += 4; in u32_writer()
565 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in u32_reader()
566 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u32_reader()
567 drv_data->rx += 4; in u32_reader()
570 return drv_data->rx == drv_data->rx_end; in u32_reader()
575 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold; in reset_sccr1() local
578 if (drv_data->controller->cur_msg) { in reset_sccr1()
579 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi); in reset_sccr1()
580 threshold = chip->threshold; in reset_sccr1()
582 threshold = 0; in reset_sccr1()
585 switch (drv_data->ssp_type) { in reset_sccr1()
597 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold); in reset_sccr1()
603 write_SSSR_CS(drv_data, drv_data->clear_sr); in int_stop_and_reset()
617 dev_err(drv_data->ssp->dev, "%s\n", msg); in int_error_stop()
619 drv_data->controller->cur_msg->status = err; in int_error_stop()
620 spi_finalize_current_transfer(drv_data->controller); in int_error_stop()
627 spi_finalize_current_transfer(drv_data->controller); in int_transfer_complete()
634 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr); in interrupt_transfer()
639 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO); in interrupt_transfer()
644 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO); in interrupt_transfer()
650 if (drv_data->read(drv_data)) { in interrupt_transfer()
656 /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */ in interrupt_transfer()
658 if (drv_data->read(drv_data)) { in interrupt_transfer()
662 } while (drv_data->write(drv_data)); in interrupt_transfer()
664 if (drv_data->read(drv_data)) { in interrupt_transfer()
669 if (drv_data->tx == drv_data->tx_end) { in interrupt_transfer()
677 * PXA25x_SSP has no timeout, set up Rx threshold for in interrupt_transfer()
685 bytes_left = drv_data->rx_end - drv_data->rx; in interrupt_transfer()
686 switch (drv_data->n_bytes) { in interrupt_transfer()
713 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n"); in handle_bad_msg()
720 u32 mask = drv_data->mask_sr; in ssp_int()
729 if (pm_runtime_suspended(drv_data->ssp->dev)) in ssp_int()
755 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); in ssp_int()
758 if (!drv_data->controller->cur_msg) { in ssp_int()
764 return drv_data->transfer_handler(drv_data); in ssp_int()
823 scale = fls_long(q1 - 1); in quark_x1000_get_clk_div()
825 q1 >>= scale - 9; in quark_x1000_get_clk_div()
826 mul >>= scale - 9; in quark_x1000_get_clk_div()
839 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); in quark_x1000_get_clk_div()
844 r2 = abs(fref2 / q2 - rate); in quark_x1000_get_clk_div()
874 r1 = abs(fssp - rate); in quark_x1000_get_clk_div()
885 return q - 1; in quark_x1000_get_clk_div()
890 unsigned long ssp_clk = drv_data->controller->max_speed_hz; in ssp_get_clk_div()
891 const struct ssp_device *ssp = drv_data->ssp; in ssp_get_clk_div()
899 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) in ssp_get_clk_div()
900 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff; in ssp_get_clk_div()
902 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff; in ssp_get_clk_div()
909 spi_get_ctldata(drv_data->controller->cur_msg->spi); in pxa2xx_ssp_get_clk_div()
912 switch (drv_data->ssp_type) { in pxa2xx_ssp_get_clk_div()
914 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); in pxa2xx_ssp_get_clk_div()
929 return drv_data->controller_info->enable_dma && in pxa2xx_spi_can_dma()
930 xfer->len <= MAX_DMA_LEN && in pxa2xx_spi_can_dma()
931 xfer->len >= drv_data->controller_info->dma_burst_size; in pxa2xx_spi_can_dma()
951 if (transfer->len > MAX_DMA_LEN && drv_data->controller_info->enable_dma) { in pxa2xx_spi_transfer_one()
953 dev_warn_ratelimited(&spi->dev, in pxa2xx_spi_transfer_one()
955 transfer->len, MAX_DMA_LEN); in pxa2xx_spi_transfer_one()
960 dev_err(&spi->dev, "Flush failed\n"); in pxa2xx_spi_transfer_one()
961 return -EIO; in pxa2xx_spi_transfer_one()
963 drv_data->tx = (void *)transfer->tx_buf; in pxa2xx_spi_transfer_one()
964 drv_data->tx_end = drv_data->tx + transfer->len; in pxa2xx_spi_transfer_one()
965 drv_data->rx = transfer->rx_buf; in pxa2xx_spi_transfer_one()
966 drv_data->rx_end = drv_data->rx + transfer->len; in pxa2xx_spi_transfer_one()
969 bits = transfer->bits_per_word; in pxa2xx_spi_transfer_one()
970 speed = transfer->speed_hz; in pxa2xx_spi_transfer_one()
975 drv_data->n_bytes = 1; in pxa2xx_spi_transfer_one()
976 drv_data->read = drv_data->rx ? u8_reader : null_reader; in pxa2xx_spi_transfer_one()
977 drv_data->write = drv_data->tx ? u8_writer : null_writer; in pxa2xx_spi_transfer_one()
979 drv_data->n_bytes = 2; in pxa2xx_spi_transfer_one()
980 drv_data->read = drv_data->rx ? u16_reader : null_reader; in pxa2xx_spi_transfer_one()
981 drv_data->write = drv_data->tx ? u16_writer : null_writer; in pxa2xx_spi_transfer_one()
983 drv_data->n_bytes = 4; in pxa2xx_spi_transfer_one()
984 drv_data->read = drv_data->rx ? u32_reader : null_reader; in pxa2xx_spi_transfer_one()
985 drv_data->write = drv_data->tx ? u32_writer : null_writer; in pxa2xx_spi_transfer_one()
992 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; in pxa2xx_spi_transfer_one()
999 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; in pxa2xx_spi_transfer_one()
1000 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); in pxa2xx_spi_transfer_one()
1005 drv_data->transfer_handler = interrupt_transfer; in pxa2xx_spi_transfer_one()
1008 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; in pxa2xx_spi_transfer_one()
1009 write_SSSR_CS(drv_data, drv_data->clear_sr); in pxa2xx_spi_transfer_one()
1015 dev_dbg(&spi->dev, "%u Hz actual, %s\n", in pxa2xx_spi_transfer_one()
1016 controller->max_speed_hz in pxa2xx_spi_transfer_one()
1020 dev_dbg(&spi->dev, "%u Hz actual, %s\n", in pxa2xx_spi_transfer_one()
1021 controller->max_speed_hz / 2 in pxa2xx_spi_transfer_one()
1026 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold); in pxa2xx_spi_transfer_one()
1027 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold); in pxa2xx_spi_transfer_one()
1034 thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold); in pxa2xx_spi_transfer_one()
1035 thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold); in pxa2xx_spi_transfer_one()
1041 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate); in pxa2xx_spi_transfer_one()
1045 pxa_ssp_disable(drv_data->ssp); in pxa2xx_spi_transfer_one()
1057 pxa_ssp_enable(drv_data->ssp); in pxa2xx_spi_transfer_one()
1063 /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */ in pxa2xx_spi_transfer_one()
1064 dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level); in pxa2xx_spi_transfer_one()
1065 if (tx_level > transfer->len) in pxa2xx_spi_transfer_one()
1066 tx_level = transfer->len; in pxa2xx_spi_transfer_one()
1067 drv_data->tx += tx_level; in pxa2xx_spi_transfer_one()
1072 while (drv_data->write(drv_data)) in pxa2xx_spi_transfer_one()
1074 if (drv_data->gpiod_ready) { in pxa2xx_spi_transfer_one()
1075 gpiod_set_value(drv_data->gpiod_ready, 1); in pxa2xx_spi_transfer_one()
1077 gpiod_set_value(drv_data->gpiod_ready, 0); in pxa2xx_spi_transfer_one()
1094 int_error_stop(drv_data, "transfer aborted", -EINTR); in pxa2xx_spi_target_abort()
1116 if (atomic_read(&drv_data->dma_running)) in pxa2xx_spi_handle_err()
1135 spi_controller_get_devdata(spi->controller); in setup()
1138 switch (drv_data->ssp_type) { in setup()
1161 tx_thres = config->tx_threshold_lo; in setup()
1162 tx_hi_thres = config->tx_threshold_hi; in setup()
1163 rx_thres = config->rx_threshold; in setup()
1167 if (spi_controller_is_target(drv_data->controller)) { in setup()
1177 if (drv_data->ssp_type == CE4100_SSP) { in setup()
1179 dev_err(&spi->dev, "failed setup: cs number must not be > 4.\n"); in setup()
1180 return -EINVAL; in setup()
1189 return -ENOMEM; in setup()
1192 chip->cr1 = 0; in setup()
1193 if (spi_controller_is_target(drv_data->controller)) { in setup()
1194 chip->cr1 |= SSCR1_SCFR; in setup()
1195 chip->cr1 |= SSCR1_SCLKDIR; in setup()
1196 chip->cr1 |= SSCR1_SFRMDIR; in setup()
1197 chip->cr1 |= SSCR1_SPH; in setup()
1201 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); in setup()
1202 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | in setup()
1207 chip->lpss_rx_threshold = rx_thres; in setup()
1208 chip->lpss_tx_threshold = tx_thres; in setup()
1211 switch (drv_data->ssp_type) { in setup()
1213 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) in setup()
1219 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | in setup()
1223 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | in setup()
1228 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); in setup()
1229 chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) | in setup()
1230 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0); in setup()
1232 if (spi->mode & SPI_LOOP) in setup()
1233 chip->cr1 |= SSCR1_LBM; in setup()
1252 switch (drv_data->ssp_type) { in pxa2xx_spi_fw_translate_cs()
1260 return cs - 1; in pxa2xx_spi_fw_translate_cs()
1281 if (platform_info->is_target) in pxa2xx_spi_probe()
1286 return dev_err_probe(dev, -ENOMEM, "cannot alloc spi_controller\n"); in pxa2xx_spi_probe()
1289 drv_data->controller = controller; in pxa2xx_spi_probe()
1290 drv_data->controller_info = platform_info; in pxa2xx_spi_probe()
1291 drv_data->ssp = ssp; in pxa2xx_spi_probe()
1293 device_set_node(&controller->dev, dev_fwnode(dev)); in pxa2xx_spi_probe()
1295 /* The spi->mode bits understood by this driver: */ in pxa2xx_spi_probe()
1296 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in pxa2xx_spi_probe()
1298 controller->bus_num = ssp->port_id; in pxa2xx_spi_probe()
1299 controller->dma_alignment = DMA_ALIGNMENT; in pxa2xx_spi_probe()
1300 controller->cleanup = cleanup; in pxa2xx_spi_probe()
1301 controller->setup = setup; in pxa2xx_spi_probe()
1302 controller->set_cs = pxa2xx_spi_set_cs; in pxa2xx_spi_probe()
1303 controller->transfer_one = pxa2xx_spi_transfer_one; in pxa2xx_spi_probe()
1304 controller->target_abort = pxa2xx_spi_target_abort; in pxa2xx_spi_probe()
1305 controller->handle_err = pxa2xx_spi_handle_err; in pxa2xx_spi_probe()
1306 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; in pxa2xx_spi_probe()
1307 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs; in pxa2xx_spi_probe()
1308 controller->auto_runtime_pm = true; in pxa2xx_spi_probe()
1309 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; in pxa2xx_spi_probe()
1311 drv_data->ssp_type = ssp->type; in pxa2xx_spi_probe()
1314 switch (drv_data->ssp_type) { in pxa2xx_spi_probe()
1316 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in pxa2xx_spi_probe()
1319 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); in pxa2xx_spi_probe()
1323 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; in pxa2xx_spi_probe()
1324 drv_data->dma_cr1 = 0; in pxa2xx_spi_probe()
1325 drv_data->clear_sr = SSSR_ROR; in pxa2xx_spi_probe()
1326 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; in pxa2xx_spi_probe()
1328 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in pxa2xx_spi_probe()
1329 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; in pxa2xx_spi_probe()
1330 drv_data->dma_cr1 = DEFAULT_DMA_CR1; in pxa2xx_spi_probe()
1331 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; in pxa2xx_spi_probe()
1332 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS in pxa2xx_spi_probe()
1336 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), in pxa2xx_spi_probe()
1339 return dev_err_probe(dev, status, "cannot get IRQ %d\n", ssp->irq); in pxa2xx_spi_probe()
1342 if (platform_info->enable_dma) { in pxa2xx_spi_probe()
1346 platform_info->enable_dma = false; in pxa2xx_spi_probe()
1348 controller->can_dma = pxa2xx_spi_can_dma; in pxa2xx_spi_probe()
1349 controller->max_dma_len = MAX_DMA_LEN; in pxa2xx_spi_probe()
1350 controller->max_transfer_size = in pxa2xx_spi_probe()
1353 dev_dbg(dev, "DMA burst size set to %u\n", platform_info->dma_burst_size); in pxa2xx_spi_probe()
1358 status = clk_prepare_enable(ssp->clk); in pxa2xx_spi_probe()
1362 controller->max_speed_hz = clk_get_rate(ssp->clk); in pxa2xx_spi_probe()
1368 controller->min_speed_hz = in pxa2xx_spi_probe()
1369 DIV_ROUND_UP(controller->max_speed_hz, 4096); in pxa2xx_spi_probe()
1371 controller->min_speed_hz = in pxa2xx_spi_probe()
1372 DIV_ROUND_UP(controller->max_speed_hz, 512); in pxa2xx_spi_probe()
1377 switch (drv_data->ssp_type) { in pxa2xx_spi_probe()
1424 if (config->reg_capabilities >= 0) { in pxa2xx_spi_probe()
1426 config->reg_capabilities); in pxa2xx_spi_probe()
1429 platform_info->num_chipselect = ffz(tmp); in pxa2xx_spi_probe()
1432 controller->num_chipselect = platform_info->num_chipselect; in pxa2xx_spi_probe()
1433 controller->use_gpio_descriptors = true; in pxa2xx_spi_probe()
1435 if (platform_info->is_target) { in pxa2xx_spi_probe()
1436 drv_data->gpiod_ready = devm_gpiod_get_optional(dev, in pxa2xx_spi_probe()
1438 if (IS_ERR(drv_data->gpiod_ready)) { in pxa2xx_spi_probe()
1439 status = PTR_ERR(drv_data->gpiod_ready); in pxa2xx_spi_probe()
1455 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_probe()
1459 free_irq(ssp->irq, drv_data); in pxa2xx_spi_probe()
1468 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_remove()
1470 spi_unregister_controller(drv_data->controller); in pxa2xx_spi_remove()
1474 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_remove()
1477 if (drv_data->controller_info->enable_dma) in pxa2xx_spi_remove()
1481 free_irq(ssp->irq, drv_data); in pxa2xx_spi_remove()
1488 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_suspend()
1491 status = spi_controller_suspend(drv_data->controller); in pxa2xx_spi_suspend()
1498 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_suspend()
1506 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_resume()
1511 status = clk_prepare_enable(ssp->clk); in pxa2xx_spi_resume()
1517 return spi_controller_resume(drv_data->controller); in pxa2xx_spi_resume()
1524 clk_disable_unprepare(drv_data->ssp->clk); in pxa2xx_spi_runtime_suspend()
1532 return clk_prepare_enable(drv_data->ssp->clk); in pxa2xx_spi_runtime_resume()