Lines Matching +full:tx +full:- +full:output +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #include "spi-pxa2xx.h"
80 /* LPSS offset from drv_data->ioaddr */
82 /* Register offsets from drv_data->lpss_base or -1 */
105 .reg_capabilities = -1,
115 .reg_capabilities = -1,
125 .reg_capabilities = -1,
134 .reg_general = -1,
137 .reg_capabilities = -1,
144 .reg_general = -1,
157 .reg_general = -1,
173 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; in lpss_get_config()
178 switch (drv_data->ssp_type) { in is_lpss_ssp()
193 return drv_data->ssp_type == QUARK_X1000_SSP; in is_quark_x1000_ssp()
198 return drv_data->ssp_type == MMP2_SSP; in is_mmp2_ssp()
203 return drv_data->ssp_type == MRFLD_SSP; in is_mrfld_ssp()
214 switch (drv_data->ssp_type) { in pxa2xx_spi_get_ssrc1_change_mask()
227 switch (drv_data->ssp_type) { in pxa2xx_spi_get_rx_default_thre()
241 switch (drv_data->ssp_type) { in pxa2xx_spi_txfifo_full()
261 switch (drv_data->ssp_type) { in pxa2xx_spi_clear_rx_thre()
278 switch (drv_data->ssp_type) { in pxa2xx_spi_set_rx_thre()
294 switch (drv_data->ssp_type) { in pxa2xx_configure_sscr0()
302 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) in pxa2xx_configure_sscr0()
313 WARN_ON(!drv_data->lpss_base); in __lpss_ssp_read_priv()
314 return readl(drv_data->lpss_base + offset); in __lpss_ssp_read_priv()
320 WARN_ON(!drv_data->lpss_base); in __lpss_ssp_write_priv()
321 writel(value, drv_data->lpss_base + offset); in __lpss_ssp_write_priv()
325 * lpss_ssp_setup - perform LPSS SSP specific setup
333 const struct lpss_config *config; in lpss_ssp_setup() local
336 config = lpss_get_config(drv_data); in lpss_ssp_setup()
337 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset; in lpss_ssp_setup()
340 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); in lpss_ssp_setup()
343 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); in lpss_ssp_setup()
346 if (drv_data->controller_info->enable_dma) { in lpss_ssp_setup()
347 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); in lpss_ssp_setup()
349 if (config->reg_general >= 0) { in lpss_ssp_setup()
351 config->reg_general); in lpss_ssp_setup()
354 config->reg_general, value); in lpss_ssp_setup()
360 const struct lpss_config *config) in lpss_ssp_select_cs() argument
363 spi_controller_get_devdata(spi->controller); in lpss_ssp_select_cs()
366 if (!config->cs_sel_mask) in lpss_ssp_select_cs()
369 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); in lpss_ssp_select_cs()
372 cs <<= config->cs_sel_shift; in lpss_ssp_select_cs()
373 if (cs != (value & config->cs_sel_mask)) { in lpss_ssp_select_cs()
375 * When switching another chip select output active the in lpss_ssp_select_cs()
376 * output must be selected first and wait 2 ssp_clk cycles in lpss_ssp_select_cs()
379 * output select is latched but state control is not. in lpss_ssp_select_cs()
381 value &= ~config->cs_sel_mask; in lpss_ssp_select_cs()
384 config->reg_cs_ctrl, value); in lpss_ssp_select_cs()
386 (drv_data->controller->max_speed_hz / 2)); in lpss_ssp_select_cs()
393 spi_controller_get_devdata(spi->controller); in lpss_ssp_cs_control()
394 const struct lpss_config *config; in lpss_ssp_cs_control() local
397 config = lpss_get_config(drv_data); in lpss_ssp_cs_control()
400 lpss_ssp_select_cs(spi, config); in lpss_ssp_cs_control()
402 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); in lpss_ssp_cs_control()
407 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); in lpss_ssp_cs_control()
408 if (config->cs_clk_stays_gated) { in lpss_ssp_cs_control()
429 spi_controller_get_devdata(spi->controller); in cs_assert()
431 if (drv_data->ssp_type == CE4100_SSP) { in cs_assert()
443 spi_controller_get_devdata(spi->controller); in cs_deassert()
446 if (drv_data->ssp_type == CE4100_SSP) in cs_deassert()
474 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); in pxa2xx_spi_flush()
486 pxa_ssp_disable(drv_data->ssp); in pxa2xx_spi_off()
491 u8 n_bytes = drv_data->n_bytes; in null_writer()
494 || (drv_data->tx == drv_data->tx_end)) in null_writer()
498 drv_data->tx += n_bytes; in null_writer()
505 u8 n_bytes = drv_data->n_bytes; in null_reader()
507 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in null_reader()
509 drv_data->rx += n_bytes; in null_reader()
512 return drv_data->rx == drv_data->rx_end; in null_reader()
518 || (drv_data->tx == drv_data->tx_end)) in u8_writer()
521 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); in u8_writer()
522 ++drv_data->tx; in u8_writer()
529 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in u8_reader()
530 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u8_reader()
531 ++drv_data->rx; in u8_reader()
534 return drv_data->rx == drv_data->rx_end; in u8_reader()
540 || (drv_data->tx == drv_data->tx_end)) in u16_writer()
543 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); in u16_writer()
544 drv_data->tx += 2; in u16_writer()
551 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in u16_reader()
552 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u16_reader()
553 drv_data->rx += 2; in u16_reader()
556 return drv_data->rx == drv_data->rx_end; in u16_reader()
562 || (drv_data->tx == drv_data->tx_end)) in u32_writer()
565 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); in u32_writer()
566 drv_data->tx += 4; in u32_writer()
573 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in u32_reader()
574 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u32_reader()
575 drv_data->rx += 4; in u32_reader()
578 return drv_data->rx == drv_data->rx_end; in u32_reader()
583 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold; in reset_sccr1()
586 if (drv_data->controller->cur_msg) { in reset_sccr1()
587 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi); in reset_sccr1()
588 threshold = chip->threshold; in reset_sccr1()
593 switch (drv_data->ssp_type) { in reset_sccr1()
611 write_SSSR_CS(drv_data, drv_data->clear_sr); in int_stop_and_reset()
625 dev_err(drv_data->ssp->dev, "%s\n", msg); in int_error_stop()
627 drv_data->controller->cur_msg->status = err; in int_error_stop()
628 spi_finalize_current_transfer(drv_data->controller); in int_error_stop()
635 spi_finalize_current_transfer(drv_data->controller); in int_transfer_complete()
642 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr); in interrupt_transfer()
647 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO); in interrupt_transfer()
652 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO); in interrupt_transfer()
658 if (drv_data->read(drv_data)) { in interrupt_transfer()
664 /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */ in interrupt_transfer()
666 if (drv_data->read(drv_data)) { in interrupt_transfer()
670 } while (drv_data->write(drv_data)); in interrupt_transfer()
672 if (drv_data->read(drv_data)) { in interrupt_transfer()
677 if (drv_data->tx == drv_data->tx_end) { in interrupt_transfer()
693 bytes_left = drv_data->rx_end - drv_data->rx; in interrupt_transfer()
694 switch (drv_data->n_bytes) { in interrupt_transfer()
721 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n"); in handle_bad_msg()
728 u32 mask = drv_data->mask_sr; in ssp_int()
737 if (pm_runtime_suspended(drv_data->ssp->dev)) in ssp_int()
763 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); in ssp_int()
766 if (!drv_data->controller->cur_msg) { in ssp_int()
772 return drv_data->transfer_handler(drv_data); in ssp_int()
831 scale = fls_long(q1 - 1); in quark_x1000_get_clk_div()
833 q1 >>= scale - 9; in quark_x1000_get_clk_div()
834 mul >>= scale - 9; in quark_x1000_get_clk_div()
847 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); in quark_x1000_get_clk_div()
852 r2 = abs(fref2 / q2 - rate); in quark_x1000_get_clk_div()
882 r1 = abs(fssp - rate); in quark_x1000_get_clk_div()
893 return q - 1; in quark_x1000_get_clk_div()
898 unsigned long ssp_clk = drv_data->controller->max_speed_hz; in ssp_get_clk_div()
899 const struct ssp_device *ssp = drv_data->ssp; in ssp_get_clk_div()
907 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) in ssp_get_clk_div()
908 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff; in ssp_get_clk_div()
910 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff; in ssp_get_clk_div()
917 spi_get_ctldata(drv_data->controller->cur_msg->spi); in pxa2xx_ssp_get_clk_div()
920 switch (drv_data->ssp_type) { in pxa2xx_ssp_get_clk_div()
922 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); in pxa2xx_ssp_get_clk_div()
937 return drv_data->controller_info->enable_dma && in pxa2xx_spi_can_dma()
938 xfer->len <= MAX_DMA_LEN && in pxa2xx_spi_can_dma()
939 xfer->len >= drv_data->controller_info->dma_burst_size; in pxa2xx_spi_can_dma()
959 if (transfer->len > MAX_DMA_LEN && drv_data->controller_info->enable_dma) { in pxa2xx_spi_transfer_one()
961 dev_warn_ratelimited(&spi->dev, in pxa2xx_spi_transfer_one()
963 transfer->len, MAX_DMA_LEN); in pxa2xx_spi_transfer_one()
968 dev_err(&spi->dev, "Flush failed\n"); in pxa2xx_spi_transfer_one()
969 return -EIO; in pxa2xx_spi_transfer_one()
971 drv_data->tx = (void *)transfer->tx_buf; in pxa2xx_spi_transfer_one()
972 drv_data->tx_end = drv_data->tx + transfer->len; in pxa2xx_spi_transfer_one()
973 drv_data->rx = transfer->rx_buf; in pxa2xx_spi_transfer_one()
974 drv_data->rx_end = drv_data->rx + transfer->len; in pxa2xx_spi_transfer_one()
977 bits = transfer->bits_per_word; in pxa2xx_spi_transfer_one()
978 speed = transfer->speed_hz; in pxa2xx_spi_transfer_one()
983 drv_data->n_bytes = 1; in pxa2xx_spi_transfer_one()
984 drv_data->read = drv_data->rx ? u8_reader : null_reader; in pxa2xx_spi_transfer_one()
985 drv_data->write = drv_data->tx ? u8_writer : null_writer; in pxa2xx_spi_transfer_one()
987 drv_data->n_bytes = 2; in pxa2xx_spi_transfer_one()
988 drv_data->read = drv_data->rx ? u16_reader : null_reader; in pxa2xx_spi_transfer_one()
989 drv_data->write = drv_data->tx ? u16_writer : null_writer; in pxa2xx_spi_transfer_one()
991 drv_data->n_bytes = 4; in pxa2xx_spi_transfer_one()
992 drv_data->read = drv_data->rx ? u32_reader : null_reader; in pxa2xx_spi_transfer_one()
993 drv_data->write = drv_data->tx ? u32_writer : null_writer; in pxa2xx_spi_transfer_one()
1000 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; in pxa2xx_spi_transfer_one()
1007 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; in pxa2xx_spi_transfer_one()
1008 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); in pxa2xx_spi_transfer_one()
1013 drv_data->transfer_handler = interrupt_transfer; in pxa2xx_spi_transfer_one()
1016 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; in pxa2xx_spi_transfer_one()
1017 write_SSSR_CS(drv_data, drv_data->clear_sr); in pxa2xx_spi_transfer_one()
1023 dev_dbg(&spi->dev, "%u Hz actual, %s\n", in pxa2xx_spi_transfer_one()
1024 controller->max_speed_hz in pxa2xx_spi_transfer_one()
1028 dev_dbg(&spi->dev, "%u Hz actual, %s\n", in pxa2xx_spi_transfer_one()
1029 controller->max_speed_hz / 2 in pxa2xx_spi_transfer_one()
1034 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold); in pxa2xx_spi_transfer_one()
1035 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold); in pxa2xx_spi_transfer_one()
1042 thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold); in pxa2xx_spi_transfer_one()
1043 thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold); in pxa2xx_spi_transfer_one()
1049 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate); in pxa2xx_spi_transfer_one()
1053 pxa_ssp_disable(drv_data->ssp); in pxa2xx_spi_transfer_one()
1065 pxa_ssp_enable(drv_data->ssp); in pxa2xx_spi_transfer_one()
1071 /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */ in pxa2xx_spi_transfer_one()
1072 dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level); in pxa2xx_spi_transfer_one()
1073 if (tx_level > transfer->len) in pxa2xx_spi_transfer_one()
1074 tx_level = transfer->len; in pxa2xx_spi_transfer_one()
1075 drv_data->tx += tx_level; in pxa2xx_spi_transfer_one()
1080 while (drv_data->write(drv_data)) in pxa2xx_spi_transfer_one()
1082 if (drv_data->gpiod_ready) { in pxa2xx_spi_transfer_one()
1083 gpiod_set_value(drv_data->gpiod_ready, 1); in pxa2xx_spi_transfer_one()
1085 gpiod_set_value(drv_data->gpiod_ready, 0); in pxa2xx_spi_transfer_one()
1102 int_error_stop(drv_data, "transfer aborted", -EINTR); in pxa2xx_spi_target_abort()
1124 if (atomic_read(&drv_data->dma_running)) in pxa2xx_spi_handle_err()
1141 const struct lpss_config *config; in setup() local
1143 spi_controller_get_devdata(spi->controller); in setup()
1146 switch (drv_data->ssp_type) { in setup()
1168 config = lpss_get_config(drv_data); in setup()
1169 tx_thres = config->tx_threshold_lo; in setup()
1170 tx_hi_thres = config->tx_threshold_hi; in setup()
1171 rx_thres = config->rx_threshold; in setup()
1175 if (spi_controller_is_target(drv_data->controller)) { in setup()
1185 if (drv_data->ssp_type == CE4100_SSP) { in setup()
1187 dev_err(&spi->dev, "failed setup: cs number must not be > 4.\n"); in setup()
1188 return -EINVAL; in setup()
1197 return -ENOMEM; in setup()
1200 chip->cr1 = 0; in setup()
1201 if (spi_controller_is_target(drv_data->controller)) { in setup()
1202 chip->cr1 |= SSCR1_SCFR; in setup()
1203 chip->cr1 |= SSCR1_SCLKDIR; in setup()
1204 chip->cr1 |= SSCR1_SFRMDIR; in setup()
1205 chip->cr1 |= SSCR1_SPH; in setup()
1209 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); in setup()
1210 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | in setup()
1215 chip->lpss_rx_threshold = rx_thres; in setup()
1216 chip->lpss_tx_threshold = tx_thres; in setup()
1219 switch (drv_data->ssp_type) { in setup()
1221 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) in setup()
1227 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | in setup()
1231 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | in setup()
1236 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); in setup()
1237 chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) | in setup()
1238 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0); in setup()
1240 if (spi->mode & SPI_LOOP) in setup()
1241 chip->cr1 |= SSCR1_LBM; in setup()
1260 switch (drv_data->ssp_type) { in pxa2xx_spi_fw_translate_cs()
1268 return cs - 1; in pxa2xx_spi_fw_translate_cs()
1285 const struct lpss_config *config; in pxa2xx_spi_probe() local
1289 if (platform_info->is_target) in pxa2xx_spi_probe()
1294 return dev_err_probe(dev, -ENOMEM, "cannot alloc spi_controller\n"); in pxa2xx_spi_probe()
1297 drv_data->controller = controller; in pxa2xx_spi_probe()
1298 drv_data->controller_info = platform_info; in pxa2xx_spi_probe()
1299 drv_data->ssp = ssp; in pxa2xx_spi_probe()
1301 device_set_node(&controller->dev, dev_fwnode(dev)); in pxa2xx_spi_probe()
1303 /* The spi->mode bits understood by this driver: */ in pxa2xx_spi_probe()
1304 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in pxa2xx_spi_probe()
1306 controller->bus_num = ssp->port_id; in pxa2xx_spi_probe()
1307 controller->dma_alignment = DMA_ALIGNMENT; in pxa2xx_spi_probe()
1308 controller->cleanup = cleanup; in pxa2xx_spi_probe()
1309 controller->setup = setup; in pxa2xx_spi_probe()
1310 controller->set_cs = pxa2xx_spi_set_cs; in pxa2xx_spi_probe()
1311 controller->transfer_one = pxa2xx_spi_transfer_one; in pxa2xx_spi_probe()
1312 controller->target_abort = pxa2xx_spi_target_abort; in pxa2xx_spi_probe()
1313 controller->handle_err = pxa2xx_spi_handle_err; in pxa2xx_spi_probe()
1314 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; in pxa2xx_spi_probe()
1315 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs; in pxa2xx_spi_probe()
1316 controller->auto_runtime_pm = true; in pxa2xx_spi_probe()
1317 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; in pxa2xx_spi_probe()
1319 drv_data->ssp_type = ssp->type; in pxa2xx_spi_probe()
1322 switch (drv_data->ssp_type) { in pxa2xx_spi_probe()
1324 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in pxa2xx_spi_probe()
1327 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); in pxa2xx_spi_probe()
1331 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; in pxa2xx_spi_probe()
1332 drv_data->dma_cr1 = 0; in pxa2xx_spi_probe()
1333 drv_data->clear_sr = SSSR_ROR; in pxa2xx_spi_probe()
1334 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; in pxa2xx_spi_probe()
1336 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in pxa2xx_spi_probe()
1337 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; in pxa2xx_spi_probe()
1338 drv_data->dma_cr1 = DEFAULT_DMA_CR1; in pxa2xx_spi_probe()
1339 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; in pxa2xx_spi_probe()
1340 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS in pxa2xx_spi_probe()
1344 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), in pxa2xx_spi_probe()
1347 return dev_err_probe(dev, status, "cannot get IRQ %d\n", ssp->irq); in pxa2xx_spi_probe()
1350 if (platform_info->enable_dma) { in pxa2xx_spi_probe()
1354 platform_info->enable_dma = false; in pxa2xx_spi_probe()
1356 controller->can_dma = pxa2xx_spi_can_dma; in pxa2xx_spi_probe()
1357 controller->max_dma_len = MAX_DMA_LEN; in pxa2xx_spi_probe()
1358 controller->max_transfer_size = in pxa2xx_spi_probe()
1361 dev_dbg(dev, "DMA burst size set to %u\n", platform_info->dma_burst_size); in pxa2xx_spi_probe()
1366 status = clk_prepare_enable(ssp->clk); in pxa2xx_spi_probe()
1370 controller->max_speed_hz = clk_get_rate(ssp->clk); in pxa2xx_spi_probe()
1376 controller->min_speed_hz = in pxa2xx_spi_probe()
1377 DIV_ROUND_UP(controller->max_speed_hz, 4096); in pxa2xx_spi_probe()
1379 controller->min_speed_hz = in pxa2xx_spi_probe()
1380 DIV_ROUND_UP(controller->max_speed_hz, 512); in pxa2xx_spi_probe()
1385 switch (drv_data->ssp_type) { in pxa2xx_spi_probe()
1431 config = lpss_get_config(drv_data); in pxa2xx_spi_probe()
1432 if (config->reg_capabilities >= 0) { in pxa2xx_spi_probe()
1434 config->reg_capabilities); in pxa2xx_spi_probe()
1437 platform_info->num_chipselect = ffz(tmp); in pxa2xx_spi_probe()
1440 controller->num_chipselect = platform_info->num_chipselect; in pxa2xx_spi_probe()
1441 controller->use_gpio_descriptors = true; in pxa2xx_spi_probe()
1443 if (platform_info->is_target) { in pxa2xx_spi_probe()
1444 drv_data->gpiod_ready = devm_gpiod_get_optional(dev, in pxa2xx_spi_probe()
1446 if (IS_ERR(drv_data->gpiod_ready)) { in pxa2xx_spi_probe()
1447 status = PTR_ERR(drv_data->gpiod_ready); in pxa2xx_spi_probe()
1463 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_probe()
1467 free_irq(ssp->irq, drv_data); in pxa2xx_spi_probe()
1476 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_remove()
1478 spi_unregister_controller(drv_data->controller); in pxa2xx_spi_remove()
1482 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_remove()
1485 if (drv_data->controller_info->enable_dma) in pxa2xx_spi_remove()
1489 free_irq(ssp->irq, drv_data); in pxa2xx_spi_remove()
1496 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_suspend()
1499 status = spi_controller_suspend(drv_data->controller); in pxa2xx_spi_suspend()
1506 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_suspend()
1514 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_resume()
1519 status = clk_prepare_enable(ssp->clk); in pxa2xx_spi_resume()
1525 return spi_controller_resume(drv_data->controller); in pxa2xx_spi_resume()
1532 clk_disable_unprepare(drv_data->ssp->clk); in pxa2xx_spi_runtime_suspend()
1540 return clk_prepare_enable(drv_data->ssp->clk); in pxa2xx_spi_runtime_resume()