Lines Matching refs:SPI_DMA_ADDR_BASE
60 #define SPI_DMA_ADDR_BASE (0x1000) macro
61 #define SPI_DMA_GLOBAL_WR_ENGINE_EN (SPI_DMA_ADDR_BASE + 0x0C)
62 #define SPI_DMA_WR_DOORBELL_REG (SPI_DMA_ADDR_BASE + 0x10)
63 #define SPI_DMA_GLOBAL_RD_ENGINE_EN (SPI_DMA_ADDR_BASE + 0x2C)
64 #define SPI_DMA_RD_DOORBELL_REG (SPI_DMA_ADDR_BASE + 0x30)
65 #define SPI_DMA_INTR_WR_STS (SPI_DMA_ADDR_BASE + 0x4C)
66 #define SPI_DMA_WR_INT_MASK (SPI_DMA_ADDR_BASE + 0x54)
67 #define SPI_DMA_INTR_WR_CLR (SPI_DMA_ADDR_BASE + 0x58)
68 #define SPI_DMA_ERR_WR_STS (SPI_DMA_ADDR_BASE + 0x5C)
69 #define SPI_DMA_INTR_IMWR_WDONE_LOW (SPI_DMA_ADDR_BASE + 0x60)
70 #define SPI_DMA_INTR_IMWR_WDONE_HIGH (SPI_DMA_ADDR_BASE + 0x64)
71 #define SPI_DMA_INTR_IMWR_WABORT_LOW (SPI_DMA_ADDR_BASE + 0x68)
72 #define SPI_DMA_INTR_IMWR_WABORT_HIGH (SPI_DMA_ADDR_BASE + 0x6C)
73 #define SPI_DMA_INTR_WR_IMWR_DATA (SPI_DMA_ADDR_BASE + 0x70)
74 #define SPI_DMA_INTR_RD_STS (SPI_DMA_ADDR_BASE + 0xA0)
75 #define SPI_DMA_RD_INT_MASK (SPI_DMA_ADDR_BASE + 0xA8)
76 #define SPI_DMA_INTR_RD_CLR (SPI_DMA_ADDR_BASE + 0xAC)
77 #define SPI_DMA_ERR_RD_STS (SPI_DMA_ADDR_BASE + 0xB8)
78 #define SPI_DMA_INTR_IMWR_RDONE_LOW (SPI_DMA_ADDR_BASE + 0xCC)
79 #define SPI_DMA_INTR_IMWR_RDONE_HIGH (SPI_DMA_ADDR_BASE + 0xD0)
80 #define SPI_DMA_INTR_IMWR_RABORT_LOW (SPI_DMA_ADDR_BASE + 0xD4)
81 #define SPI_DMA_INTR_IMWR_RABORT_HIGH (SPI_DMA_ADDR_BASE + 0xD8)
82 #define SPI_DMA_INTR_RD_IMWR_DATA (SPI_DMA_ADDR_BASE + 0xDC)
84 #define SPI_DMA_CH0_WR_BASE (SPI_DMA_ADDR_BASE + 0x200)
85 #define SPI_DMA_CH0_RD_BASE (SPI_DMA_ADDR_BASE + 0x300)
86 #define SPI_DMA_CH1_WR_BASE (SPI_DMA_ADDR_BASE + 0x400)
87 #define SPI_DMA_CH1_RD_BASE (SPI_DMA_ADDR_BASE + 0x500)