Lines Matching +full:spi +full:- +full:sck +full:- +full:cs +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
28 #include <linux/spi/spi.h>
32 #include <linux/platform_data/spi-omap2-mcspi.h>
49 /* per-channel banks, 0x14 bytes each, first is: */
56 /* per-register bitmasks: */
92 /* We have 2 DMA channels per CS, one for RX and one for TX */
117 struct list_head cs; member
154 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
161 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
164 static inline void mcspi_write_cs_reg(const struct spi_device *spi, in mcspi_write_cs_reg() argument
167 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
169 writel_relaxed(val, cs->base + idx); in mcspi_write_cs_reg()
172 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) in mcspi_read_cs_reg() argument
174 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_read_cs_reg() local
176 return readl_relaxed(cs->base + idx); in mcspi_read_cs_reg()
179 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) in mcspi_cached_chconf0() argument
181 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_cached_chconf0() local
183 return cs->chconf0; in mcspi_cached_chconf0()
186 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) in mcspi_write_chconf0() argument
188 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_chconf0() local
190 cs->chconf0 = val; in mcspi_write_chconf0()
191 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); in mcspi_write_chconf0()
192 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); in mcspi_write_chconf0()
205 static void omap2_mcspi_set_dma_req(const struct spi_device *spi, in omap2_mcspi_set_dma_req() argument
210 l = mcspi_cached_chconf0(spi); in omap2_mcspi_set_dma_req()
222 mcspi_write_chconf0(spi, l); in omap2_mcspi_set_dma_req()
225 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) in omap2_mcspi_set_enable() argument
227 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_enable() local
230 l = cs->chctrl0; in omap2_mcspi_set_enable()
235 cs->chctrl0 = l; in omap2_mcspi_set_enable()
236 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_set_enable()
237 /* Flash post-writes */ in omap2_mcspi_set_enable()
238 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); in omap2_mcspi_set_enable()
241 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) in omap2_mcspi_set_cs() argument
243 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_set_cs()
250 if (spi->mode & SPI_CS_HIGH) in omap2_mcspi_set_cs()
253 if (spi->controller_state) { in omap2_mcspi_set_cs()
254 int err = pm_runtime_resume_and_get(mcspi->dev); in omap2_mcspi_set_cs()
256 dev_err(mcspi->dev, "failed to get sync: %d\n", err); in omap2_mcspi_set_cs()
260 l = mcspi_cached_chconf0(spi); in omap2_mcspi_set_cs()
263 if (mcspi->use_multi_mode) { in omap2_mcspi_set_cs()
272 mcspi_write_chconf0(spi, l); in omap2_mcspi_set_cs()
274 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_set_cs()
275 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_set_cs()
282 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_set_mode()
296 if (mcspi->use_multi_mode) in omap2_mcspi_set_mode()
303 ctx->modulctrl = l; in omap2_mcspi_set_mode()
306 static void omap2_mcspi_set_fifo(const struct spi_device *spi, in omap2_mcspi_set_fifo() argument
309 struct spi_controller *ctlr = spi->controller; in omap2_mcspi_set_fifo()
310 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_fifo() local
318 chconf = mcspi_cached_chconf0(spi); in omap2_mcspi_set_fifo()
320 bytes_per_word = mcspi_bytes_per_word(cs->word_len); in omap2_mcspi_set_fifo()
321 if (t->len % bytes_per_word != 0) in omap2_mcspi_set_fifo()
324 if (t->rx_buf != NULL && t->tx_buf != NULL) in omap2_mcspi_set_fifo()
329 wcnt = t->len / bytes_per_word; in omap2_mcspi_set_fifo()
334 if (t->rx_buf != NULL) { in omap2_mcspi_set_fifo()
336 xferlevel |= (bytes_per_word - 1) << 8; in omap2_mcspi_set_fifo()
339 if (t->tx_buf != NULL) { in omap2_mcspi_set_fifo()
341 xferlevel |= bytes_per_word - 1; in omap2_mcspi_set_fifo()
345 mcspi_write_chconf0(spi, chconf); in omap2_mcspi_set_fifo()
346 mcspi->fifo_depth = max_fifo_depth; in omap2_mcspi_set_fifo()
352 if (t->rx_buf != NULL) in omap2_mcspi_set_fifo()
355 if (t->tx_buf != NULL) in omap2_mcspi_set_fifo()
358 mcspi_write_chconf0(spi, chconf); in omap2_mcspi_set_fifo()
359 mcspi->fifo_depth = 0; in omap2_mcspi_set_fifo()
370 return -ETIMEDOUT; in mcspi_wait_for_reg_bit()
382 if (spi_controller_is_target(mcspi->ctlr)) { in mcspi_wait_for_completion()
384 mcspi->target_aborted) in mcspi_wait_for_completion()
385 return -EINTR; in mcspi_wait_for_completion()
395 struct spi_device *spi = data; in omap2_mcspi_rx_callback() local
396 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_rx_callback()
397 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_rx_callback()
400 omap2_mcspi_set_dma_req(spi, 1, 0); in omap2_mcspi_rx_callback()
402 complete(&mcspi_dma->dma_rx_completion); in omap2_mcspi_rx_callback()
407 struct spi_device *spi = data; in omap2_mcspi_tx_callback() local
408 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_tx_callback()
409 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_tx_callback()
412 omap2_mcspi_set_dma_req(spi, 0, 0); in omap2_mcspi_tx_callback()
414 complete(&mcspi_dma->dma_tx_completion); in omap2_mcspi_tx_callback()
417 static void omap2_mcspi_tx_dma(struct spi_device *spi, in omap2_mcspi_tx_dma() argument
425 mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_tx_dma()
426 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_tx_dma()
428 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); in omap2_mcspi_tx_dma()
430 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl, in omap2_mcspi_tx_dma()
431 xfer->tx_sg.nents, in omap2_mcspi_tx_dma()
435 tx->callback = omap2_mcspi_tx_callback; in omap2_mcspi_tx_dma()
436 tx->callback_param = spi; in omap2_mcspi_tx_dma()
441 dma_async_issue_pending(mcspi_dma->dma_tx); in omap2_mcspi_tx_dma()
442 omap2_mcspi_set_dma_req(spi, 0, 1); in omap2_mcspi_tx_dma()
446 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, in omap2_mcspi_rx_dma() argument
459 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_rx_dma() local
460 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_rx_dma()
463 mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_rx_dma()
464 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_rx_dma()
465 count = xfer->len; in omap2_mcspi_rx_dma()
468 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM in omap2_mcspi_rx_dma()
472 if (mcspi->fifo_depth == 0) in omap2_mcspi_rx_dma()
475 word_len = cs->word_len; in omap2_mcspi_rx_dma()
476 l = mcspi_cached_chconf0(spi); in omap2_mcspi_rx_dma()
486 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); in omap2_mcspi_rx_dma()
492 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) in omap2_mcspi_rx_dma()
497 sizes[0] = count - transfer_reduction; in omap2_mcspi_rx_dma()
509 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes, in omap2_mcspi_rx_dma()
513 dev_err(&spi->dev, "sg_split failed\n"); in omap2_mcspi_rx_dma()
517 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0], in omap2_mcspi_rx_dma()
521 tx->callback = omap2_mcspi_rx_callback; in omap2_mcspi_rx_dma()
522 tx->callback_param = spi; in omap2_mcspi_rx_dma()
528 dma_async_issue_pending(mcspi_dma->dma_rx); in omap2_mcspi_rx_dma()
529 omap2_mcspi_set_dma_req(spi, 1, 1); in omap2_mcspi_rx_dma()
531 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion); in omap2_mcspi_rx_dma()
532 if (ret || mcspi->target_aborted) { in omap2_mcspi_rx_dma()
533 dmaengine_terminate_sync(mcspi_dma->dma_rx); in omap2_mcspi_rx_dma()
534 omap2_mcspi_set_dma_req(spi, 1, 0); in omap2_mcspi_rx_dma()
541 if (mcspi->fifo_depth > 0) in omap2_mcspi_rx_dma()
548 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_rx_dma()
550 elements = element_count - 1; in omap2_mcspi_rx_dma()
553 elements--; in omap2_mcspi_rx_dma()
559 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); in omap2_mcspi_rx_dma()
561 ((u8 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
563 ((u16 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
565 ((u32 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
568 dev_err(&spi->dev, "DMA RX penultimate word empty\n"); in omap2_mcspi_rx_dma()
569 count -= (bytes_per_word << 1); in omap2_mcspi_rx_dma()
570 omap2_mcspi_set_enable(spi, 1); in omap2_mcspi_rx_dma()
577 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); in omap2_mcspi_rx_dma()
579 ((u8 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
581 ((u16 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
583 ((u32 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
585 dev_err(&spi->dev, "DMA RX last word empty\n"); in omap2_mcspi_rx_dma()
586 count -= mcspi_bytes_per_word(word_len); in omap2_mcspi_rx_dma()
588 omap2_mcspi_set_enable(spi, 1); in omap2_mcspi_rx_dma()
593 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) in omap2_mcspi_txrx_dma() argument
596 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_dma() local
608 mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_txrx_dma()
609 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_txrx_dma()
611 if (cs->word_len <= 8) { in omap2_mcspi_txrx_dma()
614 } else if (cs->word_len <= 16) { in omap2_mcspi_txrx_dma()
622 count = xfer->len; in omap2_mcspi_txrx_dma()
625 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; in omap2_mcspi_txrx_dma()
626 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; in omap2_mcspi_txrx_dma()
632 rx = xfer->rx_buf; in omap2_mcspi_txrx_dma()
633 tx = xfer->tx_buf; in omap2_mcspi_txrx_dma()
635 mcspi->target_aborted = false; in omap2_mcspi_txrx_dma()
636 reinit_completion(&mcspi_dma->dma_tx_completion); in omap2_mcspi_txrx_dma()
637 reinit_completion(&mcspi_dma->dma_rx_completion); in omap2_mcspi_txrx_dma()
638 reinit_completion(&mcspi->txdone); in omap2_mcspi_txrx_dma()
641 if (spi_controller_is_target(spi->controller)) in omap2_mcspi_txrx_dma()
642 mcspi_write_reg(spi->controller, in omap2_mcspi_txrx_dma()
645 omap2_mcspi_tx_dma(spi, xfer, cfg); in omap2_mcspi_txrx_dma()
649 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); in omap2_mcspi_txrx_dma()
654 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion); in omap2_mcspi_txrx_dma()
655 if (ret || mcspi->target_aborted) { in omap2_mcspi_txrx_dma()
656 dmaengine_terminate_sync(mcspi_dma->dma_tx); in omap2_mcspi_txrx_dma()
657 omap2_mcspi_set_dma_req(spi, 0, 0); in omap2_mcspi_txrx_dma()
661 if (spi_controller_is_target(mcspi->ctlr)) { in omap2_mcspi_txrx_dma()
662 ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone); in omap2_mcspi_txrx_dma()
663 if (ret || mcspi->target_aborted) in omap2_mcspi_txrx_dma()
667 if (mcspi->fifo_depth > 0) { in omap2_mcspi_txrx_dma()
668 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; in omap2_mcspi_txrx_dma()
672 dev_err(&spi->dev, "EOW timed out\n"); in omap2_mcspi_txrx_dma()
674 mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS, in omap2_mcspi_txrx_dma()
680 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_txrx_dma()
681 if (mcspi->fifo_depth > 0) { in omap2_mcspi_txrx_dma()
685 dev_err(&spi->dev, "TXFFE timed out\n"); in omap2_mcspi_txrx_dma()
690 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_dma()
695 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_dma()
702 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) in omap2_mcspi_txrx_pio() argument
704 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_pio() local
707 void __iomem *base = cs->base; in omap2_mcspi_txrx_pio()
713 count = xfer->len; in omap2_mcspi_txrx_pio()
715 word_len = cs->word_len; in omap2_mcspi_txrx_pio()
717 l = mcspi_cached_chconf0(spi); in omap2_mcspi_txrx_pio()
719 /* We store the pre-calculated register addresses on stack to speed in omap2_mcspi_txrx_pio()
732 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
733 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
736 c -= 1; in omap2_mcspi_txrx_pio()
740 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
743 dev_vdbg(&spi->dev, "write-%d %02x\n", in omap2_mcspi_txrx_pio()
750 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
756 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
758 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
759 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
762 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
768 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
772 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
773 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
775 /* Add word delay between each word */ in omap2_mcspi_txrx_pio()
776 spi_delay_exec(&xfer->word_delay, xfer); in omap2_mcspi_txrx_pio()
782 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
783 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
785 c -= 2; in omap2_mcspi_txrx_pio()
789 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
792 dev_vdbg(&spi->dev, "write-%d %04x\n", in omap2_mcspi_txrx_pio()
799 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
805 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
807 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
808 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
811 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
817 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
821 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
822 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
824 /* Add word delay between each word */ in omap2_mcspi_txrx_pio()
825 spi_delay_exec(&xfer->word_delay, xfer); in omap2_mcspi_txrx_pio()
831 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
832 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
834 c -= 4; in omap2_mcspi_txrx_pio()
838 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
841 dev_vdbg(&spi->dev, "write-%d %08x\n", in omap2_mcspi_txrx_pio()
848 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
854 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
856 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
857 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
860 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
866 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
870 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
871 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
873 /* Add word delay between each word */ in omap2_mcspi_txrx_pio()
874 spi_delay_exec(&xfer->word_delay, xfer); in omap2_mcspi_txrx_pio()
879 if (xfer->rx_buf == NULL) { in omap2_mcspi_txrx_pio()
882 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
885 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_pio()
891 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
894 omap2_mcspi_set_enable(spi, 1); in omap2_mcspi_txrx_pio()
895 return count - c; in omap2_mcspi_txrx_pio()
910 static int omap2_mcspi_setup_transfer(struct spi_device *spi, in omap2_mcspi_setup_transfer() argument
913 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup_transfer() local
916 u8 word_len = spi->bits_per_word; in omap2_mcspi_setup_transfer()
917 u32 speed_hz = spi->max_speed_hz; in omap2_mcspi_setup_transfer()
919 mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_setup_transfer()
921 if (t != NULL && t->bits_per_word) in omap2_mcspi_setup_transfer()
922 word_len = t->bits_per_word; in omap2_mcspi_setup_transfer()
924 cs->word_len = word_len; in omap2_mcspi_setup_transfer()
926 if (t && t->speed_hz) in omap2_mcspi_setup_transfer()
927 speed_hz = t->speed_hz; in omap2_mcspi_setup_transfer()
929 ref_clk_hz = mcspi->ref_clk_hz; in omap2_mcspi_setup_transfer()
936 div = (ref_clk_hz + speed_hz - 1) / speed_hz; in omap2_mcspi_setup_transfer()
938 clkd = (div - 1) & 0xf; in omap2_mcspi_setup_transfer()
939 extclk = (div - 1) >> 4; in omap2_mcspi_setup_transfer()
943 l = mcspi_cached_chconf0(spi); in omap2_mcspi_setup_transfer()
945 /* standard 4-wire host mode: SCK, MOSI/out, MISO/in, nCS in omap2_mcspi_setup_transfer()
948 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { in omap2_mcspi_setup_transfer()
960 l |= (word_len - 1) << 7; in omap2_mcspi_setup_transfer()
963 if (!(spi->mode & SPI_CS_HIGH)) in omap2_mcspi_setup_transfer()
964 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ in omap2_mcspi_setup_transfer()
976 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; in omap2_mcspi_setup_transfer()
977 cs->chctrl0 |= extclk << 8; in omap2_mcspi_setup_transfer()
978 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_setup_transfer()
981 /* set SPI mode 0..3 */ in omap2_mcspi_setup_transfer()
982 if (spi->mode & SPI_CPOL) in omap2_mcspi_setup_transfer()
986 if (spi->mode & SPI_CPHA) in omap2_mcspi_setup_transfer()
991 mcspi_write_chconf0(spi, l); in omap2_mcspi_setup_transfer()
993 cs->mode = spi->mode; in omap2_mcspi_setup_transfer()
995 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", in omap2_mcspi_setup_transfer()
997 (spi->mode & SPI_CPHA) ? "trailing" : "leading", in omap2_mcspi_setup_transfer()
998 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); in omap2_mcspi_setup_transfer()
1012 mcspi_dma->dma_rx = dma_request_chan(mcspi->dev, in omap2_mcspi_request_dma()
1013 mcspi_dma->dma_rx_ch_name); in omap2_mcspi_request_dma()
1014 if (IS_ERR(mcspi_dma->dma_rx)) { in omap2_mcspi_request_dma()
1015 ret = PTR_ERR(mcspi_dma->dma_rx); in omap2_mcspi_request_dma()
1016 mcspi_dma->dma_rx = NULL; in omap2_mcspi_request_dma()
1020 mcspi_dma->dma_tx = dma_request_chan(mcspi->dev, in omap2_mcspi_request_dma()
1021 mcspi_dma->dma_tx_ch_name); in omap2_mcspi_request_dma()
1022 if (IS_ERR(mcspi_dma->dma_tx)) { in omap2_mcspi_request_dma()
1023 ret = PTR_ERR(mcspi_dma->dma_tx); in omap2_mcspi_request_dma()
1024 mcspi_dma->dma_tx = NULL; in omap2_mcspi_request_dma()
1025 dma_release_channel(mcspi_dma->dma_rx); in omap2_mcspi_request_dma()
1026 mcspi_dma->dma_rx = NULL; in omap2_mcspi_request_dma()
1029 init_completion(&mcspi_dma->dma_rx_completion); in omap2_mcspi_request_dma()
1030 init_completion(&mcspi_dma->dma_tx_completion); in omap2_mcspi_request_dma()
1042 for (i = 0; i < ctlr->num_chipselect; i++) { in omap2_mcspi_release_dma()
1043 mcspi_dma = &mcspi->dma_channels[i]; in omap2_mcspi_release_dma()
1045 if (mcspi_dma->dma_rx) { in omap2_mcspi_release_dma()
1046 dma_release_channel(mcspi_dma->dma_rx); in omap2_mcspi_release_dma()
1047 mcspi_dma->dma_rx = NULL; in omap2_mcspi_release_dma()
1049 if (mcspi_dma->dma_tx) { in omap2_mcspi_release_dma()
1050 dma_release_channel(mcspi_dma->dma_tx); in omap2_mcspi_release_dma()
1051 mcspi_dma->dma_tx = NULL; in omap2_mcspi_release_dma()
1056 static void omap2_mcspi_cleanup(struct spi_device *spi) in omap2_mcspi_cleanup() argument
1058 struct omap2_mcspi_cs *cs; in omap2_mcspi_cleanup() local
1060 if (spi->controller_state) { in omap2_mcspi_cleanup()
1062 cs = spi->controller_state; in omap2_mcspi_cleanup()
1063 list_del(&cs->node); in omap2_mcspi_cleanup()
1065 kfree(cs); in omap2_mcspi_cleanup()
1069 static int omap2_mcspi_setup(struct spi_device *spi) in omap2_mcspi_setup() argument
1073 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_setup()
1074 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_setup()
1075 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup() local
1077 if (!cs) { in omap2_mcspi_setup()
1078 cs = kzalloc(sizeof(*cs), GFP_KERNEL); in omap2_mcspi_setup()
1079 if (!cs) in omap2_mcspi_setup()
1080 return -ENOMEM; in omap2_mcspi_setup()
1081 cs->base = mcspi->base + spi_get_chipselect(spi, 0) * 0x14; in omap2_mcspi_setup()
1082 cs->phys = mcspi->phys + spi_get_chipselect(spi, 0) * 0x14; in omap2_mcspi_setup()
1083 cs->mode = 0; in omap2_mcspi_setup()
1084 cs->chconf0 = 0; in omap2_mcspi_setup()
1085 cs->chctrl0 = 0; in omap2_mcspi_setup()
1086 spi->controller_state = cs; in omap2_mcspi_setup()
1088 list_add_tail(&cs->node, &ctx->cs); in omap2_mcspi_setup()
1092 ret = pm_runtime_resume_and_get(mcspi->dev); in omap2_mcspi_setup()
1095 omap2_mcspi_cleanup(spi); in omap2_mcspi_setup()
1100 ret = omap2_mcspi_setup_transfer(spi, NULL); in omap2_mcspi_setup()
1102 omap2_mcspi_cleanup(spi); in omap2_mcspi_setup()
1104 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_setup()
1105 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_setup()
1115 irqstat = mcspi_read_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS); in omap2_mcspi_irq_handler()
1120 mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQENABLE, 0); in omap2_mcspi_irq_handler()
1122 complete(&mcspi->txdone); in omap2_mcspi_irq_handler()
1130 struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels; in omap2_mcspi_target_abort()
1132 mcspi->target_aborted = true; in omap2_mcspi_target_abort()
1133 complete(&mcspi_dma->dma_rx_completion); in omap2_mcspi_target_abort()
1134 complete(&mcspi_dma->dma_tx_completion); in omap2_mcspi_target_abort()
1135 complete(&mcspi->txdone); in omap2_mcspi_target_abort()
1141 struct spi_device *spi, in omap2_mcspi_transfer_one() argument
1145 /* We only enable one channel at a time -- the one whose message is in omap2_mcspi_transfer_one()
1146 * -- although this controller would gladly in omap2_mcspi_transfer_one()
1149 * chipselect with the FORCE bit ... CS != channel enable. in omap2_mcspi_transfer_one()
1154 struct omap2_mcspi_cs *cs; in omap2_mcspi_transfer_one() local
1161 mcspi_dma = mcspi->dma_channels + spi_get_chipselect(spi, 0); in omap2_mcspi_transfer_one()
1162 cs = spi->controller_state; in omap2_mcspi_transfer_one()
1163 cd = spi->controller_data; in omap2_mcspi_transfer_one()
1166 * The target driver could have changed spi->mode in which case in omap2_mcspi_transfer_one()
1167 * it will be different from cs->mode (the current hardware setup). in omap2_mcspi_transfer_one()
1172 if (spi->mode != cs->mode) in omap2_mcspi_transfer_one()
1175 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_transfer_one()
1177 if (spi_get_csgpiod(spi, 0)) in omap2_mcspi_transfer_one()
1178 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); in omap2_mcspi_transfer_one()
1181 (t->speed_hz != spi->max_speed_hz) || in omap2_mcspi_transfer_one()
1182 (t->bits_per_word != spi->bits_per_word)) { in omap2_mcspi_transfer_one()
1184 status = omap2_mcspi_setup_transfer(spi, t); in omap2_mcspi_transfer_one()
1187 if (t->speed_hz == spi->max_speed_hz && in omap2_mcspi_transfer_one()
1188 t->bits_per_word == spi->bits_per_word) in omap2_mcspi_transfer_one()
1192 chconf = mcspi_cached_chconf0(spi); in omap2_mcspi_transfer_one()
1196 if (t->tx_buf == NULL) in omap2_mcspi_transfer_one()
1198 else if (t->rx_buf == NULL) in omap2_mcspi_transfer_one()
1201 if (cd && cd->turbo_mode && t->tx_buf == NULL) { in omap2_mcspi_transfer_one()
1203 if (t->len > ((cs->word_len + 7) >> 3)) in omap2_mcspi_transfer_one()
1207 mcspi_write_chconf0(spi, chconf); in omap2_mcspi_transfer_one()
1209 if (t->len) { in omap2_mcspi_transfer_one()
1212 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && in omap2_mcspi_transfer_one()
1213 spi_xfer_is_dma_mapped(ctlr, spi, t)) in omap2_mcspi_transfer_one()
1214 omap2_mcspi_set_fifo(spi, t, 1); in omap2_mcspi_transfer_one()
1216 omap2_mcspi_set_enable(spi, 1); in omap2_mcspi_transfer_one()
1219 if (t->tx_buf == NULL) in omap2_mcspi_transfer_one()
1220 writel_relaxed(0, cs->base in omap2_mcspi_transfer_one()
1223 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && in omap2_mcspi_transfer_one()
1224 spi_xfer_is_dma_mapped(ctlr, spi, t)) in omap2_mcspi_transfer_one()
1225 count = omap2_mcspi_txrx_dma(spi, t); in omap2_mcspi_transfer_one()
1227 count = omap2_mcspi_txrx_pio(spi, t); in omap2_mcspi_transfer_one()
1229 if (count != t->len) { in omap2_mcspi_transfer_one()
1230 status = -EIO; in omap2_mcspi_transfer_one()
1235 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_transfer_one()
1237 if (mcspi->fifo_depth > 0) in omap2_mcspi_transfer_one()
1238 omap2_mcspi_set_fifo(spi, t, 0); in omap2_mcspi_transfer_one()
1244 status = omap2_mcspi_setup_transfer(spi, NULL); in omap2_mcspi_transfer_one()
1247 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_transfer_one()
1249 if (spi_get_csgpiod(spi, 0)) in omap2_mcspi_transfer_one()
1250 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); in omap2_mcspi_transfer_one()
1252 if (mcspi->fifo_depth > 0 && t) in omap2_mcspi_transfer_one()
1253 omap2_mcspi_set_fifo(spi, t, 0); in omap2_mcspi_transfer_one()
1262 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_prepare_message()
1263 struct omap2_mcspi_cs *cs; in omap2_mcspi_prepare_message() local
1269 * multi-mode is applicable. in omap2_mcspi_prepare_message()
1271 mcspi->use_multi_mode = true; in omap2_mcspi_prepare_message()
1272 list_for_each_entry(tr, &msg->transfers, transfer_list) { in omap2_mcspi_prepare_message()
1273 if (!tr->bits_per_word) in omap2_mcspi_prepare_message()
1274 bits_per_word = msg->spi->bits_per_word; in omap2_mcspi_prepare_message()
1276 bits_per_word = tr->bits_per_word; in omap2_mcspi_prepare_message()
1281 if (bits_per_word < 8 && tr->len == 1) { in omap2_mcspi_prepare_message()
1282 /* multi-mode is applicable, only one word (1..7 bits) */ in omap2_mcspi_prepare_message()
1283 } else if (bits_per_word >= 8 && tr->len == bits_per_word / 8) { in omap2_mcspi_prepare_message()
1284 /* multi-mode is applicable, only one word (8..32 bits) */ in omap2_mcspi_prepare_message()
1286 /* multi-mode is not applicable: more than one word in the transfer */ in omap2_mcspi_prepare_message()
1287 mcspi->use_multi_mode = false; in omap2_mcspi_prepare_message()
1290 /* Check if transfer asks to change the CS status after the transfer */ in omap2_mcspi_prepare_message()
1291 if (!tr->cs_change) in omap2_mcspi_prepare_message()
1292 mcspi->use_multi_mode = false; in omap2_mcspi_prepare_message()
1300 if (!mcspi->use_multi_mode) in omap2_mcspi_prepare_message()
1313 list_for_each_entry(cs, &ctx->cs, node) { in omap2_mcspi_prepare_message()
1314 if (msg->spi->controller_state == cs && !mcspi->use_multi_mode) { in omap2_mcspi_prepare_message()
1318 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { in omap2_mcspi_prepare_message()
1319 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; in omap2_mcspi_prepare_message()
1320 writel_relaxed(cs->chconf0, in omap2_mcspi_prepare_message()
1321 cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_prepare_message()
1322 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_prepare_message()
1330 struct spi_device *spi, in omap2_mcspi_can_dma() argument
1333 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_can_dma()
1335 &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_can_dma()
1337 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) in omap2_mcspi_can_dma()
1343 ctlr->dma_rx = mcspi_dma->dma_rx; in omap2_mcspi_can_dma()
1344 ctlr->dma_tx = mcspi_dma->dma_tx; in omap2_mcspi_can_dma()
1346 return (xfer->len >= DMA_MIN_BYTES); in omap2_mcspi_can_dma()
1349 static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi) in omap2_mcspi_max_xfer_size() argument
1351 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_max_xfer_size()
1353 &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_max_xfer_size()
1355 if (mcspi->max_xfer_len && mcspi_dma->dma_rx) in omap2_mcspi_max_xfer_size()
1356 return mcspi->max_xfer_len; in omap2_mcspi_max_xfer_size()
1363 struct spi_controller *ctlr = mcspi->ctlr; in omap2_mcspi_controller_setup()
1364 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_controller_setup()
1367 ret = pm_runtime_resume_and_get(mcspi->dev); in omap2_mcspi_controller_setup()
1373 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; in omap2_mcspi_controller_setup()
1376 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_controller_setup()
1377 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_controller_setup()
1393 * When SPI wake up from off-mode, CS is in activate state. If it was in
1401 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap_mcspi_runtime_resume()
1402 struct omap2_mcspi_cs *cs; in omap_mcspi_runtime_resume() local
1410 mcspi_write_reg(ctlr, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); in omap_mcspi_runtime_resume()
1411 mcspi_write_reg(ctlr, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); in omap_mcspi_runtime_resume()
1413 list_for_each_entry(cs, &ctx->cs, node) { in omap_mcspi_runtime_resume()
1415 * We need to toggle CS state for OMAP take this in omap_mcspi_runtime_resume()
1418 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { in omap_mcspi_runtime_resume()
1419 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; in omap_mcspi_runtime_resume()
1420 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1421 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1422 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; in omap_mcspi_runtime_resume()
1423 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1424 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1426 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1427 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1444 .max_xfer_len = SZ_4K - 1,
1449 .compatible = "ti,omap2-mcspi",
1453 .compatible = "ti,omap4-mcspi",
1457 .compatible = "ti,am654-mcspi",
1472 struct device_node *node = pdev->dev.of_node; in omap2_mcspi_probe()
1475 if (of_property_read_bool(node, "spi-slave")) in omap2_mcspi_probe()
1476 ctlr = spi_alloc_target(&pdev->dev, sizeof(*mcspi)); in omap2_mcspi_probe()
1478 ctlr = spi_alloc_host(&pdev->dev, sizeof(*mcspi)); in omap2_mcspi_probe()
1480 return -ENOMEM; in omap2_mcspi_probe()
1482 /* the spi->mode bits understood by this driver: */ in omap2_mcspi_probe()
1483 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in omap2_mcspi_probe()
1484 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in omap2_mcspi_probe()
1485 ctlr->setup = omap2_mcspi_setup; in omap2_mcspi_probe()
1486 ctlr->auto_runtime_pm = true; in omap2_mcspi_probe()
1487 ctlr->prepare_message = omap2_mcspi_prepare_message; in omap2_mcspi_probe()
1488 ctlr->can_dma = omap2_mcspi_can_dma; in omap2_mcspi_probe()
1489 ctlr->transfer_one = omap2_mcspi_transfer_one; in omap2_mcspi_probe()
1490 ctlr->set_cs = omap2_mcspi_set_cs; in omap2_mcspi_probe()
1491 ctlr->cleanup = omap2_mcspi_cleanup; in omap2_mcspi_probe()
1492 ctlr->target_abort = omap2_mcspi_target_abort; in omap2_mcspi_probe()
1493 ctlr->dev.of_node = node; in omap2_mcspi_probe()
1494 ctlr->use_gpio_descriptors = true; in omap2_mcspi_probe()
1499 mcspi->ctlr = ctlr; in omap2_mcspi_probe()
1501 match = of_match_device(omap_mcspi_of_match, &pdev->dev); in omap2_mcspi_probe()
1504 pdata = match->data; in omap2_mcspi_probe()
1506 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); in omap2_mcspi_probe()
1507 ctlr->num_chipselect = num_cs; in omap2_mcspi_probe()
1508 if (of_property_read_bool(node, "ti,pindir-d0-out-d1-in")) in omap2_mcspi_probe()
1509 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; in omap2_mcspi_probe()
1511 pdata = dev_get_platdata(&pdev->dev); in omap2_mcspi_probe()
1512 ctlr->num_chipselect = pdata->num_cs; in omap2_mcspi_probe()
1513 mcspi->pin_dir = pdata->pin_dir; in omap2_mcspi_probe()
1515 regs_offset = pdata->regs_offset; in omap2_mcspi_probe()
1516 if (pdata->max_xfer_len) { in omap2_mcspi_probe()
1517 mcspi->max_xfer_len = pdata->max_xfer_len; in omap2_mcspi_probe()
1518 ctlr->max_transfer_size = omap2_mcspi_max_xfer_size; in omap2_mcspi_probe()
1521 mcspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); in omap2_mcspi_probe()
1522 if (IS_ERR(mcspi->base)) { in omap2_mcspi_probe()
1523 status = PTR_ERR(mcspi->base); in omap2_mcspi_probe()
1526 mcspi->phys = r->start + regs_offset; in omap2_mcspi_probe()
1527 mcspi->base += regs_offset; in omap2_mcspi_probe()
1529 mcspi->dev = &pdev->dev; in omap2_mcspi_probe()
1531 INIT_LIST_HEAD(&mcspi->ctx.cs); in omap2_mcspi_probe()
1533 mcspi->dma_channels = devm_kcalloc(&pdev->dev, ctlr->num_chipselect, in omap2_mcspi_probe()
1536 if (mcspi->dma_channels == NULL) { in omap2_mcspi_probe()
1537 status = -ENOMEM; in omap2_mcspi_probe()
1541 for (i = 0; i < ctlr->num_chipselect; i++) { in omap2_mcspi_probe()
1542 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i); in omap2_mcspi_probe()
1543 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i); in omap2_mcspi_probe()
1546 &mcspi->dma_channels[i]); in omap2_mcspi_probe()
1547 if (status == -EPROBE_DEFER) in omap2_mcspi_probe()
1554 init_completion(&mcspi->txdone); in omap2_mcspi_probe()
1555 status = devm_request_irq(&pdev->dev, status, in omap2_mcspi_probe()
1556 omap2_mcspi_irq_handler, 0, pdev->name, in omap2_mcspi_probe()
1559 dev_err(&pdev->dev, "Cannot request IRQ"); in omap2_mcspi_probe()
1563 mcspi->ref_clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); in omap2_mcspi_probe()
1564 if (mcspi->ref_clk) in omap2_mcspi_probe()
1565 mcspi->ref_clk_hz = clk_get_rate(mcspi->ref_clk); in omap2_mcspi_probe()
1567 mcspi->ref_clk_hz = OMAP2_MCSPI_MAX_FREQ; in omap2_mcspi_probe()
1568 ctlr->max_speed_hz = mcspi->ref_clk_hz; in omap2_mcspi_probe()
1569 ctlr->min_speed_hz = mcspi->ref_clk_hz >> 15; in omap2_mcspi_probe()
1571 pm_runtime_use_autosuspend(&pdev->dev); in omap2_mcspi_probe()
1572 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); in omap2_mcspi_probe()
1573 pm_runtime_enable(&pdev->dev); in omap2_mcspi_probe()
1579 status = devm_spi_register_controller(&pdev->dev, ctlr); in omap2_mcspi_probe()
1586 pm_runtime_dont_use_autosuspend(&pdev->dev); in omap2_mcspi_probe()
1587 pm_runtime_put_sync(&pdev->dev); in omap2_mcspi_probe()
1588 pm_runtime_disable(&pdev->dev); in omap2_mcspi_probe()
1602 pm_runtime_dont_use_autosuspend(mcspi->dev); in omap2_mcspi_remove()
1603 pm_runtime_put_sync(mcspi->dev); in omap2_mcspi_remove()
1604 pm_runtime_disable(&pdev->dev); in omap2_mcspi_remove()
1618 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n", in omap2_mcspi_suspend()
1623 dev_warn(mcspi->dev, "%s: controller suspend failed: %i\n", in omap2_mcspi_suspend()
1637 dev_warn(mcspi->dev, "%s: controller resume failed: %i\n", in omap2_mcspi_resume()