Lines Matching +full:am654 +full:- +full:mcspi
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OMAP2 McSPI controller driver
15 #include <linux/dma-mapping.h>
32 #include <linux/platform_data/spi-omap2-mcspi.h>
49 /* per-channel banks, 0x14 bytes each, first is: */
56 /* per-register bitmasks: */
153 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); in mcspi_write_reg() local
155 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
160 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); in mcspi_read_reg() local
162 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
168 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg()
170 writel_relaxed(val, cs->base + idx); in mcspi_write_cs_reg()
175 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_read_cs_reg()
177 return readl_relaxed(cs->base + idx); in mcspi_read_cs_reg()
182 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_cached_chconf0()
184 return cs->chconf0; in mcspi_cached_chconf0()
189 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_chconf0()
191 cs->chconf0 = val; in mcspi_write_chconf0()
228 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_enable()
231 l = cs->chctrl0; in omap2_mcspi_set_enable()
236 cs->chctrl0 = l; in omap2_mcspi_set_enable()
237 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_set_enable()
238 /* Flash post-writes */ in omap2_mcspi_set_enable()
244 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_set_cs() local
251 if (spi->mode & SPI_CS_HIGH) in omap2_mcspi_set_cs()
254 if (spi->controller_state) { in omap2_mcspi_set_cs()
255 int err = pm_runtime_resume_and_get(mcspi->dev); in omap2_mcspi_set_cs()
257 dev_err(mcspi->dev, "failed to get sync: %d\n", err); in omap2_mcspi_set_cs()
264 if (mcspi->use_multi_mode) { in omap2_mcspi_set_cs()
275 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_set_cs()
276 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_set_cs()
282 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); in omap2_mcspi_set_mode() local
283 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_set_mode()
297 if (mcspi->use_multi_mode) in omap2_mcspi_set_mode()
304 ctx->modulctrl = l; in omap2_mcspi_set_mode()
310 struct spi_controller *ctlr = spi->controller; in omap2_mcspi_set_fifo()
311 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_fifo()
312 struct omap2_mcspi *mcspi; in omap2_mcspi_set_fifo() local
317 mcspi = spi_controller_get_devdata(ctlr); in omap2_mcspi_set_fifo()
321 bytes_per_word = mcspi_bytes_per_word(cs->word_len); in omap2_mcspi_set_fifo()
322 if (t->len % bytes_per_word != 0) in omap2_mcspi_set_fifo()
325 if (t->rx_buf != NULL && t->tx_buf != NULL) in omap2_mcspi_set_fifo()
330 wcnt = t->len / bytes_per_word; in omap2_mcspi_set_fifo()
335 if (t->rx_buf != NULL) { in omap2_mcspi_set_fifo()
337 xferlevel |= (bytes_per_word - 1) << 8; in omap2_mcspi_set_fifo()
340 if (t->tx_buf != NULL) { in omap2_mcspi_set_fifo()
342 xferlevel |= bytes_per_word - 1; in omap2_mcspi_set_fifo()
347 mcspi->fifo_depth = max_fifo_depth; in omap2_mcspi_set_fifo()
353 if (t->rx_buf != NULL) in omap2_mcspi_set_fifo()
356 if (t->tx_buf != NULL) in omap2_mcspi_set_fifo()
360 mcspi->fifo_depth = 0; in omap2_mcspi_set_fifo()
371 return -ETIMEDOUT; in mcspi_wait_for_reg_bit()
380 static int mcspi_wait_for_completion(struct omap2_mcspi *mcspi, in mcspi_wait_for_completion() argument
383 if (spi_controller_is_target(mcspi->ctlr)) { in mcspi_wait_for_completion()
385 mcspi->target_aborted) in mcspi_wait_for_completion()
386 return -EINTR; in mcspi_wait_for_completion()
397 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_rx_callback() local
398 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_rx_callback()
403 complete(&mcspi_dma->dma_rx_completion); in omap2_mcspi_rx_callback()
409 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_tx_callback() local
410 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_tx_callback()
415 complete(&mcspi_dma->dma_tx_completion); in omap2_mcspi_tx_callback()
422 struct omap2_mcspi *mcspi; in omap2_mcspi_tx_dma() local
426 mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_tx_dma()
427 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_tx_dma()
429 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); in omap2_mcspi_tx_dma()
431 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl, in omap2_mcspi_tx_dma()
432 xfer->tx_sg.nents, in omap2_mcspi_tx_dma()
436 tx->callback = omap2_mcspi_tx_callback; in omap2_mcspi_tx_dma()
437 tx->callback_param = spi; in omap2_mcspi_tx_dma()
442 dma_async_issue_pending(mcspi_dma->dma_tx); in omap2_mcspi_tx_dma()
451 struct omap2_mcspi *mcspi; in omap2_mcspi_rx_dma() local
460 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_rx_dma()
461 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_rx_dma()
464 mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_rx_dma()
465 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_rx_dma()
466 count = xfer->len; in omap2_mcspi_rx_dma()
469 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM in omap2_mcspi_rx_dma()
473 if (mcspi->fifo_depth == 0) in omap2_mcspi_rx_dma()
476 word_len = cs->word_len; in omap2_mcspi_rx_dma()
487 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); in omap2_mcspi_rx_dma()
490 * Reduce DMA transfer length by one more if McSPI is in omap2_mcspi_rx_dma()
493 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) in omap2_mcspi_rx_dma()
498 sizes[0] = count - transfer_reduction; in omap2_mcspi_rx_dma()
510 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes, in omap2_mcspi_rx_dma()
514 dev_err(&spi->dev, "sg_split failed\n"); in omap2_mcspi_rx_dma()
518 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0], in omap2_mcspi_rx_dma()
522 tx->callback = omap2_mcspi_rx_callback; in omap2_mcspi_rx_dma()
523 tx->callback_param = spi; in omap2_mcspi_rx_dma()
529 dma_async_issue_pending(mcspi_dma->dma_rx); in omap2_mcspi_rx_dma()
532 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion); in omap2_mcspi_rx_dma()
533 if (ret || mcspi->target_aborted) { in omap2_mcspi_rx_dma()
534 dmaengine_terminate_sync(mcspi_dma->dma_rx); in omap2_mcspi_rx_dma()
542 if (mcspi->fifo_depth > 0) in omap2_mcspi_rx_dma()
551 elements = element_count - 1; in omap2_mcspi_rx_dma()
554 elements--; in omap2_mcspi_rx_dma()
562 ((u8 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
564 ((u16 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
566 ((u32 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
569 dev_err(&spi->dev, "DMA RX penultimate word empty\n"); in omap2_mcspi_rx_dma()
570 count -= (bytes_per_word << 1); in omap2_mcspi_rx_dma()
580 ((u8 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
582 ((u16 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
584 ((u32 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
586 dev_err(&spi->dev, "DMA RX last word empty\n"); in omap2_mcspi_rx_dma()
587 count -= mcspi_bytes_per_word(word_len); in omap2_mcspi_rx_dma()
596 struct omap2_mcspi *mcspi; in omap2_mcspi_txrx_dma() local
597 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_dma()
609 mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_txrx_dma()
610 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_txrx_dma()
612 if (cs->word_len <= 8) { in omap2_mcspi_txrx_dma()
615 } else if (cs->word_len <= 16) { in omap2_mcspi_txrx_dma()
623 count = xfer->len; in omap2_mcspi_txrx_dma()
626 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; in omap2_mcspi_txrx_dma()
627 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; in omap2_mcspi_txrx_dma()
633 rx = xfer->rx_buf; in omap2_mcspi_txrx_dma()
634 tx = xfer->tx_buf; in omap2_mcspi_txrx_dma()
636 mcspi->target_aborted = false; in omap2_mcspi_txrx_dma()
637 reinit_completion(&mcspi_dma->dma_tx_completion); in omap2_mcspi_txrx_dma()
638 reinit_completion(&mcspi_dma->dma_rx_completion); in omap2_mcspi_txrx_dma()
639 reinit_completion(&mcspi->txdone); in omap2_mcspi_txrx_dma()
642 if (spi_controller_is_target(spi->controller)) in omap2_mcspi_txrx_dma()
643 mcspi_write_reg(spi->controller, in omap2_mcspi_txrx_dma()
655 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion); in omap2_mcspi_txrx_dma()
656 if (ret || mcspi->target_aborted) { in omap2_mcspi_txrx_dma()
657 dmaengine_terminate_sync(mcspi_dma->dma_tx); in omap2_mcspi_txrx_dma()
662 if (spi_controller_is_target(mcspi->ctlr)) { in omap2_mcspi_txrx_dma()
663 ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone); in omap2_mcspi_txrx_dma()
664 if (ret || mcspi->target_aborted) in omap2_mcspi_txrx_dma()
668 if (mcspi->fifo_depth > 0) { in omap2_mcspi_txrx_dma()
669 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; in omap2_mcspi_txrx_dma()
673 dev_err(&spi->dev, "EOW timed out\n"); in omap2_mcspi_txrx_dma()
675 mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS, in omap2_mcspi_txrx_dma()
681 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_txrx_dma()
682 if (mcspi->fifo_depth > 0) { in omap2_mcspi_txrx_dma()
686 dev_err(&spi->dev, "TXFFE timed out\n"); in omap2_mcspi_txrx_dma()
691 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_dma()
696 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_dma()
705 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_pio()
708 void __iomem *base = cs->base; in omap2_mcspi_txrx_pio()
714 count = xfer->len; in omap2_mcspi_txrx_pio()
716 word_len = cs->word_len; in omap2_mcspi_txrx_pio()
720 /* We store the pre-calculated register addresses on stack to speed in omap2_mcspi_txrx_pio()
733 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
734 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
737 c -= 1; in omap2_mcspi_txrx_pio()
741 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
744 dev_vdbg(&spi->dev, "write-%d %02x\n", in omap2_mcspi_txrx_pio()
751 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
759 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
760 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
763 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
773 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
774 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
777 spi_delay_exec(&xfer->word_delay, xfer); in omap2_mcspi_txrx_pio()
783 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
784 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
786 c -= 2; in omap2_mcspi_txrx_pio()
790 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
793 dev_vdbg(&spi->dev, "write-%d %04x\n", in omap2_mcspi_txrx_pio()
800 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
808 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
809 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
812 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
822 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
823 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
826 spi_delay_exec(&xfer->word_delay, xfer); in omap2_mcspi_txrx_pio()
832 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
833 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
835 c -= 4; in omap2_mcspi_txrx_pio()
839 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
842 dev_vdbg(&spi->dev, "write-%d %08x\n", in omap2_mcspi_txrx_pio()
849 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
857 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
858 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
861 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
871 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
872 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
875 spi_delay_exec(&xfer->word_delay, xfer); in omap2_mcspi_txrx_pio()
880 if (xfer->rx_buf == NULL) { in omap2_mcspi_txrx_pio()
883 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
886 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_pio()
896 return count - c; in omap2_mcspi_txrx_pio()
914 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup_transfer()
915 struct omap2_mcspi *mcspi; in omap2_mcspi_setup_transfer() local
917 u8 word_len = spi->bits_per_word; in omap2_mcspi_setup_transfer()
918 u32 speed_hz = spi->max_speed_hz; in omap2_mcspi_setup_transfer()
920 mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_setup_transfer()
922 if (t != NULL && t->bits_per_word) in omap2_mcspi_setup_transfer()
923 word_len = t->bits_per_word; in omap2_mcspi_setup_transfer()
925 cs->word_len = word_len; in omap2_mcspi_setup_transfer()
927 if (t && t->speed_hz) in omap2_mcspi_setup_transfer()
928 speed_hz = t->speed_hz; in omap2_mcspi_setup_transfer()
930 ref_clk_hz = mcspi->ref_clk_hz; in omap2_mcspi_setup_transfer()
937 div = (ref_clk_hz + speed_hz - 1) / speed_hz; in omap2_mcspi_setup_transfer()
939 clkd = (div - 1) & 0xf; in omap2_mcspi_setup_transfer()
940 extclk = (div - 1) >> 4; in omap2_mcspi_setup_transfer()
946 /* standard 4-wire host mode: SCK, MOSI/out, MISO/in, nCS in omap2_mcspi_setup_transfer()
949 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { in omap2_mcspi_setup_transfer()
961 l |= (word_len - 1) << 7; in omap2_mcspi_setup_transfer()
964 if (!(spi->mode & SPI_CS_HIGH)) in omap2_mcspi_setup_transfer()
965 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ in omap2_mcspi_setup_transfer()
977 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; in omap2_mcspi_setup_transfer()
978 cs->chctrl0 |= extclk << 8; in omap2_mcspi_setup_transfer()
979 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_setup_transfer()
983 if (spi->mode & SPI_CPOL) in omap2_mcspi_setup_transfer()
987 if (spi->mode & SPI_CPHA) in omap2_mcspi_setup_transfer()
994 cs->mode = spi->mode; in omap2_mcspi_setup_transfer()
996 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", in omap2_mcspi_setup_transfer()
998 (spi->mode & SPI_CPHA) ? "trailing" : "leading", in omap2_mcspi_setup_transfer()
999 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); in omap2_mcspi_setup_transfer()
1008 static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi, in omap2_mcspi_request_dma() argument
1013 mcspi_dma->dma_rx = dma_request_chan(mcspi->dev, in omap2_mcspi_request_dma()
1014 mcspi_dma->dma_rx_ch_name); in omap2_mcspi_request_dma()
1015 if (IS_ERR(mcspi_dma->dma_rx)) { in omap2_mcspi_request_dma()
1016 ret = PTR_ERR(mcspi_dma->dma_rx); in omap2_mcspi_request_dma()
1017 mcspi_dma->dma_rx = NULL; in omap2_mcspi_request_dma()
1021 mcspi_dma->dma_tx = dma_request_chan(mcspi->dev, in omap2_mcspi_request_dma()
1022 mcspi_dma->dma_tx_ch_name); in omap2_mcspi_request_dma()
1023 if (IS_ERR(mcspi_dma->dma_tx)) { in omap2_mcspi_request_dma()
1024 ret = PTR_ERR(mcspi_dma->dma_tx); in omap2_mcspi_request_dma()
1025 mcspi_dma->dma_tx = NULL; in omap2_mcspi_request_dma()
1026 dma_release_channel(mcspi_dma->dma_rx); in omap2_mcspi_request_dma()
1027 mcspi_dma->dma_rx = NULL; in omap2_mcspi_request_dma()
1030 init_completion(&mcspi_dma->dma_rx_completion); in omap2_mcspi_request_dma()
1031 init_completion(&mcspi_dma->dma_tx_completion); in omap2_mcspi_request_dma()
1039 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); in omap2_mcspi_release_dma() local
1043 for (i = 0; i < ctlr->num_chipselect; i++) { in omap2_mcspi_release_dma()
1044 mcspi_dma = &mcspi->dma_channels[i]; in omap2_mcspi_release_dma()
1046 if (mcspi_dma->dma_rx) { in omap2_mcspi_release_dma()
1047 dma_release_channel(mcspi_dma->dma_rx); in omap2_mcspi_release_dma()
1048 mcspi_dma->dma_rx = NULL; in omap2_mcspi_release_dma()
1050 if (mcspi_dma->dma_tx) { in omap2_mcspi_release_dma()
1051 dma_release_channel(mcspi_dma->dma_tx); in omap2_mcspi_release_dma()
1052 mcspi_dma->dma_tx = NULL; in omap2_mcspi_release_dma()
1061 if (spi->controller_state) { in omap2_mcspi_cleanup()
1063 cs = spi->controller_state; in omap2_mcspi_cleanup()
1064 list_del(&cs->node); in omap2_mcspi_cleanup()
1074 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_setup() local
1075 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_setup()
1076 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup()
1081 return -ENOMEM; in omap2_mcspi_setup()
1082 cs->base = mcspi->base + spi_get_chipselect(spi, 0) * 0x14; in omap2_mcspi_setup()
1083 cs->phys = mcspi->phys + spi_get_chipselect(spi, 0) * 0x14; in omap2_mcspi_setup()
1084 cs->mode = 0; in omap2_mcspi_setup()
1085 cs->chconf0 = 0; in omap2_mcspi_setup()
1086 cs->chctrl0 = 0; in omap2_mcspi_setup()
1087 spi->controller_state = cs; in omap2_mcspi_setup()
1089 list_add_tail(&cs->node, &ctx->cs); in omap2_mcspi_setup()
1093 ret = pm_runtime_resume_and_get(mcspi->dev); in omap2_mcspi_setup()
1105 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_setup()
1106 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_setup()
1113 struct omap2_mcspi *mcspi = data; in omap2_mcspi_irq_handler() local
1116 irqstat = mcspi_read_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS); in omap2_mcspi_irq_handler()
1121 mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQENABLE, 0); in omap2_mcspi_irq_handler()
1123 complete(&mcspi->txdone); in omap2_mcspi_irq_handler()
1130 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); in omap2_mcspi_target_abort() local
1131 struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels; in omap2_mcspi_target_abort()
1133 mcspi->target_aborted = true; in omap2_mcspi_target_abort()
1134 complete(&mcspi_dma->dma_rx_completion); in omap2_mcspi_target_abort()
1135 complete(&mcspi_dma->dma_tx_completion); in omap2_mcspi_target_abort()
1136 complete(&mcspi->txdone); in omap2_mcspi_target_abort()
1146 /* We only enable one channel at a time -- the one whose message is in omap2_mcspi_transfer_one()
1147 * -- although this controller would gladly in omap2_mcspi_transfer_one()
1153 struct omap2_mcspi *mcspi; in omap2_mcspi_transfer_one() local
1161 mcspi = spi_controller_get_devdata(ctlr); in omap2_mcspi_transfer_one()
1162 mcspi_dma = mcspi->dma_channels + spi_get_chipselect(spi, 0); in omap2_mcspi_transfer_one()
1163 cs = spi->controller_state; in omap2_mcspi_transfer_one()
1164 cd = spi->controller_data; in omap2_mcspi_transfer_one()
1167 * The target driver could have changed spi->mode in which case in omap2_mcspi_transfer_one()
1168 * it will be different from cs->mode (the current hardware setup). in omap2_mcspi_transfer_one()
1173 if (spi->mode != cs->mode) in omap2_mcspi_transfer_one()
1179 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); in omap2_mcspi_transfer_one()
1182 (t->speed_hz != spi->max_speed_hz) || in omap2_mcspi_transfer_one()
1183 (t->bits_per_word != spi->bits_per_word)) { in omap2_mcspi_transfer_one()
1188 if (t->speed_hz == spi->max_speed_hz && in omap2_mcspi_transfer_one()
1189 t->bits_per_word == spi->bits_per_word) in omap2_mcspi_transfer_one()
1197 if (t->tx_buf == NULL) in omap2_mcspi_transfer_one()
1199 else if (t->rx_buf == NULL) in omap2_mcspi_transfer_one()
1202 if (cd && cd->turbo_mode && t->tx_buf == NULL) { in omap2_mcspi_transfer_one()
1204 if (t->len > ((cs->word_len + 7) >> 3)) in omap2_mcspi_transfer_one()
1210 if (t->len) { in omap2_mcspi_transfer_one()
1213 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && in omap2_mcspi_transfer_one()
1220 if (t->tx_buf == NULL) in omap2_mcspi_transfer_one()
1221 writel_relaxed(0, cs->base in omap2_mcspi_transfer_one()
1224 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && in omap2_mcspi_transfer_one()
1230 if (count != t->len) { in omap2_mcspi_transfer_one()
1231 status = -EIO; in omap2_mcspi_transfer_one()
1238 if (mcspi->fifo_depth > 0) in omap2_mcspi_transfer_one()
1251 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); in omap2_mcspi_transfer_one()
1253 if (mcspi->fifo_depth > 0 && t) in omap2_mcspi_transfer_one()
1262 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); in omap2_mcspi_prepare_message() local
1263 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_prepare_message()
1270 * multi-mode is applicable. in omap2_mcspi_prepare_message()
1272 mcspi->use_multi_mode = true; in omap2_mcspi_prepare_message()
1274 if (mcspi->last_msg_kept_cs) in omap2_mcspi_prepare_message()
1275 mcspi->use_multi_mode = false; in omap2_mcspi_prepare_message()
1277 list_for_each_entry(tr, &msg->transfers, transfer_list) { in omap2_mcspi_prepare_message()
1278 if (!tr->bits_per_word) in omap2_mcspi_prepare_message()
1279 bits_per_word = msg->spi->bits_per_word; in omap2_mcspi_prepare_message()
1281 bits_per_word = tr->bits_per_word; in omap2_mcspi_prepare_message()
1286 if (bits_per_word < 8 && tr->len == 1) { in omap2_mcspi_prepare_message()
1287 /* multi-mode is applicable, only one word (1..7 bits) */ in omap2_mcspi_prepare_message()
1288 } else if (bits_per_word >= 8 && tr->len == bits_per_word / 8) { in omap2_mcspi_prepare_message()
1289 /* multi-mode is applicable, only one word (8..32 bits) */ in omap2_mcspi_prepare_message()
1291 /* multi-mode is not applicable: more than one word in the transfer */ in omap2_mcspi_prepare_message()
1292 mcspi->use_multi_mode = false; in omap2_mcspi_prepare_message()
1295 if (list_is_last(&tr->transfer_list, &msg->transfers)) { in omap2_mcspi_prepare_message()
1297 if (tr->cs_change) { in omap2_mcspi_prepare_message()
1298 mcspi->use_multi_mode = false; in omap2_mcspi_prepare_message()
1299 mcspi->last_msg_kept_cs = true; in omap2_mcspi_prepare_message()
1301 mcspi->last_msg_kept_cs = false; in omap2_mcspi_prepare_message()
1305 if (!tr->cs_change) in omap2_mcspi_prepare_message()
1306 mcspi->use_multi_mode = false; in omap2_mcspi_prepare_message()
1319 list_for_each_entry(cs, &ctx->cs, node) { in omap2_mcspi_prepare_message()
1320 if (msg->spi->controller_state == cs && !mcspi->use_multi_mode) { in omap2_mcspi_prepare_message()
1324 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { in omap2_mcspi_prepare_message()
1325 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; in omap2_mcspi_prepare_message()
1326 writel_relaxed(cs->chconf0, in omap2_mcspi_prepare_message()
1327 cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_prepare_message()
1328 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_prepare_message()
1339 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_can_dma() local
1341 &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_can_dma()
1343 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) in omap2_mcspi_can_dma()
1349 ctlr->dma_rx = mcspi_dma->dma_rx; in omap2_mcspi_can_dma()
1350 ctlr->dma_tx = mcspi_dma->dma_tx; in omap2_mcspi_can_dma()
1352 return (xfer->len >= DMA_MIN_BYTES); in omap2_mcspi_can_dma()
1357 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_max_xfer_size() local
1359 &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_max_xfer_size()
1361 if (mcspi->max_xfer_len && mcspi_dma->dma_rx) in omap2_mcspi_max_xfer_size()
1362 return mcspi->max_xfer_len; in omap2_mcspi_max_xfer_size()
1367 static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi) in omap2_mcspi_controller_setup() argument
1369 struct spi_controller *ctlr = mcspi->ctlr; in omap2_mcspi_controller_setup()
1370 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_controller_setup()
1373 ret = pm_runtime_resume_and_get(mcspi->dev); in omap2_mcspi_controller_setup()
1379 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; in omap2_mcspi_controller_setup()
1382 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_controller_setup()
1383 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_controller_setup()
1399 * When SPI wake up from off-mode, CS is in activate state. If it was in
1406 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); in omap_mcspi_runtime_resume() local
1407 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap_mcspi_runtime_resume()
1415 /* McSPI: context restore */ in omap_mcspi_runtime_resume()
1416 mcspi_write_reg(ctlr, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); in omap_mcspi_runtime_resume()
1417 mcspi_write_reg(ctlr, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); in omap_mcspi_runtime_resume()
1419 list_for_each_entry(cs, &ctx->cs, node) { in omap_mcspi_runtime_resume()
1424 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { in omap_mcspi_runtime_resume()
1425 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; in omap_mcspi_runtime_resume()
1426 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1427 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1428 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; in omap_mcspi_runtime_resume()
1429 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1430 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1432 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1433 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1450 .max_xfer_len = SZ_4K - 1,
1455 .compatible = "ti,omap2-mcspi",
1459 .compatible = "ti,omap4-mcspi",
1463 .compatible = "ti,am654-mcspi",
1474 struct omap2_mcspi *mcspi; in omap2_mcspi_probe() local
1478 struct device_node *node = pdev->dev.of_node; in omap2_mcspi_probe()
1481 if (of_property_read_bool(node, "spi-slave")) in omap2_mcspi_probe()
1482 ctlr = spi_alloc_target(&pdev->dev, sizeof(*mcspi)); in omap2_mcspi_probe()
1484 ctlr = spi_alloc_host(&pdev->dev, sizeof(*mcspi)); in omap2_mcspi_probe()
1486 return -ENOMEM; in omap2_mcspi_probe()
1488 /* the spi->mode bits understood by this driver: */ in omap2_mcspi_probe()
1489 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in omap2_mcspi_probe()
1490 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in omap2_mcspi_probe()
1491 ctlr->setup = omap2_mcspi_setup; in omap2_mcspi_probe()
1492 ctlr->auto_runtime_pm = true; in omap2_mcspi_probe()
1493 ctlr->prepare_message = omap2_mcspi_prepare_message; in omap2_mcspi_probe()
1494 ctlr->can_dma = omap2_mcspi_can_dma; in omap2_mcspi_probe()
1495 ctlr->transfer_one = omap2_mcspi_transfer_one; in omap2_mcspi_probe()
1496 ctlr->set_cs = omap2_mcspi_set_cs; in omap2_mcspi_probe()
1497 ctlr->cleanup = omap2_mcspi_cleanup; in omap2_mcspi_probe()
1498 ctlr->target_abort = omap2_mcspi_target_abort; in omap2_mcspi_probe()
1499 ctlr->dev.of_node = node; in omap2_mcspi_probe()
1500 ctlr->use_gpio_descriptors = true; in omap2_mcspi_probe()
1504 mcspi = spi_controller_get_devdata(ctlr); in omap2_mcspi_probe()
1505 mcspi->ctlr = ctlr; in omap2_mcspi_probe()
1507 match = of_match_device(omap_mcspi_of_match, &pdev->dev); in omap2_mcspi_probe()
1510 pdata = match->data; in omap2_mcspi_probe()
1512 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); in omap2_mcspi_probe()
1513 ctlr->num_chipselect = num_cs; in omap2_mcspi_probe()
1514 if (of_property_read_bool(node, "ti,pindir-d0-out-d1-in")) in omap2_mcspi_probe()
1515 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; in omap2_mcspi_probe()
1517 pdata = dev_get_platdata(&pdev->dev); in omap2_mcspi_probe()
1518 ctlr->num_chipselect = pdata->num_cs; in omap2_mcspi_probe()
1519 mcspi->pin_dir = pdata->pin_dir; in omap2_mcspi_probe()
1521 regs_offset = pdata->regs_offset; in omap2_mcspi_probe()
1522 if (pdata->max_xfer_len) { in omap2_mcspi_probe()
1523 mcspi->max_xfer_len = pdata->max_xfer_len; in omap2_mcspi_probe()
1524 ctlr->max_transfer_size = omap2_mcspi_max_xfer_size; in omap2_mcspi_probe()
1527 mcspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); in omap2_mcspi_probe()
1528 if (IS_ERR(mcspi->base)) { in omap2_mcspi_probe()
1529 status = PTR_ERR(mcspi->base); in omap2_mcspi_probe()
1532 mcspi->phys = r->start + regs_offset; in omap2_mcspi_probe()
1533 mcspi->base += regs_offset; in omap2_mcspi_probe()
1535 mcspi->dev = &pdev->dev; in omap2_mcspi_probe()
1537 INIT_LIST_HEAD(&mcspi->ctx.cs); in omap2_mcspi_probe()
1539 mcspi->dma_channels = devm_kcalloc(&pdev->dev, ctlr->num_chipselect, in omap2_mcspi_probe()
1542 if (mcspi->dma_channels == NULL) { in omap2_mcspi_probe()
1543 status = -ENOMEM; in omap2_mcspi_probe()
1547 for (i = 0; i < ctlr->num_chipselect; i++) { in omap2_mcspi_probe()
1548 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i); in omap2_mcspi_probe()
1549 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i); in omap2_mcspi_probe()
1551 status = omap2_mcspi_request_dma(mcspi, in omap2_mcspi_probe()
1552 &mcspi->dma_channels[i]); in omap2_mcspi_probe()
1553 if (status == -EPROBE_DEFER) in omap2_mcspi_probe()
1560 init_completion(&mcspi->txdone); in omap2_mcspi_probe()
1561 status = devm_request_irq(&pdev->dev, status, in omap2_mcspi_probe()
1562 omap2_mcspi_irq_handler, 0, pdev->name, in omap2_mcspi_probe()
1563 mcspi); in omap2_mcspi_probe()
1565 dev_err(&pdev->dev, "Cannot request IRQ"); in omap2_mcspi_probe()
1569 mcspi->ref_clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); in omap2_mcspi_probe()
1570 if (IS_ERR(mcspi->ref_clk)) { in omap2_mcspi_probe()
1571 status = PTR_ERR(mcspi->ref_clk); in omap2_mcspi_probe()
1572 dev_err_probe(&pdev->dev, status, "Failed to get ref_clk"); in omap2_mcspi_probe()
1575 if (mcspi->ref_clk) in omap2_mcspi_probe()
1576 mcspi->ref_clk_hz = clk_get_rate(mcspi->ref_clk); in omap2_mcspi_probe()
1578 mcspi->ref_clk_hz = OMAP2_MCSPI_MAX_FREQ; in omap2_mcspi_probe()
1579 ctlr->max_speed_hz = mcspi->ref_clk_hz; in omap2_mcspi_probe()
1580 ctlr->min_speed_hz = mcspi->ref_clk_hz >> 15; in omap2_mcspi_probe()
1582 pm_runtime_use_autosuspend(&pdev->dev); in omap2_mcspi_probe()
1583 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); in omap2_mcspi_probe()
1584 pm_runtime_enable(&pdev->dev); in omap2_mcspi_probe()
1586 status = omap2_mcspi_controller_setup(mcspi); in omap2_mcspi_probe()
1590 status = devm_spi_register_controller(&pdev->dev, ctlr); in omap2_mcspi_probe()
1597 pm_runtime_dont_use_autosuspend(&pdev->dev); in omap2_mcspi_probe()
1598 pm_runtime_put_sync(&pdev->dev); in omap2_mcspi_probe()
1599 pm_runtime_disable(&pdev->dev); in omap2_mcspi_probe()
1609 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); in omap2_mcspi_remove() local
1613 pm_runtime_dont_use_autosuspend(mcspi->dev); in omap2_mcspi_remove()
1614 pm_runtime_put_sync(mcspi->dev); in omap2_mcspi_remove()
1615 pm_runtime_disable(&pdev->dev); in omap2_mcspi_remove()
1624 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); in omap2_mcspi_suspend() local
1629 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n", in omap2_mcspi_suspend()
1634 dev_warn(mcspi->dev, "%s: controller suspend failed: %i\n", in omap2_mcspi_suspend()
1643 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr); in omap2_mcspi_resume() local
1648 dev_warn(mcspi->dev, "%s: controller resume failed: %i\n", in omap2_mcspi_resume()
1672 MODULE_DESCRIPTION("OMAP2 McSPI controller driver");