Lines Matching +full:strobe +full:- +full:dll +full:- +full:delay +full:- +full:target
1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2019-2020 NXP
14 * FlexSPI controller is driven by the LUT(Look-up Table) registers
15 * LUT registers are a look-up-table for sequences of instructions.
19 * LUTs are being created at run-time based on the commands passed
20 * from the spi-mem framework, thus using single LUT index.
26 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
39 #include <linux/delay.h>
60 #include <linux/spi/spi-mem.h>
305 #define LUT_PAD(x) (fls(x) - 1)
311 * ---------------------------------------------------
313 * ---------------------------------------------------
351 .little_endian = true, /* little-endian */
360 .little_endian = true, /* little-endian */
369 .little_endian = true, /* little-endian */
378 .little_endian = true, /* little-endian */
387 .little_endian = true, /* little-endian */
415 return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY; in needs_ip_only()
419 * R/W functions for big- or little-endian registers:
422 * core is little-endian the FSPI controller can use
423 * big-endian or little-endian.
427 if (f->devtype_data->little_endian) in fspi_writel()
435 if (f->devtype_data->little_endian) in fspi_readl()
447 reg = fspi_readl(f, f->iobase + FSPI_INTR); in nxp_fspi_irq_handler()
448 fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR); in nxp_fspi_irq_handler()
451 complete(&f->c); in nxp_fspi_irq_handler()
466 return -ENOTSUPP; in nxp_fspi_check_buswidth()
472 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); in nxp_fspi_supports_op()
475 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); in nxp_fspi_supports_op()
477 if (op->addr.nbytes) in nxp_fspi_supports_op()
478 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); in nxp_fspi_supports_op()
480 if (op->dummy.nbytes) in nxp_fspi_supports_op()
481 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); in nxp_fspi_supports_op()
483 if (op->data.nbytes) in nxp_fspi_supports_op()
484 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); in nxp_fspi_supports_op()
492 if (op->addr.nbytes > 4) in nxp_fspi_supports_op()
500 if (op->addr.val >= f->memmap_phy_size) in nxp_fspi_supports_op()
504 if (op->dummy.buswidth && in nxp_fspi_supports_op()
505 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) in nxp_fspi_supports_op()
509 if (op->data.dir == SPI_MEM_DATA_IN && in nxp_fspi_supports_op()
510 (op->data.nbytes > f->devtype_data->ahb_buf_size || in nxp_fspi_supports_op()
511 (op->data.nbytes > f->devtype_data->rxfifo - 4 && in nxp_fspi_supports_op()
512 !IS_ALIGNED(op->data.nbytes, 8)))) in nxp_fspi_supports_op()
515 if (op->data.dir == SPI_MEM_DATA_OUT && in nxp_fspi_supports_op()
516 op->data.nbytes > f->devtype_data->txfifo) in nxp_fspi_supports_op()
529 if (!f->devtype_data->little_endian) in fspi_readl_poll_tout()
541 * If the target device content being changed by Write/Erase, need to
550 reg = fspi_readl(f, f->iobase + FSPI_MCR0); in nxp_fspi_invalid()
551 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); in nxp_fspi_invalid()
554 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, in nxp_fspi_invalid()
562 void __iomem *base = f->iobase; in nxp_fspi_prepare_lut()
565 u32 lut_offset = (f->devtype_data->lut_num - 1) * 4 * 4; in nxp_fspi_prepare_lut()
569 if (op->cmd.dtr) { in nxp_fspi_prepare_lut()
570 lutval[0] |= LUT_DEF(0, LUT_CMD_DDR, LUT_PAD(op->cmd.buswidth), in nxp_fspi_prepare_lut()
571 op->cmd.opcode >> 8); in nxp_fspi_prepare_lut()
573 LUT_PAD(op->cmd.buswidth), in nxp_fspi_prepare_lut()
574 op->cmd.opcode & 0xFF); in nxp_fspi_prepare_lut()
577 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), in nxp_fspi_prepare_lut()
578 op->cmd.opcode); in nxp_fspi_prepare_lut()
582 if (op->addr.nbytes) { in nxp_fspi_prepare_lut()
583 lutval[lutidx / 2] |= LUT_DEF(lutidx, op->addr.dtr ? LUT_ADDR_DDR : LUT_ADDR, in nxp_fspi_prepare_lut()
584 LUT_PAD(op->addr.buswidth), in nxp_fspi_prepare_lut()
585 op->addr.nbytes * 8); in nxp_fspi_prepare_lut()
590 if (op->dummy.nbytes) { in nxp_fspi_prepare_lut()
591 lutval[lutidx / 2] |= LUT_DEF(lutidx, op->dummy.dtr ? LUT_DUMMY_DDR : LUT_DUMMY, in nxp_fspi_prepare_lut()
596 LUT_PAD(op->data.buswidth), in nxp_fspi_prepare_lut()
597 op->dummy.nbytes * 8 / in nxp_fspi_prepare_lut()
598 op->dummy.buswidth); in nxp_fspi_prepare_lut()
603 if (op->data.nbytes) { in nxp_fspi_prepare_lut()
605 op->data.dir == SPI_MEM_DATA_IN ? in nxp_fspi_prepare_lut()
606 (op->data.dtr ? LUT_READ_DDR : LUT_NXP_READ) : in nxp_fspi_prepare_lut()
607 (op->data.dtr ? LUT_WRITE_DDR : LUT_NXP_WRITE), in nxp_fspi_prepare_lut()
608 LUT_PAD(op->data.buswidth), in nxp_fspi_prepare_lut()
617 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); in nxp_fspi_prepare_lut()
618 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); in nxp_fspi_prepare_lut()
626 dev_dbg(f->dev, "CMD[%02x] lutval[0:%08x 1:%08x 2:%08x 3:%08x], size: 0x%08x\n", in nxp_fspi_prepare_lut()
627 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); in nxp_fspi_prepare_lut()
630 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); in nxp_fspi_prepare_lut()
631 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); in nxp_fspi_prepare_lut()
638 if (is_acpi_node(dev_fwnode(f->dev))) in nxp_fspi_clk_prep_enable()
641 ret = clk_prepare_enable(f->clk_en); in nxp_fspi_clk_prep_enable()
645 ret = clk_prepare_enable(f->clk); in nxp_fspi_clk_prep_enable()
647 clk_disable_unprepare(f->clk_en); in nxp_fspi_clk_prep_enable()
656 if (is_acpi_node(dev_fwnode(f->dev))) in nxp_fspi_clk_disable_unprep()
659 clk_disable_unprepare(f->clk); in nxp_fspi_clk_disable_unprep()
660 clk_disable_unprepare(f->clk_en); in nxp_fspi_clk_disable_unprep()
668 * mode 0: Dummy Read strobe generated by FlexSPI Controller
670 * mode 1: Dummy Read strobe generated by FlexSPI Controller
673 * mode 3: Flash provided Read strobe and input from DQS pad
683 * For 8D-8D-8D mode, need to use mode 3 (Flash provided Read in nxp_fspi_select_rx_sample_clk_source()
684 * strobe and input from DQS pad), otherwise read operaton may in nxp_fspi_select_rx_sample_clk_source()
688 * spi_nor_suspend will disable 8D-8D-8D mode, also need to in nxp_fspi_select_rx_sample_clk_source()
691 reg = fspi_readl(f, f->iobase + FSPI_MCR0); in nxp_fspi_select_rx_sample_clk_source()
694 f->max_rate = 166000000; in nxp_fspi_select_rx_sample_clk_source()
697 f->max_rate = 66000000; in nxp_fspi_select_rx_sample_clk_source()
699 fspi_writel(f, reg, f->iobase + FSPI_MCR0); in nxp_fspi_select_rx_sample_clk_source()
706 /* Reset the DLL, set the DLLRESET to 1 and then set to 0 */ in nxp_fspi_dll_calibration()
707 fspi_writel(f, FSPI_DLLACR_DLLRESET, f->iobase + FSPI_DLLACR); in nxp_fspi_dll_calibration()
708 fspi_writel(f, FSPI_DLLBCR_DLLRESET, f->iobase + FSPI_DLLBCR); in nxp_fspi_dll_calibration()
709 fspi_writel(f, 0, f->iobase + FSPI_DLLACR); in nxp_fspi_dll_calibration()
710 fspi_writel(f, 0, f->iobase + FSPI_DLLBCR); in nxp_fspi_dll_calibration()
713 * Enable the DLL calibration mode. in nxp_fspi_dll_calibration()
714 * The delay target for slave delay line is: in nxp_fspi_dll_calibration()
720 f->iobase + FSPI_DLLACR); in nxp_fspi_dll_calibration()
722 f->iobase + FSPI_DLLBCR); in nxp_fspi_dll_calibration()
725 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_STS2, FSPI_STS2_AB_LOCK, in nxp_fspi_dll_calibration()
728 dev_warn(f->dev, "DLL lock failed, please fix it!\n"); in nxp_fspi_dll_calibration()
731 * For ERR050272, DLL lock status bit is not accurate, in nxp_fspi_dll_calibration()
738 * Config the DLL register to default value, enable the target clock delay
739 * line delay cell override mode, and use 1 fixed delay cell in DLL delay
744 fspi_writel(f, FSPI_DLLACR_OVRDEN, f->iobase + FSPI_DLLACR); in nxp_fspi_dll_override()
745 fspi_writel(f, FSPI_DLLBCR_OVRDEN, f->iobase + FSPI_DLLBCR); in nxp_fspi_dll_override()
750 * register and start base address of the target device.
753 * -------- <-- FLSHB2CR0
756 * B2 start address --> -------- <-- FLSHB1CR0
759 * B1 start address --> -------- <-- FLSHA2CR0
762 * A2 start address --> -------- <-- FLSHA1CR0
765 * A1 start address --> -------- (Lower address)
769 * FSPI_FLSHXXCR0 defines the size of the target device connected at given CS.
775 * of the connected target device.
777 * target device.
779 * chip-select Flash configuration register.
789 /* flexspi only support one DTR mode: 8D-8D-8D */ in nxp_fspi_select_mem()
790 bool op_is_dtr = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && op->data.dtr; in nxp_fspi_select_mem()
791 unsigned long rate = op->max_freq; in nxp_fspi_select_mem()
797 * 1, if previously selected target device is same as current in nxp_fspi_select_mem()
798 * requested target device. in nxp_fspi_select_mem()
802 * For other case, need to re-config. in nxp_fspi_select_mem()
804 if ((f->selected == spi_get_chipselect(spi, 0)) && in nxp_fspi_select_mem()
805 (!!(f->flags & FSPI_DTR_MODE) == op_is_dtr) && in nxp_fspi_select_mem()
806 (f->pre_op_rate == op->max_freq)) in nxp_fspi_select_mem()
810 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); in nxp_fspi_select_mem()
811 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); in nxp_fspi_select_mem()
812 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); in nxp_fspi_select_mem()
813 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); in nxp_fspi_select_mem()
816 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); in nxp_fspi_select_mem()
818 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + in nxp_fspi_select_mem()
821 dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0)); in nxp_fspi_select_mem()
824 rate = min(f->max_rate, op->max_freq); in nxp_fspi_select_mem()
827 f->flags |= FSPI_DTR_MODE; in nxp_fspi_select_mem()
833 f->flags &= ~FSPI_DTR_MODE; in nxp_fspi_select_mem()
838 ret = clk_set_rate(f->clk, rate); in nxp_fspi_select_mem()
847 * If clock rate > 100MHz, then switch from DLL override mode to in nxp_fspi_select_mem()
848 * DLL calibration mode. in nxp_fspi_select_mem()
855 f->pre_op_rate = op->max_freq; in nxp_fspi_select_mem()
857 f->selected = spi_get_chipselect(spi, 0); in nxp_fspi_select_mem()
862 u32 start = op->addr.val; in nxp_fspi_read_ahb()
863 u32 len = op->data.nbytes; in nxp_fspi_read_ahb()
866 if ((!f->ahb_addr) || start < f->memmap_start || in nxp_fspi_read_ahb()
867 start + len > f->memmap_start + f->memmap_len) { in nxp_fspi_read_ahb()
868 if (f->ahb_addr) in nxp_fspi_read_ahb()
869 iounmap(f->ahb_addr); in nxp_fspi_read_ahb()
871 f->memmap_start = start; in nxp_fspi_read_ahb()
872 f->memmap_len = max_t(u32, len, NXP_FSPI_MIN_IOMAP); in nxp_fspi_read_ahb()
874 f->ahb_addr = ioremap(f->memmap_phy + f->memmap_start, in nxp_fspi_read_ahb()
875 f->memmap_len); in nxp_fspi_read_ahb()
877 if (!f->ahb_addr) { in nxp_fspi_read_ahb()
878 dev_err(f->dev, "failed to alloc memory\n"); in nxp_fspi_read_ahb()
879 return -ENOMEM; in nxp_fspi_read_ahb()
884 memcpy_fromio(op->data.buf.in, in nxp_fspi_read_ahb()
885 f->ahb_addr + start - f->memmap_start, len); in nxp_fspi_read_ahb()
893 void __iomem *base = f->iobase; in nxp_fspi_fill_txfifo()
895 u8 *buf = (u8 *) op->data.buf.out; in nxp_fspi_fill_txfifo()
905 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { in nxp_fspi_fill_txfifo()
907 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, in nxp_fspi_fill_txfifo()
917 if (i < op->data.nbytes) { in nxp_fspi_fill_txfifo()
920 int remaining = op->data.nbytes - i; in nxp_fspi_fill_txfifo()
922 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, in nxp_fspi_fill_txfifo()
928 memcpy(&data, buf + i + j, min_t(int, 4, remaining - j)); in nxp_fspi_fill_txfifo()
938 void __iomem *base = f->iobase; in nxp_fspi_read_rxfifo()
940 int len = op->data.nbytes; in nxp_fspi_read_rxfifo()
941 u8 *buf = (u8 *) op->data.buf.in; in nxp_fspi_read_rxfifo()
949 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, in nxp_fspi_read_rxfifo()
964 buf = op->data.buf.in + i; in nxp_fspi_read_rxfifo()
966 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, in nxp_fspi_read_rxfifo()
971 len = op->data.nbytes - i; in nxp_fspi_read_rxfifo()
972 for (j = 0; j < op->data.nbytes - i; j += 4) { in nxp_fspi_read_rxfifo()
976 len -= size; in nxp_fspi_read_rxfifo()
988 void __iomem *base = f->iobase; in nxp_fspi_do_op()
999 init_completion(&f->c); in nxp_fspi_do_op()
1001 fspi_writel(f, op->addr.val, base + FSPI_IPCR0); in nxp_fspi_do_op()
1007 seqid_lut = f->devtype_data->lut_num - 1; in nxp_fspi_do_op()
1008 fspi_writel(f, op->data.nbytes | in nxp_fspi_do_op()
1017 if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000))) in nxp_fspi_do_op()
1018 err = -ETIMEDOUT; in nxp_fspi_do_op()
1021 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) in nxp_fspi_do_op()
1029 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); in nxp_fspi_exec_op()
1032 guard(mutex)(&f->lock); in nxp_fspi_exec_op()
1034 err = pm_runtime_get_sync(f->dev); in nxp_fspi_exec_op()
1036 dev_err(f->dev, "Failed to enable clock %d\n", __LINE__); in nxp_fspi_exec_op()
1041 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, in nxp_fspi_exec_op()
1045 nxp_fspi_select_mem(f, mem->spi, op); in nxp_fspi_exec_op()
1054 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && in nxp_fspi_exec_op()
1055 op->data.dir == SPI_MEM_DATA_IN && in nxp_fspi_exec_op()
1059 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) in nxp_fspi_exec_op()
1068 pm_runtime_put_autosuspend(f->dev); in nxp_fspi_exec_op()
1075 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); in nxp_fspi_adjust_op_size()
1077 if (op->data.dir == SPI_MEM_DATA_OUT) { in nxp_fspi_adjust_op_size()
1078 if (op->data.nbytes > f->devtype_data->txfifo) in nxp_fspi_adjust_op_size()
1079 op->data.nbytes = f->devtype_data->txfifo; in nxp_fspi_adjust_op_size()
1081 if (op->data.nbytes > f->devtype_data->ahb_buf_size) in nxp_fspi_adjust_op_size()
1082 op->data.nbytes = f->devtype_data->ahb_buf_size; in nxp_fspi_adjust_op_size()
1083 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) in nxp_fspi_adjust_op_size()
1084 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); in nxp_fspi_adjust_op_size()
1088 if (op->data.dir == SPI_MEM_DATA_IN && in nxp_fspi_adjust_op_size()
1090 op->data.nbytes > f->devtype_data->rxfifo) in nxp_fspi_adjust_op_size()
1091 op->data.nbytes = f->devtype_data->rxfifo; in nxp_fspi_adjust_op_size()
1108 dev_dbg(f->dev, "Errata applicable only for LS1028A\n"); in erratum_err050568()
1112 map = syscon_regmap_lookup_by_compatible("fsl,ls1028a-dcfg"); in erratum_err050568()
1114 dev_err(f->dev, "No syscon regmap\n"); in erratum_err050568()
1123 dev_dbg(f->dev, "val: 0x%08x, sys_pll_ratio: %d\n", val, sys_pll_ratio); in erratum_err050568()
1127 f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY; in erratum_err050568()
1132 dev_err(f->dev, "Errata cannot be executed. Read via IP bus may not work\n"); in erratum_err050568()
1137 void __iomem *base = f->iobase; in nxp_fspi_default_setup()
1145 ret = clk_set_rate(f->clk, 20000000); in nxp_fspi_default_setup()
1159 if (of_device_is_compatible(f->dev->of_node, "nxp,lx2160a-fspi")) in nxp_fspi_default_setup()
1164 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, in nxp_fspi_default_setup()
1179 * Disable same device enable bit and configure all target devices in nxp_fspi_default_setup()
1182 reg = fspi_readl(f, f->iobase + FSPI_MCR2); in nxp_fspi_default_setup()
1194 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | in nxp_fspi_default_setup()
1213 seqid_lut = f->devtype_data->lut_num - 1; in nxp_fspi_default_setup()
1214 /* AHB Read - Set lut sequence ID for all CS. */ in nxp_fspi_default_setup()
1220 f->selected = -1; in nxp_fspi_default_setup()
1230 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); in nxp_fspi_get_name()
1231 struct device *dev = &mem->spi->dev; in nxp_fspi_get_name()
1235 if (of_get_available_child_count(f->dev->of_node) == 1) in nxp_fspi_get_name()
1236 return dev_name(f->dev); in nxp_fspi_get_name()
1239 "%s-%d", dev_name(f->dev), in nxp_fspi_get_name()
1240 spi_get_chipselect(mem->spi, 0)); in nxp_fspi_get_name()
1244 return ERR_PTR(-ENOMEM); in nxp_fspi_get_name()
1273 pm_runtime_get_sync(f->dev); in nxp_fspi_cleanup()
1276 fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0); in nxp_fspi_cleanup()
1278 pm_runtime_disable(f->dev); in nxp_fspi_cleanup()
1279 pm_runtime_put_noidle(f->dev); in nxp_fspi_cleanup()
1282 if (f->ahb_addr) in nxp_fspi_cleanup()
1283 iounmap(f->ahb_addr); in nxp_fspi_cleanup()
1289 struct device *dev = &pdev->dev; in nxp_fspi_probe()
1296 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*f)); in nxp_fspi_probe()
1298 return -ENOMEM; in nxp_fspi_probe()
1300 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | in nxp_fspi_probe()
1304 f->dev = dev; in nxp_fspi_probe()
1305 f->devtype_data = (struct nxp_fspi_devtype_data *)device_get_match_data(dev); in nxp_fspi_probe()
1306 if (!f->devtype_data) in nxp_fspi_probe()
1307 return -ENODEV; in nxp_fspi_probe()
1311 /* find the resources - configuration register address space */ in nxp_fspi_probe()
1313 f->iobase = devm_platform_ioremap_resource(pdev, 0); in nxp_fspi_probe()
1315 f->iobase = devm_platform_ioremap_resource_byname(pdev, "fspi_base"); in nxp_fspi_probe()
1316 if (IS_ERR(f->iobase)) in nxp_fspi_probe()
1317 return PTR_ERR(f->iobase); in nxp_fspi_probe()
1319 /* find the resources - controller memory mapped space */ in nxp_fspi_probe()
1326 return -ENODEV; in nxp_fspi_probe()
1329 f->memmap_phy = res->start; in nxp_fspi_probe()
1330 f->memmap_phy_size = resource_size(res); in nxp_fspi_probe()
1334 f->clk_en = devm_clk_get(dev, "fspi_en"); in nxp_fspi_probe()
1335 if (IS_ERR(f->clk_en)) in nxp_fspi_probe()
1336 return PTR_ERR(f->clk_en); in nxp_fspi_probe()
1338 f->clk = devm_clk_get(dev, "fspi"); in nxp_fspi_probe()
1339 if (IS_ERR(f->clk)) in nxp_fspi_probe()
1340 return PTR_ERR(f->clk); in nxp_fspi_probe()
1353 ret = pm_runtime_get_sync(f->dev); in nxp_fspi_probe()
1358 reg = fspi_readl(f, f->iobase + FSPI_INTR); in nxp_fspi_probe()
1360 fspi_writel(f, reg, f->iobase + FSPI_INTR); in nxp_fspi_probe()
1369 nxp_fspi_irq_handler, 0, pdev->name, f); in nxp_fspi_probe()
1373 ret = devm_mutex_init(dev, &f->lock); in nxp_fspi_probe()
1377 ctlr->bus_num = -1; in nxp_fspi_probe()
1378 ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; in nxp_fspi_probe()
1379 ctlr->mem_ops = &nxp_fspi_mem_ops; in nxp_fspi_probe()
1381 if (f->devtype_data->quirks & FSPI_QUIRK_DISABLE_DTR) in nxp_fspi_probe()
1382 ctlr->mem_caps = &nxp_fspi_mem_caps_disable_dtr; in nxp_fspi_probe()
1384 ctlr->mem_caps = &nxp_fspi_mem_caps; in nxp_fspi_probe()
1386 device_set_node(&ctlr->dev, fwnode); in nxp_fspi_probe()
1392 return devm_spi_register_controller(&pdev->dev, ctlr); in nxp_fspi_probe()
1413 if (f->flags & FSPI_NEED_INIT) { in nxp_fspi_runtime_resume()
1418 f->flags &= ~FSPI_NEED_INIT; in nxp_fspi_runtime_resume()
1435 f->flags |= FSPI_NEED_INIT; in nxp_fspi_suspend()
1446 { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, },
1447 { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, },
1448 { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, },
1449 { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, },
1450 { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, },
1451 { .compatible = "nxp,imx8ulp-fspi", .data = (void *)&imx8ulp_data, },
1466 .name = "nxp-fspi",