Lines Matching +full:ls1028a +full:- +full:flexspi +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0+
4 * NXP FlexSPI(FSPI) controller driver.
6 * Copyright 2019-2020 NXP
9 * FlexSPI is a flexsible SPI host controller which supports two SPI
14 * FlexSPI controller is driven by the LUT(Look-up Table) registers
15 * LUT registers are a look-up-table for sequences of instructions.
19 * LUTs are being created at run-time based on the commands passed
20 * from the spi-mem framework, thus using single LUT index.
26 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
37 #include <linux/clk.h>
58 #include <linux/spi/spi-mem.h>
300 #define LUT_PAD(x) (fls(x) - 1)
306 * ---------------------------------------------------
308 * ---------------------------------------------------
344 .little_endian = true, /* little-endian */
353 .little_endian = true, /* little-endian */
362 .little_endian = true, /* little-endian */
371 .little_endian = true, /* little-endian */
380 .little_endian = true, /* little-endian */
390 struct clk *clk, *clk_en; member
401 return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY; in needs_ip_only()
405 * R/W functions for big- or little-endian registers:
408 * core is little-endian the FSPI controller can use
409 * big-endian or little-endian.
413 if (f->devtype_data->little_endian) in fspi_writel()
421 if (f->devtype_data->little_endian) in fspi_readl()
433 reg = fspi_readl(f, f->iobase + FSPI_INTR); in nxp_fspi_irq_handler()
434 fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR); in nxp_fspi_irq_handler()
437 complete(&f->c); in nxp_fspi_irq_handler()
452 return -ENOTSUPP; in nxp_fspi_check_buswidth()
458 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); in nxp_fspi_supports_op()
461 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); in nxp_fspi_supports_op()
463 if (op->addr.nbytes) in nxp_fspi_supports_op()
464 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); in nxp_fspi_supports_op()
466 if (op->dummy.nbytes) in nxp_fspi_supports_op()
467 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); in nxp_fspi_supports_op()
469 if (op->data.nbytes) in nxp_fspi_supports_op()
470 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); in nxp_fspi_supports_op()
478 if (op->addr.nbytes > 4) in nxp_fspi_supports_op()
486 if (op->addr.val >= f->memmap_phy_size) in nxp_fspi_supports_op()
490 if (op->dummy.buswidth && in nxp_fspi_supports_op()
491 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) in nxp_fspi_supports_op()
495 if (op->data.dir == SPI_MEM_DATA_IN && in nxp_fspi_supports_op()
496 (op->data.nbytes > f->devtype_data->ahb_buf_size || in nxp_fspi_supports_op()
497 (op->data.nbytes > f->devtype_data->rxfifo - 4 && in nxp_fspi_supports_op()
498 !IS_ALIGNED(op->data.nbytes, 8)))) in nxp_fspi_supports_op()
501 if (op->data.dir == SPI_MEM_DATA_OUT && in nxp_fspi_supports_op()
502 op->data.nbytes > f->devtype_data->txfifo) in nxp_fspi_supports_op()
515 if (!f->devtype_data->little_endian) in fspi_readl_poll_tout()
536 reg = fspi_readl(f, f->iobase + FSPI_MCR0); in nxp_fspi_invalid()
537 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); in nxp_fspi_invalid()
540 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, in nxp_fspi_invalid()
548 void __iomem *base = f->iobase; in nxp_fspi_prepare_lut()
551 u32 lut_offset = (f->devtype_data->lut_num - 1) * 4 * 4; in nxp_fspi_prepare_lut()
555 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), in nxp_fspi_prepare_lut()
556 op->cmd.opcode); in nxp_fspi_prepare_lut()
559 if (op->addr.nbytes) { in nxp_fspi_prepare_lut()
561 LUT_PAD(op->addr.buswidth), in nxp_fspi_prepare_lut()
562 op->addr.nbytes * 8); in nxp_fspi_prepare_lut()
567 if (op->dummy.nbytes) { in nxp_fspi_prepare_lut()
570 * Due to FlexSPI controller limitation number of PAD for dummy in nxp_fspi_prepare_lut()
573 LUT_PAD(op->data.buswidth), in nxp_fspi_prepare_lut()
574 op->dummy.nbytes * 8 / in nxp_fspi_prepare_lut()
575 op->dummy.buswidth); in nxp_fspi_prepare_lut()
580 if (op->data.nbytes) { in nxp_fspi_prepare_lut()
582 op->data.dir == SPI_MEM_DATA_IN ? in nxp_fspi_prepare_lut()
584 LUT_PAD(op->data.buswidth), in nxp_fspi_prepare_lut()
593 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); in nxp_fspi_prepare_lut()
594 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); in nxp_fspi_prepare_lut()
602 dev_dbg(f->dev, "CMD[%02x] lutval[0:%08x 1:%08x 2:%08x 3:%08x], size: 0x%08x\n", in nxp_fspi_prepare_lut()
603 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); in nxp_fspi_prepare_lut()
606 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); in nxp_fspi_prepare_lut()
607 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); in nxp_fspi_prepare_lut()
614 if (is_acpi_node(dev_fwnode(f->dev))) in nxp_fspi_clk_prep_enable()
617 ret = clk_prepare_enable(f->clk_en); in nxp_fspi_clk_prep_enable()
621 ret = clk_prepare_enable(f->clk); in nxp_fspi_clk_prep_enable()
623 clk_disable_unprepare(f->clk_en); in nxp_fspi_clk_prep_enable()
632 if (is_acpi_node(dev_fwnode(f->dev))) in nxp_fspi_clk_disable_unprep()
635 clk_disable_unprepare(f->clk); in nxp_fspi_clk_disable_unprep()
636 clk_disable_unprepare(f->clk_en); in nxp_fspi_clk_disable_unprep()
646 fspi_writel(f, FSPI_DLLACR_DLLRESET, f->iobase + FSPI_DLLACR); in nxp_fspi_dll_calibration()
647 fspi_writel(f, FSPI_DLLBCR_DLLRESET, f->iobase + FSPI_DLLBCR); in nxp_fspi_dll_calibration()
648 fspi_writel(f, 0, f->iobase + FSPI_DLLACR); in nxp_fspi_dll_calibration()
649 fspi_writel(f, 0, f->iobase + FSPI_DLLBCR); in nxp_fspi_dll_calibration()
659 f->iobase + FSPI_DLLACR); in nxp_fspi_dll_calibration()
661 f->iobase + FSPI_DLLBCR); in nxp_fspi_dll_calibration()
664 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_STS2, FSPI_STS2_AB_LOCK, in nxp_fspi_dll_calibration()
667 dev_warn(f->dev, "DLL lock failed, please fix it!\n"); in nxp_fspi_dll_calibration()
671 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
675 * -------- <-- FLSHB2CR0
678 * B2 start address --> -------- <-- FLSHB1CR0
681 * B1 start address --> -------- <-- FLSHA2CR0
684 * A2 start address --> -------- <-- FLSHA1CR0
687 * A1 start address --> -------- (Lower address)
701 * chip-select Flash configuration register.
710 unsigned long rate = spi->max_speed_hz; in nxp_fspi_select_mem()
718 if (f->selected == spi_get_chipselect(spi, 0)) in nxp_fspi_select_mem()
722 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); in nxp_fspi_select_mem()
723 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); in nxp_fspi_select_mem()
724 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); in nxp_fspi_select_mem()
725 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); in nxp_fspi_select_mem()
728 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); in nxp_fspi_select_mem()
730 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + in nxp_fspi_select_mem()
733 dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0)); in nxp_fspi_select_mem()
737 ret = clk_set_rate(f->clk, rate); in nxp_fspi_select_mem()
752 f->selected = spi_get_chipselect(spi, 0); in nxp_fspi_select_mem()
757 u32 start = op->addr.val; in nxp_fspi_read_ahb()
758 u32 len = op->data.nbytes; in nxp_fspi_read_ahb()
761 if ((!f->ahb_addr) || start < f->memmap_start || in nxp_fspi_read_ahb()
762 start + len > f->memmap_start + f->memmap_len) { in nxp_fspi_read_ahb()
763 if (f->ahb_addr) in nxp_fspi_read_ahb()
764 iounmap(f->ahb_addr); in nxp_fspi_read_ahb()
766 f->memmap_start = start; in nxp_fspi_read_ahb()
767 f->memmap_len = max_t(u32, len, NXP_FSPI_MIN_IOMAP); in nxp_fspi_read_ahb()
769 f->ahb_addr = ioremap(f->memmap_phy + f->memmap_start, in nxp_fspi_read_ahb()
770 f->memmap_len); in nxp_fspi_read_ahb()
772 if (!f->ahb_addr) { in nxp_fspi_read_ahb()
773 dev_err(f->dev, "failed to alloc memory\n"); in nxp_fspi_read_ahb()
774 return -ENOMEM; in nxp_fspi_read_ahb()
779 memcpy_fromio(op->data.buf.in, in nxp_fspi_read_ahb()
780 f->ahb_addr + start - f->memmap_start, len); in nxp_fspi_read_ahb()
788 void __iomem *base = f->iobase; in nxp_fspi_fill_txfifo()
790 u8 *buf = (u8 *) op->data.buf.out; in nxp_fspi_fill_txfifo()
800 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { in nxp_fspi_fill_txfifo()
802 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, in nxp_fspi_fill_txfifo()
812 if (i < op->data.nbytes) { in nxp_fspi_fill_txfifo()
815 int remaining = op->data.nbytes - i; in nxp_fspi_fill_txfifo()
817 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, in nxp_fspi_fill_txfifo()
823 memcpy(&data, buf + i + j, min_t(int, 4, remaining - j)); in nxp_fspi_fill_txfifo()
833 void __iomem *base = f->iobase; in nxp_fspi_read_rxfifo()
835 int len = op->data.nbytes; in nxp_fspi_read_rxfifo()
836 u8 *buf = (u8 *) op->data.buf.in; in nxp_fspi_read_rxfifo()
844 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, in nxp_fspi_read_rxfifo()
859 buf = op->data.buf.in + i; in nxp_fspi_read_rxfifo()
861 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, in nxp_fspi_read_rxfifo()
866 len = op->data.nbytes - i; in nxp_fspi_read_rxfifo()
867 for (j = 0; j < op->data.nbytes - i; j += 4) { in nxp_fspi_read_rxfifo()
871 len -= size; in nxp_fspi_read_rxfifo()
883 void __iomem *base = f->iobase; in nxp_fspi_do_op()
894 init_completion(&f->c); in nxp_fspi_do_op()
896 fspi_writel(f, op->addr.val, base + FSPI_IPCR0); in nxp_fspi_do_op()
902 seqid_lut = f->devtype_data->lut_num - 1; in nxp_fspi_do_op()
903 fspi_writel(f, op->data.nbytes | in nxp_fspi_do_op()
912 if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000))) in nxp_fspi_do_op()
913 err = -ETIMEDOUT; in nxp_fspi_do_op()
916 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) in nxp_fspi_do_op()
924 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); in nxp_fspi_exec_op()
927 mutex_lock(&f->lock); in nxp_fspi_exec_op()
930 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, in nxp_fspi_exec_op()
934 nxp_fspi_select_mem(f, mem->spi); in nxp_fspi_exec_op()
943 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && in nxp_fspi_exec_op()
944 op->data.dir == SPI_MEM_DATA_IN && in nxp_fspi_exec_op()
948 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) in nxp_fspi_exec_op()
957 mutex_unlock(&f->lock); in nxp_fspi_exec_op()
964 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); in nxp_fspi_adjust_op_size()
966 if (op->data.dir == SPI_MEM_DATA_OUT) { in nxp_fspi_adjust_op_size()
967 if (op->data.nbytes > f->devtype_data->txfifo) in nxp_fspi_adjust_op_size()
968 op->data.nbytes = f->devtype_data->txfifo; in nxp_fspi_adjust_op_size()
970 if (op->data.nbytes > f->devtype_data->ahb_buf_size) in nxp_fspi_adjust_op_size()
971 op->data.nbytes = f->devtype_data->ahb_buf_size; in nxp_fspi_adjust_op_size()
972 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) in nxp_fspi_adjust_op_size()
973 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); in nxp_fspi_adjust_op_size()
977 if (op->data.dir == SPI_MEM_DATA_IN && in nxp_fspi_adjust_op_size()
979 op->data.nbytes > f->devtype_data->rxfifo) in nxp_fspi_adjust_op_size()
980 op->data.nbytes = f->devtype_data->rxfifo; in nxp_fspi_adjust_op_size()
988 { .family = "QorIQ LS1028A" }, in erratum_err050568()
995 /* Check for LS1028A family */ in erratum_err050568()
997 dev_dbg(f->dev, "Errata applicable only for LS1028A\n"); in erratum_err050568()
1001 map = syscon_regmap_lookup_by_compatible("fsl,ls1028a-dcfg"); in erratum_err050568()
1003 dev_err(f->dev, "No syscon regmap\n"); in erratum_err050568()
1012 dev_dbg(f->dev, "val: 0x%08x, sys_pll_ratio: %d\n", val, sys_pll_ratio); in erratum_err050568()
1016 f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY; in erratum_err050568()
1021 dev_err(f->dev, "Errata cannot be executed. Read via IP bus may not work\n"); in erratum_err050568()
1026 void __iomem *base = f->iobase; in nxp_fspi_default_setup()
1034 ret = clk_set_rate(f->clk, 20000000); in nxp_fspi_default_setup()
1043 * ERR050568: Flash access by FlexSPI AHB command may not work with in nxp_fspi_default_setup()
1044 * platform frequency equal to 300 MHz on LS1028A. in nxp_fspi_default_setup()
1045 * LS1028A reuses LX2160A compatible entry. Make errata applicable for in nxp_fspi_default_setup()
1046 * Layerscape LS1028A platform. in nxp_fspi_default_setup()
1048 if (of_device_is_compatible(f->dev->of_node, "nxp,lx2160a-fspi")) in nxp_fspi_default_setup()
1053 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, in nxp_fspi_default_setup()
1077 reg = fspi_readl(f, f->iobase + FSPI_MCR2); in nxp_fspi_default_setup()
1089 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | in nxp_fspi_default_setup()
1108 seqid_lut = f->devtype_data->lut_num - 1; in nxp_fspi_default_setup()
1109 /* AHB Read - Set lut sequence ID for all CS. */ in nxp_fspi_default_setup()
1115 f->selected = -1; in nxp_fspi_default_setup()
1125 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); in nxp_fspi_get_name()
1126 struct device *dev = &mem->spi->dev; in nxp_fspi_get_name()
1130 if (of_get_available_child_count(f->dev->of_node) == 1) in nxp_fspi_get_name()
1131 return dev_name(f->dev); in nxp_fspi_get_name()
1134 "%s-%d", dev_name(f->dev), in nxp_fspi_get_name()
1135 spi_get_chipselect(mem->spi, 0)); in nxp_fspi_get_name()
1139 return ERR_PTR(-ENOMEM); in nxp_fspi_get_name()
1155 struct device *dev = &pdev->dev; in nxp_fspi_probe()
1156 struct device_node *np = dev->of_node; in nxp_fspi_probe()
1162 ctlr = spi_alloc_host(&pdev->dev, sizeof(*f)); in nxp_fspi_probe()
1164 return -ENOMEM; in nxp_fspi_probe()
1166 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | in nxp_fspi_probe()
1170 f->dev = dev; in nxp_fspi_probe()
1171 f->devtype_data = (struct nxp_fspi_devtype_data *)device_get_match_data(dev); in nxp_fspi_probe()
1172 if (!f->devtype_data) { in nxp_fspi_probe()
1173 ret = -ENODEV; in nxp_fspi_probe()
1179 /* find the resources - configuration register address space */ in nxp_fspi_probe()
1180 if (is_acpi_node(dev_fwnode(f->dev))) in nxp_fspi_probe()
1181 f->iobase = devm_platform_ioremap_resource(pdev, 0); in nxp_fspi_probe()
1183 f->iobase = devm_platform_ioremap_resource_byname(pdev, "fspi_base"); in nxp_fspi_probe()
1185 if (IS_ERR(f->iobase)) { in nxp_fspi_probe()
1186 ret = PTR_ERR(f->iobase); in nxp_fspi_probe()
1190 /* find the resources - controller memory mapped space */ in nxp_fspi_probe()
1191 if (is_acpi_node(dev_fwnode(f->dev))) in nxp_fspi_probe()
1198 ret = -ENODEV; in nxp_fspi_probe()
1203 f->memmap_phy = res->start; in nxp_fspi_probe()
1204 f->memmap_phy_size = resource_size(res); in nxp_fspi_probe()
1207 if (dev_of_node(&pdev->dev)) { in nxp_fspi_probe()
1208 f->clk_en = devm_clk_get(dev, "fspi_en"); in nxp_fspi_probe()
1209 if (IS_ERR(f->clk_en)) { in nxp_fspi_probe()
1210 ret = PTR_ERR(f->clk_en); in nxp_fspi_probe()
1214 f->clk = devm_clk_get(dev, "fspi"); in nxp_fspi_probe()
1215 if (IS_ERR(f->clk)) { in nxp_fspi_probe()
1216 ret = PTR_ERR(f->clk); in nxp_fspi_probe()
1228 reg = fspi_readl(f, f->iobase + FSPI_INTR); in nxp_fspi_probe()
1230 fspi_writel(f, reg, f->iobase + FSPI_INTR); in nxp_fspi_probe()
1238 nxp_fspi_irq_handler, 0, pdev->name, f); in nxp_fspi_probe()
1244 mutex_init(&f->lock); in nxp_fspi_probe()
1246 ctlr->bus_num = -1; in nxp_fspi_probe()
1247 ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; in nxp_fspi_probe()
1248 ctlr->mem_ops = &nxp_fspi_mem_ops; in nxp_fspi_probe()
1252 ctlr->dev.of_node = np; in nxp_fspi_probe()
1254 ret = devm_spi_register_controller(&pdev->dev, ctlr); in nxp_fspi_probe()
1261 mutex_destroy(&f->lock); in nxp_fspi_probe()
1278 fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0); in nxp_fspi_remove()
1282 mutex_destroy(&f->lock); in nxp_fspi_remove()
1284 if (f->ahb_addr) in nxp_fspi_remove()
1285 iounmap(f->ahb_addr); in nxp_fspi_remove()
1303 { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, },
1304 { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, },
1305 { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, },
1306 { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, },
1307 { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, },
1308 { .compatible = "nxp,imx8ulp-fspi", .data = (void *)&imx8ulp_data, },
1328 .name = "nxp-fspi",