Lines Matching +full:1 +full:f
11 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
74 #define FSPI_MCR0_MDIS BIT(1)
92 #define FSPI_MCR2_ABRRADDR BIT(1)
101 #define FSPI_AHBCR_CLRRXBUF BIT(1)
113 #define FSPI_INTEN_IPCMDGE BIT(1)
125 #define FSPI_INTR_IPCMDGE BIT(1)
199 #define FSPI_IPRXFCR_DMA_EN BIT(1)
204 #define FSPI_IPTXFCR_DMA_EN BIT(1)
210 #define FSPI_DLLACR_DLLRESET BIT(1)
216 #define FSPI_DLLBCR_DLLRESET BIT(1)
223 #define FSPI_STS0_ARB_IDLE BIT(1)
235 #define FSPI_STS2_AREFLOCK BIT(1)
244 #define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
300 #define LUT_PAD(x) (fls(x) - 1)
399 static inline int needs_ip_only(struct nxp_fspi *f)
401 return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY;
411 static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
413 if (f->devtype_data->little_endian)
419 static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
421 if (f->devtype_data->little_endian)
429 struct nxp_fspi *f = dev_id;
433 reg = fspi_readl(f, f->iobase + FSPI_INTR);
434 fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR);
437 complete(&f->c);
442 static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
445 case 1:
458 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller);
461 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
464 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
467 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
470 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
486 if (op->addr.val >= f->memmap_phy_size)
496 (op->data.nbytes > f->devtype_data->ahb_buf_size ||
497 (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
502 op->data.nbytes > f->devtype_data->txfifo)
509 static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
515 if (!f->devtype_data->little_endian)
531 static inline void nxp_fspi_invalid(struct nxp_fspi *f)
536 reg = fspi_readl(f, f->iobase + FSPI_MCR0);
537 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
540 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
545 static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
548 void __iomem *base = f->iobase;
550 int lutidx = 1, i;
551 u32 lut_offset = (f->devtype_data->lut_num - 1) * 4 * 4;
593 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
594 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
599 fspi_writel(f, lutval[i], base + target_lut_reg);
602 dev_dbg(f->dev, "CMD[%02x] lutval[0:%08x 1:%08x 2:%08x 3:%08x], size: 0x%08x\n",
603 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes);
606 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
607 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
610 static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
614 if (is_acpi_node(dev_fwnode(f->dev)))
617 ret = clk_prepare_enable(f->clk_en);
621 ret = clk_prepare_enable(f->clk);
623 clk_disable_unprepare(f->clk_en);
630 static int nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
632 if (is_acpi_node(dev_fwnode(f->dev)))
635 clk_disable_unprepare(f->clk);
636 clk_disable_unprepare(f->clk_en);
641 static void nxp_fspi_dll_calibration(struct nxp_fspi *f)
645 /* Reset the DLL, set the DLLRESET to 1 and then set to 0 */
646 fspi_writel(f, FSPI_DLLACR_DLLRESET, f->iobase + FSPI_DLLACR);
647 fspi_writel(f, FSPI_DLLBCR_DLLRESET, f->iobase + FSPI_DLLBCR);
648 fspi_writel(f, 0, f->iobase + FSPI_DLLACR);
649 fspi_writel(f, 0, f->iobase + FSPI_DLLBCR);
654 * ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock.
658 fspi_writel(f, FSPI_DLLACR_DLLEN | FSPI_DLLACR_SLVDLY(0xF),
659 f->iobase + FSPI_DLLACR);
660 fspi_writel(f, FSPI_DLLBCR_DLLEN | FSPI_DLLBCR_SLVDLY(0xF),
661 f->iobase + FSPI_DLLBCR);
664 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_STS2, FSPI_STS2_AB_LOCK,
667 dev_warn(f->dev, "DLL lock failed, please fix it!\n");
708 static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
719 if (f->selected == spi_get_chipselect(spi, 0))
723 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
724 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
725 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
726 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
729 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
731 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
734 dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0));
736 nxp_fspi_clk_disable_unprep(f);
738 ret = clk_set_rate(f->clk, rate);
742 ret = nxp_fspi_clk_prep_enable(f);
751 nxp_fspi_dll_calibration(f);
753 f->selected = spi_get_chipselect(spi, 0);
756 static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
762 if ((!f->ahb_addr) || start < f->memmap_start ||
763 start + len > f->memmap_start + f->memmap_len) {
764 if (f->ahb_addr)
765 iounmap(f->ahb_addr);
767 f->memmap_start = start;
768 f->memmap_len = max_t(u32, len, NXP_FSPI_MIN_IOMAP);
770 f->ahb_addr = ioremap(f->memmap_phy + f->memmap_start,
771 f->memmap_len);
773 if (!f->ahb_addr) {
774 dev_err(f->dev, "failed to alloc memory\n");
781 f->ahb_addr + start - f->memmap_start, len);
786 static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
789 void __iomem *base = f->iobase;
794 fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
803 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
808 fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR);
809 fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4);
810 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
818 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
825 fspi_writel(f, data, base + FSPI_TFDR + j);
827 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
831 static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
834 void __iomem *base = f->iobase;
845 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
850 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
851 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
853 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
862 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
869 tmp = fspi_readl(f, base + FSPI_RFDR + j);
877 fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
879 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
882 static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
884 void __iomem *base = f->iobase;
889 reg = fspi_readl(f, base + FSPI_IPRXFCR);
893 fspi_writel(f, reg, base + FSPI_IPRXFCR);
895 init_completion(&f->c);
897 fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
903 seqid_lut = f->devtype_data->lut_num - 1;
904 fspi_writel(f, op->data.nbytes |
910 fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
913 if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000)))
918 nxp_fspi_read_rxfifo(f, op);
925 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller);
928 mutex_lock(&f->lock);
931 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
932 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
935 nxp_fspi_select_mem(f, mem->spi, op);
937 nxp_fspi_prepare_lut(f, op);
944 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
946 !needs_ip_only(f)) {
947 err = nxp_fspi_read_ahb(f, op);
950 nxp_fspi_fill_txfifo(f, op);
952 err = nxp_fspi_do_op(f, op);
956 nxp_fspi_invalid(f);
958 mutex_unlock(&f->lock);
965 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller);
968 if (op->data.nbytes > f->devtype_data->txfifo)
969 op->data.nbytes = f->devtype_data->txfifo;
971 if (op->data.nbytes > f->devtype_data->ahb_buf_size)
972 op->data.nbytes = f->devtype_data->ahb_buf_size;
973 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
979 needs_ip_only(f) &&
980 op->data.nbytes > f->devtype_data->rxfifo)
981 op->data.nbytes = f->devtype_data->rxfifo;
986 static void erratum_err050568(struct nxp_fspi *f)
998 dev_dbg(f->dev, "Errata applicable only for LS1028A\n");
1004 dev_err(f->dev, "No syscon regmap\n");
1013 dev_dbg(f->dev, "val: 0x%08x, sys_pll_ratio: %d\n", val, sys_pll_ratio);
1017 f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY;
1022 dev_err(f->dev, "Errata cannot be executed. Read via IP bus may not work\n");
1025 static int nxp_fspi_default_setup(struct nxp_fspi *f)
1027 void __iomem *base = f->iobase;
1032 nxp_fspi_clk_disable_unprep(f);
1035 ret = clk_set_rate(f->clk, 20000000);
1039 ret = nxp_fspi_clk_prep_enable(f);
1049 if (of_device_is_compatible(f->dev->of_node, "nxp,lx2160a-fspi"))
1050 erratum_err050568(f);
1054 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
1059 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
1063 * line delay cell override mode, and use 1 fixed delay cell in DLL delay
1066 fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
1067 fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
1070 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) |
1078 reg = fspi_readl(f, f->iobase + FSPI_MCR2);
1080 fspi_writel(f, reg, base + FSPI_MCR2);
1084 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
1090 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
1094 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
1099 fspi_writel(f, reg, base + FSPI_FLSHA1CR1);
1100 fspi_writel(f, reg, base + FSPI_FLSHA2CR1);
1101 fspi_writel(f, reg, base + FSPI_FLSHB1CR1);
1102 fspi_writel(f, reg, base + FSPI_FLSHB2CR1);
1109 seqid_lut = f->devtype_data->lut_num - 1;
1111 fspi_writel(f, seqid_lut, base + FSPI_FLSHA1CR2);
1112 fspi_writel(f, seqid_lut, base + FSPI_FLSHA2CR2);
1113 fspi_writel(f, seqid_lut, base + FSPI_FLSHB1CR2);
1114 fspi_writel(f, seqid_lut, base + FSPI_FLSHB2CR2);
1116 f->selected = -1;
1119 fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN);
1126 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller);
1131 if (of_get_available_child_count(f->dev->of_node) == 1)
1132 return dev_name(f->dev);
1135 "%s-%d", dev_name(f->dev),
1163 struct nxp_fspi *f;
1167 ctlr = spi_alloc_host(&pdev->dev, sizeof(*f));
1174 f = spi_controller_get_devdata(ctlr);
1175 f->dev = dev;
1176 f->devtype_data = (struct nxp_fspi_devtype_data *)device_get_match_data(dev);
1177 if (!f->devtype_data) {
1182 platform_set_drvdata(pdev, f);
1185 if (is_acpi_node(dev_fwnode(f->dev)))
1186 f->iobase = devm_platform_ioremap_resource(pdev, 0);
1188 f->iobase = devm_platform_ioremap_resource_byname(pdev, "fspi_base");
1190 if (IS_ERR(f->iobase)) {
1191 ret = PTR_ERR(f->iobase);
1196 if (is_acpi_node(dev_fwnode(f->dev)))
1197 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1208 f->memmap_phy = res->start;
1209 f->memmap_phy_size = resource_size(res);
1213 f->clk_en = devm_clk_get(dev, "fspi_en");
1214 if (IS_ERR(f->clk_en)) {
1215 ret = PTR_ERR(f->clk_en);
1219 f->clk = devm_clk_get(dev, "fspi");
1220 if (IS_ERR(f->clk)) {
1221 ret = PTR_ERR(f->clk);
1225 ret = nxp_fspi_clk_prep_enable(f);
1233 reg = fspi_readl(f, f->iobase + FSPI_INTR);
1235 fspi_writel(f, reg, f->iobase + FSPI_INTR);
1243 nxp_fspi_irq_handler, 0, pdev->name, f);
1249 mutex_init(&f->lock);
1251 ctlr->bus_num = -1;
1256 nxp_fspi_default_setup(f);
1267 mutex_destroy(&f->lock);
1270 nxp_fspi_clk_disable_unprep(f);
1281 struct nxp_fspi *f = platform_get_drvdata(pdev);
1284 fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);
1286 nxp_fspi_clk_disable_unprep(f);
1288 mutex_destroy(&f->lock);
1290 if (f->ahb_addr)
1291 iounmap(f->ahb_addr);
1301 struct nxp_fspi *f = dev_get_drvdata(dev);
1303 nxp_fspi_default_setup(f);