Lines Matching +full:txrx +full:-
1 // SPDX-License-Identifier: GPL-2.0+
15 // Based on code from U-Boot bootloader by:
18 // Based on spi-stmp.c, which is:
28 #include <linux/dma-mapping.h>
40 #include <linux/spi/mxs-spi.h>
42 #include <linux/dma/mxs-dma.h>
44 #define DRIVER_NAME "mxs-spi"
52 * Flags for txrx functions. More efficient that using an argument register for
56 #define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
67 struct mxs_spi *spi = spi_controller_get_devdata(dev->controller);
68 struct mxs_ssp *ssp = &spi->ssp;
69 const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
72 dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
73 return -EINVAL;
76 if (hz != spi->sck) {
80 * ssp->clk_rate. Otherwise we would set the rate every transfer
83 spi->sck = hz;
91 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
95 ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
96 ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
97 ssp->base + HW_SSP_CTRL1(ssp));
99 writel(0x0, ssp->base + HW_SSP_CMD0);
100 writel(0x0, ssp->base + HW_SSP_CMD1);
115 * toggle the chip-select lines (nCS pins).
128 struct mxs_ssp *ssp = &spi->ssp;
132 reg = readl_relaxed(ssp->base + offset);
143 return -ETIMEDOUT;
150 complete(&spi->c);
157 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
159 readl(ssp->base + HW_SSP_CTRL1(ssp)),
160 readl(ssp->base + HW_SSP_STATUS(ssp)));
168 struct mxs_ssp *ssp = &spi->ssp;
183 return -EINVAL;
187 return -ENOMEM;
189 reinit_completion(&spi->c);
192 ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
206 * De-assert CS on last segment if flag is set (i.e., no more
212 if (ssp->devid == IMX23_SSP) {
223 ret = -ENOMEM;
234 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
237 len -= min;
241 desc = dmaengine_prep_slave_sg(ssp->dmach,
243 (ssp->devid == IMX23_SSP) ? 1 : 4,
247 dev_err(ssp->dev,
249 ret = -EINVAL;
253 desc = dmaengine_prep_slave_sg(ssp->dmach,
259 dev_err(ssp->dev,
261 ret = -EINVAL;
270 desc->callback = mxs_ssp_dma_irq_callback;
271 desc->callback_param = spi;
275 dma_async_issue_pending(ssp->dmach);
277 if (!wait_for_completion_timeout(&spi->c,
279 dev_err(ssp->dev, "DMA transfer timeout\n");
280 ret = -ETIMEDOUT;
281 dmaengine_terminate_all(ssp->dmach);
288 while (--sg_count >= 0) {
290 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
303 struct mxs_ssp *ssp = &spi->ssp;
306 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
308 while (len--) {
311 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
313 if (ssp->devid == IMX23_SSP) {
315 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
317 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
319 writel(1, ssp->base + HW_SSP_XFER_SIZE);
324 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
327 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
330 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
333 return -ETIMEDOUT;
336 writel(*buf, ssp->base + HW_SSP_DATA(ssp));
339 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
344 return -ETIMEDOUT;
346 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
350 return -ETIMEDOUT;
358 return -ETIMEDOUT;
365 struct mxs_ssp *ssp = &spi->ssp;
372 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
373 writel(mxs_spi_cs_to_reg(spi_get_chipselect(m->spi, 0)),
374 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
376 list_for_each_entry(t, &m->transfers, transfer_list) {
380 status = mxs_spi_setup_transfer(m->spi, t);
384 t->effective_speed_hz = ssp->clk_rate;
386 /* De-assert on last transfer, inverted by cs_change flag */
387 flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
399 if (t->len < 32) {
401 ssp->base + HW_SSP_CTRL1(ssp) +
404 if (t->tx_buf)
406 (void *)t->tx_buf,
407 t->len, flag | TXRX_WRITE);
408 if (t->rx_buf)
410 t->rx_buf, t->len,
414 ssp->base + HW_SSP_CTRL1(ssp) +
417 if (t->tx_buf)
419 (void *)t->tx_buf, t->len,
421 if (t->rx_buf)
423 t->rx_buf, t->len,
430 stmp_reset_block(ssp->base);
434 m->actual_length += t->len;
437 m->status = status;
447 struct mxs_ssp *ssp = &spi->ssp;
450 clk_disable_unprepare(ssp->clk);
454 int ret2 = clk_prepare_enable(ssp->clk);
468 struct mxs_ssp *ssp = &spi->ssp;
475 ret = clk_prepare_enable(ssp->clk);
522 { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
523 { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
531 of_match_device(mxs_spi_dt_ids, &pdev->dev);
532 struct device_node *np = pdev->dev.of_node;
544 * as a default. Override with "clock-frequency" DT prop.
556 clk = devm_clk_get(&pdev->dev, NULL);
560 devid = (enum mxs_ssp_id) of_id->data;
561 ret = of_property_read_u32(np, "clock-frequency",
566 host = spi_alloc_host(&pdev->dev, sizeof(*spi));
568 return -ENOMEM;
572 host->transfer_one_message = mxs_spi_transfer_one;
573 host->bits_per_word_mask = SPI_BPW_MASK(8);
574 host->mode_bits = SPI_CPOL | SPI_CPHA;
575 host->num_chipselect = 3;
576 host->dev.of_node = np;
577 host->flags = SPI_CONTROLLER_HALF_DUPLEX;
578 host->auto_runtime_pm = true;
581 ssp = &spi->ssp;
582 ssp->dev = &pdev->dev;
583 ssp->clk = clk;
584 ssp->base = base;
585 ssp->devid = devid;
587 init_completion(&spi->c);
589 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
590 dev_name(&pdev->dev), ssp);
594 ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
595 if (IS_ERR(ssp->dmach)) {
596 dev_err(ssp->dev, "Failed to request DMA\n");
597 ret = PTR_ERR(ssp->dmach);
601 pm_runtime_enable(ssp->dev);
602 if (!pm_runtime_enabled(ssp->dev)) {
603 ret = mxs_spi_runtime_resume(ssp->dev);
605 dev_err(ssp->dev, "runtime resume failed\n");
610 ret = pm_runtime_resume_and_get(ssp->dev);
612 dev_err(ssp->dev, "runtime_get_sync failed\n");
616 clk_set_rate(ssp->clk, clk_freq);
618 ret = stmp_reset_block(ssp->base);
622 ret = devm_spi_register_controller(&pdev->dev, host);
624 dev_err(&pdev->dev, "Cannot register SPI host, %d\n", ret);
628 pm_runtime_put(ssp->dev);
633 pm_runtime_put(ssp->dev);
635 pm_runtime_disable(ssp->dev);
637 dma_release_channel(ssp->dmach);
651 ssp = &spi->ssp;
653 pm_runtime_disable(&pdev->dev);
654 if (!pm_runtime_status_suspended(&pdev->dev))
655 mxs_spi_runtime_suspend(&pdev->dev);
657 dma_release_channel(ssp->dmach);
675 MODULE_ALIAS("platform:mxs-spi");