Lines Matching +full:rx +full:- +full:inactive
1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/platform_data/spi-mt65xx.h>
21 #include <linux/spi/spi-mem.h>
22 #include <linux/dma-mapping.h>
115 * struct mtk_spi_compatible - device data structure
117 * @must_tx: Must explicitly send dummy TX bytes to do RX only transfer
133 * struct mtk_spi - SPI driver instance
146 * @rx_sgl: RX transfer scatterlist
148 * @rx_sgl_len: Size of RX DMA transfer
151 * @spimem_done: SPI-MEM operation completion
152 * @use_spimem: Enables SPI-MEM
154 * @tx_dma: DMA start for SPI-MEM TX
155 * @rx_dma: DMA start for SPI-MEM RX
230 { .compatible = "mediatek,spi-ipm",
233 { .compatible = "mediatek,mt2701-spi",
236 { .compatible = "mediatek,mt2712-spi",
239 { .compatible = "mediatek,mt6589-spi",
242 { .compatible = "mediatek,mt6765-spi",
245 { .compatible = "mediatek,mt7622-spi",
248 { .compatible = "mediatek,mt7629-spi",
251 { .compatible = "mediatek,mt8135-spi",
254 { .compatible = "mediatek,mt8173-spi",
257 { .compatible = "mediatek,mt8183-spi",
260 { .compatible = "mediatek,mt8192-spi",
263 { .compatible = "mediatek,mt6893-spi",
275 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
277 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
279 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
281 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
286 struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); in mtk_spi_set_hw_cs_timing()
287 struct spi_delay *cs_setup = &spi->cs_setup; in mtk_spi_set_hw_cs_timing()
288 struct spi_delay *cs_hold = &spi->cs_hold; in mtk_spi_set_hw_cs_timing()
289 struct spi_delay *cs_inactive = &spi->cs_inactive; in mtk_spi_set_hw_cs_timing()
290 u32 setup, hold, inactive; in mtk_spi_set_hw_cs_timing() local
297 setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; in mtk_spi_set_hw_cs_timing()
302 hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; in mtk_spi_set_hw_cs_timing()
307 inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; in mtk_spi_set_hw_cs_timing()
310 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
311 if (mdata->dev_comp->enhance_timing) { in mtk_spi_set_hw_cs_timing()
315 reg_val |= (((hold - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
321 reg_val |= (((setup - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
328 reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
333 reg_val |= (((setup - 1) & 0xff) in mtk_spi_set_hw_cs_timing()
337 writel(reg_val, mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
340 if (inactive) { in mtk_spi_set_hw_cs_timing()
341 inactive = min_t(u32, inactive, 0x100); in mtk_spi_set_hw_cs_timing()
342 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_set_hw_cs_timing()
344 reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); in mtk_spi_set_hw_cs_timing()
345 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_set_hw_cs_timing()
356 struct mtk_chip_config *chip_config = spi->controller_data; in mtk_spi_hw_init()
359 cpha = spi->mode & SPI_CPHA ? 1 : 0; in mtk_spi_hw_init()
360 cpol = spi->mode & SPI_CPOL ? 1 : 0; in mtk_spi_hw_init()
362 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
363 if (mdata->dev_comp->ipm_design) { in mtk_spi_hw_init()
366 if (spi->mode & SPI_LOOP) in mtk_spi_hw_init()
382 if (spi->mode & SPI_LSB_FIRST) { in mtk_spi_hw_init()
390 /* set the tx/rx endian */ in mtk_spi_hw_init()
399 if (mdata->dev_comp->enhance_timing) { in mtk_spi_hw_init()
401 if (spi->mode & SPI_CS_HIGH) in mtk_spi_hw_init()
406 if (chip_config->sample_sel) in mtk_spi_hw_init()
421 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
424 if (mdata->dev_comp->need_pad_sel) in mtk_spi_hw_init()
425 writel(mdata->pad_sel[spi_get_chipselect(spi, 0)], in mtk_spi_hw_init()
426 mdata->base + SPI_PAD_SEL_REG); in mtk_spi_hw_init()
429 if (mdata->dev_comp->enhance_timing) { in mtk_spi_hw_init()
430 if (mdata->dev_comp->ipm_design) { in mtk_spi_hw_init()
431 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
433 reg_val |= ((chip_config->tick_delay & 0x7) in mtk_spi_hw_init()
435 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
437 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
439 reg_val |= ((chip_config->tick_delay & 0x7) in mtk_spi_hw_init()
441 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
444 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
446 reg_val |= ((chip_config->tick_delay & 0x3) in mtk_spi_hw_init()
448 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
459 return mtk_spi_hw_init(host, msg->spi); in mtk_spi_prepare_message()
465 struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); in mtk_spi_set_cs()
467 if (spi->mode & SPI_CS_HIGH) in mtk_spi_set_cs()
470 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
473 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
476 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
477 mdata->state = MTK_SPI_IDLE; in mtk_spi_set_cs()
488 if (speed_hz < mdata->spi_clk_hz / 2) in mtk_spi_prepare_transfer()
489 div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); in mtk_spi_prepare_transfer()
495 if (mdata->dev_comp->enhance_timing) { in mtk_spi_prepare_transfer()
496 reg_val = readl(mdata->base + SPI_CFG2_REG); in mtk_spi_prepare_transfer()
498 reg_val |= (((sck_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
501 reg_val |= (((sck_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
503 writel(reg_val, mdata->base + SPI_CFG2_REG); in mtk_spi_prepare_transfer()
505 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_prepare_transfer()
507 reg_val |= (((sck_time - 1) & 0xff) in mtk_spi_prepare_transfer()
510 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); in mtk_spi_prepare_transfer()
511 writel(reg_val, mdata->base + SPI_CFG0_REG); in mtk_spi_prepare_transfer()
520 if (mdata->dev_comp->ipm_design) in mtk_spi_setup_packet()
522 mdata->xfer_len, in mtk_spi_setup_packet()
526 mdata->xfer_len, in mtk_spi_setup_packet()
529 packet_loop = mdata->xfer_len / packet_size; in mtk_spi_setup_packet()
531 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_setup_packet()
532 if (mdata->dev_comp->ipm_design) in mtk_spi_setup_packet()
536 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; in mtk_spi_setup_packet()
538 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; in mtk_spi_setup_packet()
539 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_setup_packet()
547 cmd = readl(mdata->base + SPI_CMD_REG); in mtk_spi_enable_transfer()
548 if (mdata->state == MTK_SPI_IDLE) in mtk_spi_enable_transfer()
552 writel(cmd, mdata->base + SPI_CMD_REG); in mtk_spi_enable_transfer()
559 if (mdata->dev_comp->ipm_design) { in mtk_spi_get_mult_delta()
575 if (mdata->tx_sgl_len && mdata->rx_sgl_len) { in mtk_spi_update_mdata_len()
576 if (mdata->tx_sgl_len > mdata->rx_sgl_len) { in mtk_spi_update_mdata_len()
577 mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len); in mtk_spi_update_mdata_len()
578 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; in mtk_spi_update_mdata_len()
579 mdata->rx_sgl_len = mult_delta; in mtk_spi_update_mdata_len()
580 mdata->tx_sgl_len -= mdata->xfer_len; in mtk_spi_update_mdata_len()
582 mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len); in mtk_spi_update_mdata_len()
583 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; in mtk_spi_update_mdata_len()
584 mdata->tx_sgl_len = mult_delta; in mtk_spi_update_mdata_len()
585 mdata->rx_sgl_len -= mdata->xfer_len; in mtk_spi_update_mdata_len()
587 } else if (mdata->tx_sgl_len) { in mtk_spi_update_mdata_len()
588 mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len); in mtk_spi_update_mdata_len()
589 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; in mtk_spi_update_mdata_len()
590 mdata->tx_sgl_len = mult_delta; in mtk_spi_update_mdata_len()
591 } else if (mdata->rx_sgl_len) { in mtk_spi_update_mdata_len()
592 mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len); in mtk_spi_update_mdata_len()
593 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; in mtk_spi_update_mdata_len()
594 mdata->rx_sgl_len = mult_delta; in mtk_spi_update_mdata_len()
603 if (mdata->tx_sgl) { in mtk_spi_setup_dma_addr()
604 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK), in mtk_spi_setup_dma_addr()
605 mdata->base + SPI_TX_SRC_REG); in mtk_spi_setup_dma_addr()
607 if (mdata->dev_comp->dma_ext) in mtk_spi_setup_dma_addr()
608 writel((u32)(xfer->tx_dma >> 32), in mtk_spi_setup_dma_addr()
609 mdata->base + SPI_TX_SRC_REG_64); in mtk_spi_setup_dma_addr()
613 if (mdata->rx_sgl) { in mtk_spi_setup_dma_addr()
614 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK), in mtk_spi_setup_dma_addr()
615 mdata->base + SPI_RX_DST_REG); in mtk_spi_setup_dma_addr()
617 if (mdata->dev_comp->dma_ext) in mtk_spi_setup_dma_addr()
618 writel((u32)(xfer->rx_dma >> 32), in mtk_spi_setup_dma_addr()
619 mdata->base + SPI_RX_DST_REG_64); in mtk_spi_setup_dma_addr()
632 mdata->cur_transfer = xfer; in mtk_spi_fifo_transfer()
633 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); in mtk_spi_fifo_transfer()
634 mdata->num_xfered = 0; in mtk_spi_fifo_transfer()
635 mtk_spi_prepare_transfer(host, xfer->speed_hz); in mtk_spi_fifo_transfer()
638 if (xfer->tx_buf) { in mtk_spi_fifo_transfer()
639 cnt = xfer->len / 4; in mtk_spi_fifo_transfer()
640 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); in mtk_spi_fifo_transfer()
641 remainder = xfer->len % 4; in mtk_spi_fifo_transfer()
644 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); in mtk_spi_fifo_transfer()
645 writel(reg_val, mdata->base + SPI_TX_DATA_REG); in mtk_spi_fifo_transfer()
661 mdata->tx_sgl = NULL; in mtk_spi_dma_transfer()
662 mdata->rx_sgl = NULL; in mtk_spi_dma_transfer()
663 mdata->tx_sgl_len = 0; in mtk_spi_dma_transfer()
664 mdata->rx_sgl_len = 0; in mtk_spi_dma_transfer()
665 mdata->cur_transfer = xfer; in mtk_spi_dma_transfer()
666 mdata->num_xfered = 0; in mtk_spi_dma_transfer()
668 mtk_spi_prepare_transfer(host, xfer->speed_hz); in mtk_spi_dma_transfer()
670 cmd = readl(mdata->base + SPI_CMD_REG); in mtk_spi_dma_transfer()
671 if (xfer->tx_buf) in mtk_spi_dma_transfer()
673 if (xfer->rx_buf) in mtk_spi_dma_transfer()
675 writel(cmd, mdata->base + SPI_CMD_REG); in mtk_spi_dma_transfer()
677 if (xfer->tx_buf) in mtk_spi_dma_transfer()
678 mdata->tx_sgl = xfer->tx_sg.sgl; in mtk_spi_dma_transfer()
679 if (xfer->rx_buf) in mtk_spi_dma_transfer()
680 mdata->rx_sgl = xfer->rx_sg.sgl; in mtk_spi_dma_transfer()
682 if (mdata->tx_sgl) { in mtk_spi_dma_transfer()
683 xfer->tx_dma = sg_dma_address(mdata->tx_sgl); in mtk_spi_dma_transfer()
684 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); in mtk_spi_dma_transfer()
686 if (mdata->rx_sgl) { in mtk_spi_dma_transfer()
687 xfer->rx_dma = sg_dma_address(mdata->rx_sgl); in mtk_spi_dma_transfer()
688 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); in mtk_spi_dma_transfer()
703 struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); in mtk_spi_transfer_one()
707 if (mdata->dev_comp->ipm_design) { in mtk_spi_transfer_one()
708 if (!xfer->tx_buf || !xfer->rx_buf) { in mtk_spi_transfer_one()
710 if (xfer->rx_buf) in mtk_spi_transfer_one()
713 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); in mtk_spi_transfer_one()
716 if (host->can_dma(host, spi, xfer)) in mtk_spi_transfer_one()
726 /* Buffers for DMA transactions must be 4-byte aligned */ in mtk_spi_can_dma()
727 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE && in mtk_spi_can_dma()
728 (unsigned long)xfer->tx_buf % 4 == 0 && in mtk_spi_can_dma()
729 (unsigned long)xfer->rx_buf % 4 == 0); in mtk_spi_can_dma()
734 struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); in mtk_spi_setup()
736 if (!spi->controller_data) in mtk_spi_setup()
737 spi->controller_data = (void *)&mtk_default_chip_info; in mtk_spi_setup()
739 if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0)) in mtk_spi_setup()
740 /* CS de-asserted, gpiolib will handle inversion */ in mtk_spi_setup()
751 struct spi_transfer *xfer = mdata->cur_transfer; in mtk_spi_interrupt_thread()
753 if (!host->can_dma(host, NULL, xfer)) { in mtk_spi_interrupt_thread()
754 if (xfer->rx_buf) { in mtk_spi_interrupt_thread()
755 cnt = mdata->xfer_len / 4; in mtk_spi_interrupt_thread()
756 ioread32_rep(mdata->base + SPI_RX_DATA_REG, in mtk_spi_interrupt_thread()
757 xfer->rx_buf + mdata->num_xfered, cnt); in mtk_spi_interrupt_thread()
758 remainder = mdata->xfer_len % 4; in mtk_spi_interrupt_thread()
760 reg_val = readl(mdata->base + SPI_RX_DATA_REG); in mtk_spi_interrupt_thread()
761 memcpy(xfer->rx_buf + (cnt * 4) + mdata->num_xfered, in mtk_spi_interrupt_thread()
767 mdata->num_xfered += mdata->xfer_len; in mtk_spi_interrupt_thread()
768 if (mdata->num_xfered == xfer->len) { in mtk_spi_interrupt_thread()
773 len = xfer->len - mdata->num_xfered; in mtk_spi_interrupt_thread()
774 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len); in mtk_spi_interrupt_thread()
777 if (xfer->tx_buf) { in mtk_spi_interrupt_thread()
778 cnt = mdata->xfer_len / 4; in mtk_spi_interrupt_thread()
779 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, in mtk_spi_interrupt_thread()
780 xfer->tx_buf + mdata->num_xfered, cnt); in mtk_spi_interrupt_thread()
782 remainder = mdata->xfer_len % 4; in mtk_spi_interrupt_thread()
786 xfer->tx_buf + (cnt * 4) + mdata->num_xfered, in mtk_spi_interrupt_thread()
788 writel(reg_val, mdata->base + SPI_TX_DATA_REG); in mtk_spi_interrupt_thread()
797 if (mdata->tx_sgl) in mtk_spi_interrupt_thread()
798 xfer->tx_dma += mdata->xfer_len; in mtk_spi_interrupt_thread()
799 if (mdata->rx_sgl) in mtk_spi_interrupt_thread()
800 xfer->rx_dma += mdata->xfer_len; in mtk_spi_interrupt_thread()
802 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { in mtk_spi_interrupt_thread()
803 mdata->tx_sgl = sg_next(mdata->tx_sgl); in mtk_spi_interrupt_thread()
804 if (mdata->tx_sgl) { in mtk_spi_interrupt_thread()
805 xfer->tx_dma = sg_dma_address(mdata->tx_sgl); in mtk_spi_interrupt_thread()
806 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); in mtk_spi_interrupt_thread()
809 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { in mtk_spi_interrupt_thread()
810 mdata->rx_sgl = sg_next(mdata->rx_sgl); in mtk_spi_interrupt_thread()
811 if (mdata->rx_sgl) { in mtk_spi_interrupt_thread()
812 xfer->rx_dma = sg_dma_address(mdata->rx_sgl); in mtk_spi_interrupt_thread()
813 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); in mtk_spi_interrupt_thread()
817 if (!mdata->tx_sgl && !mdata->rx_sgl) { in mtk_spi_interrupt_thread()
819 cmd = readl(mdata->base + SPI_CMD_REG); in mtk_spi_interrupt_thread()
822 writel(cmd, mdata->base + SPI_CMD_REG); in mtk_spi_interrupt_thread()
842 reg_val = readl(mdata->base + SPI_STATUS0_REG); in mtk_spi_interrupt()
844 mdata->state = MTK_SPI_PAUSED; in mtk_spi_interrupt()
846 mdata->state = MTK_SPI_IDLE; in mtk_spi_interrupt()
848 /* SPI-MEM ops */ in mtk_spi_interrupt()
849 if (mdata->use_spimem) { in mtk_spi_interrupt()
850 complete(&mdata->spimem_done); in mtk_spi_interrupt()
862 if (op->data.dir != SPI_MEM_NO_DATA) { in mtk_spi_mem_adjust_op_size()
863 opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes; in mtk_spi_mem_adjust_op_size()
864 if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { in mtk_spi_mem_adjust_op_size()
865 op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len; in mtk_spi_mem_adjust_op_size()
866 /* force data buffer dma-aligned. */ in mtk_spi_mem_adjust_op_size()
867 op->data.nbytes -= op->data.nbytes % 4; in mtk_spi_mem_adjust_op_size()
880 if (op->addr.nbytes && op->dummy.nbytes && in mtk_spi_mem_supports_op()
881 op->addr.buswidth != op->dummy.buswidth) in mtk_spi_mem_supports_op()
884 if (op->addr.nbytes + op->dummy.nbytes > 16) in mtk_spi_mem_supports_op()
887 if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { in mtk_spi_mem_supports_op()
888 if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > in mtk_spi_mem_supports_op()
890 op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0) in mtk_spi_mem_supports_op()
902 writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK), in mtk_spi_mem_setup_dma_xfer()
903 mdata->base + SPI_TX_SRC_REG); in mtk_spi_mem_setup_dma_xfer()
905 if (mdata->dev_comp->dma_ext) in mtk_spi_mem_setup_dma_xfer()
906 writel((u32)(mdata->tx_dma >> 32), in mtk_spi_mem_setup_dma_xfer()
907 mdata->base + SPI_TX_SRC_REG_64); in mtk_spi_mem_setup_dma_xfer()
910 if (op->data.dir == SPI_MEM_DATA_IN) { in mtk_spi_mem_setup_dma_xfer()
911 writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK), in mtk_spi_mem_setup_dma_xfer()
912 mdata->base + SPI_RX_DST_REG); in mtk_spi_mem_setup_dma_xfer()
914 if (mdata->dev_comp->dma_ext) in mtk_spi_mem_setup_dma_xfer()
915 writel((u32)(mdata->rx_dma >> 32), in mtk_spi_mem_setup_dma_xfer()
916 mdata->base + SPI_RX_DST_REG_64); in mtk_spi_mem_setup_dma_xfer()
924 struct mtk_spi *mdata = spi_controller_get_devdata(mem->spi->controller); in mtk_spi_transfer_wait()
932 if (op->data.dir == SPI_MEM_NO_DATA) in mtk_spi_transfer_wait()
935 ms *= op->data.nbytes; in mtk_spi_transfer_wait()
936 ms = div_u64(ms, mem->spi->max_speed_hz); in mtk_spi_transfer_wait()
942 if (!wait_for_completion_timeout(&mdata->spimem_done, in mtk_spi_transfer_wait()
944 dev_err(mdata->dev, "spi-mem transfer timeout\n"); in mtk_spi_transfer_wait()
945 return -ETIMEDOUT; in mtk_spi_transfer_wait()
954 struct mtk_spi *mdata = spi_controller_get_devdata(mem->spi->controller); in mtk_spi_mem_exec_op()
959 mdata->use_spimem = true; in mtk_spi_mem_exec_op()
960 reinit_completion(&mdata->spimem_done); in mtk_spi_mem_exec_op()
963 mtk_spi_hw_init(mem->spi->controller, mem->spi); in mtk_spi_mem_exec_op()
964 mtk_spi_prepare_transfer(mem->spi->controller, mem->spi->max_speed_hz); in mtk_spi_mem_exec_op()
966 reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); in mtk_spi_mem_exec_op()
973 if (op->addr.nbytes || op->dummy.nbytes) in mtk_spi_mem_exec_op()
974 reg_val |= (op->addr.nbytes + op->dummy.nbytes) << in mtk_spi_mem_exec_op()
978 if (op->data.dir == SPI_MEM_NO_DATA) { in mtk_spi_mem_exec_op()
980 writel(0, mdata->base + SPI_CFG1_REG); in mtk_spi_mem_exec_op()
983 mdata->xfer_len = op->data.nbytes; in mtk_spi_mem_exec_op()
984 mtk_spi_setup_packet(mem->spi->controller); in mtk_spi_mem_exec_op()
987 if (op->addr.nbytes || op->dummy.nbytes) { in mtk_spi_mem_exec_op()
988 if (op->addr.buswidth == 1 || op->dummy.buswidth == 1) in mtk_spi_mem_exec_op()
994 if (op->addr.buswidth == 2 || in mtk_spi_mem_exec_op()
995 op->dummy.buswidth == 2 || in mtk_spi_mem_exec_op()
996 op->data.buswidth == 2) in mtk_spi_mem_exec_op()
998 else if (op->addr.buswidth == 4 || in mtk_spi_mem_exec_op()
999 op->dummy.buswidth == 4 || in mtk_spi_mem_exec_op()
1000 op->data.buswidth == 4) in mtk_spi_mem_exec_op()
1009 if (op->data.dir == SPI_MEM_DATA_IN) in mtk_spi_mem_exec_op()
1013 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); in mtk_spi_mem_exec_op()
1015 tx_size = 1 + op->addr.nbytes + op->dummy.nbytes; in mtk_spi_mem_exec_op()
1016 if (op->data.dir == SPI_MEM_DATA_OUT) in mtk_spi_mem_exec_op()
1017 tx_size += op->data.nbytes; in mtk_spi_mem_exec_op()
1023 mdata->use_spimem = false; in mtk_spi_mem_exec_op()
1024 return -ENOMEM; in mtk_spi_mem_exec_op()
1027 tx_tmp_buf[0] = op->cmd.opcode; in mtk_spi_mem_exec_op()
1029 if (op->addr.nbytes) { in mtk_spi_mem_exec_op()
1032 for (i = 0; i < op->addr.nbytes; i++) in mtk_spi_mem_exec_op()
1033 tx_tmp_buf[i + 1] = op->addr.val >> in mtk_spi_mem_exec_op()
1034 (8 * (op->addr.nbytes - i - 1)); in mtk_spi_mem_exec_op()
1037 if (op->dummy.nbytes) in mtk_spi_mem_exec_op()
1038 memset(tx_tmp_buf + op->addr.nbytes + 1, in mtk_spi_mem_exec_op()
1040 op->dummy.nbytes); in mtk_spi_mem_exec_op()
1042 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) in mtk_spi_mem_exec_op()
1043 memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, in mtk_spi_mem_exec_op()
1044 op->data.buf.out, in mtk_spi_mem_exec_op()
1045 op->data.nbytes); in mtk_spi_mem_exec_op()
1047 mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf, in mtk_spi_mem_exec_op()
1049 if (dma_mapping_error(mdata->dev, mdata->tx_dma)) { in mtk_spi_mem_exec_op()
1050 ret = -ENOMEM; in mtk_spi_mem_exec_op()
1054 if (op->data.dir == SPI_MEM_DATA_IN) { in mtk_spi_mem_exec_op()
1055 if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { in mtk_spi_mem_exec_op()
1056 rx_tmp_buf = kzalloc(op->data.nbytes, in mtk_spi_mem_exec_op()
1059 ret = -ENOMEM; in mtk_spi_mem_exec_op()
1063 rx_tmp_buf = op->data.buf.in; in mtk_spi_mem_exec_op()
1066 mdata->rx_dma = dma_map_single(mdata->dev, in mtk_spi_mem_exec_op()
1068 op->data.nbytes, in mtk_spi_mem_exec_op()
1070 if (dma_mapping_error(mdata->dev, mdata->rx_dma)) { in mtk_spi_mem_exec_op()
1071 ret = -ENOMEM; in mtk_spi_mem_exec_op()
1076 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1078 if (op->data.dir == SPI_MEM_DATA_IN) in mtk_spi_mem_exec_op()
1080 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1082 mtk_spi_mem_setup_dma_xfer(mem->spi->controller, op); in mtk_spi_mem_exec_op()
1084 mtk_spi_enable_transfer(mem->spi->controller); in mtk_spi_mem_exec_op()
1092 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1094 if (op->data.dir == SPI_MEM_DATA_IN) in mtk_spi_mem_exec_op()
1096 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1099 if (op->data.dir == SPI_MEM_DATA_IN) { in mtk_spi_mem_exec_op()
1100 dma_unmap_single(mdata->dev, mdata->rx_dma, in mtk_spi_mem_exec_op()
1101 op->data.nbytes, DMA_FROM_DEVICE); in mtk_spi_mem_exec_op()
1102 if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) in mtk_spi_mem_exec_op()
1103 memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); in mtk_spi_mem_exec_op()
1106 if (op->data.dir == SPI_MEM_DATA_IN && in mtk_spi_mem_exec_op()
1107 !IS_ALIGNED((size_t)op->data.buf.in, 4)) in mtk_spi_mem_exec_op()
1110 dma_unmap_single(mdata->dev, mdata->tx_dma, in mtk_spi_mem_exec_op()
1114 mdata->use_spimem = false; in mtk_spi_mem_exec_op()
1127 struct device *dev = &pdev->dev; in mtk_spi_probe()
1134 return dev_err_probe(dev, -ENOMEM, "failed to alloc spi host\n"); in mtk_spi_probe()
1136 host->auto_runtime_pm = true; in mtk_spi_probe()
1137 host->dev.of_node = dev->of_node; in mtk_spi_probe()
1138 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; in mtk_spi_probe()
1140 host->set_cs = mtk_spi_set_cs; in mtk_spi_probe()
1141 host->prepare_message = mtk_spi_prepare_message; in mtk_spi_probe()
1142 host->transfer_one = mtk_spi_transfer_one; in mtk_spi_probe()
1143 host->can_dma = mtk_spi_can_dma; in mtk_spi_probe()
1144 host->setup = mtk_spi_setup; in mtk_spi_probe()
1145 host->set_cs_timing = mtk_spi_set_hw_cs_timing; in mtk_spi_probe()
1146 host->use_gpio_descriptors = true; in mtk_spi_probe()
1149 mdata->dev_comp = device_get_match_data(dev); in mtk_spi_probe()
1151 if (mdata->dev_comp->enhance_timing) in mtk_spi_probe()
1152 host->mode_bits |= SPI_CS_HIGH; in mtk_spi_probe()
1154 if (mdata->dev_comp->must_tx) in mtk_spi_probe()
1155 host->flags = SPI_CONTROLLER_MUST_TX; in mtk_spi_probe()
1156 if (mdata->dev_comp->ipm_design) in mtk_spi_probe()
1157 host->mode_bits |= SPI_LOOP | SPI_RX_DUAL | SPI_TX_DUAL | in mtk_spi_probe()
1160 if (mdata->dev_comp->ipm_design) { in mtk_spi_probe()
1161 mdata->dev = dev; in mtk_spi_probe()
1162 host->mem_ops = &mtk_spi_mem_ops; in mtk_spi_probe()
1163 init_completion(&mdata->spimem_done); in mtk_spi_probe()
1166 if (mdata->dev_comp->need_pad_sel) { in mtk_spi_probe()
1167 mdata->pad_num = of_property_count_u32_elems(dev->of_node, in mtk_spi_probe()
1168 "mediatek,pad-select"); in mtk_spi_probe()
1169 if (mdata->pad_num < 0) in mtk_spi_probe()
1170 return dev_err_probe(dev, -EINVAL, in mtk_spi_probe()
1171 "No 'mediatek,pad-select' property\n"); in mtk_spi_probe()
1173 mdata->pad_sel = devm_kmalloc_array(dev, mdata->pad_num, in mtk_spi_probe()
1175 if (!mdata->pad_sel) in mtk_spi_probe()
1176 return -ENOMEM; in mtk_spi_probe()
1178 for (i = 0; i < mdata->pad_num; i++) { in mtk_spi_probe()
1179 of_property_read_u32_index(dev->of_node, in mtk_spi_probe()
1180 "mediatek,pad-select", in mtk_spi_probe()
1181 i, &mdata->pad_sel[i]); in mtk_spi_probe()
1182 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) in mtk_spi_probe()
1183 return dev_err_probe(dev, -EINVAL, in mtk_spi_probe()
1184 "wrong pad-sel[%d]: %u\n", in mtk_spi_probe()
1185 i, mdata->pad_sel[i]); in mtk_spi_probe()
1190 mdata->base = devm_platform_ioremap_resource(pdev, 0); in mtk_spi_probe()
1191 if (IS_ERR(mdata->base)) in mtk_spi_probe()
1192 return PTR_ERR(mdata->base); in mtk_spi_probe()
1198 if (!dev->dma_mask) in mtk_spi_probe()
1199 dev->dma_mask = &dev->coherent_dma_mask; in mtk_spi_probe()
1201 if (mdata->dev_comp->ipm_design) in mtk_spi_probe()
1206 mdata->parent_clk = devm_clk_get(dev, "parent-clk"); in mtk_spi_probe()
1207 if (IS_ERR(mdata->parent_clk)) in mtk_spi_probe()
1208 return dev_err_probe(dev, PTR_ERR(mdata->parent_clk), in mtk_spi_probe()
1209 "failed to get parent-clk\n"); in mtk_spi_probe()
1211 mdata->sel_clk = devm_clk_get(dev, "sel-clk"); in mtk_spi_probe()
1212 if (IS_ERR(mdata->sel_clk)) in mtk_spi_probe()
1213 return dev_err_probe(dev, PTR_ERR(mdata->sel_clk), "failed to get sel-clk\n"); in mtk_spi_probe()
1215 mdata->spi_clk = devm_clk_get(dev, "spi-clk"); in mtk_spi_probe()
1216 if (IS_ERR(mdata->spi_clk)) in mtk_spi_probe()
1217 return dev_err_probe(dev, PTR_ERR(mdata->spi_clk), "failed to get spi-clk\n"); in mtk_spi_probe()
1219 mdata->spi_hclk = devm_clk_get_optional(dev, "hclk"); in mtk_spi_probe()
1220 if (IS_ERR(mdata->spi_hclk)) in mtk_spi_probe()
1221 return dev_err_probe(dev, PTR_ERR(mdata->spi_hclk), "failed to get hclk\n"); in mtk_spi_probe()
1223 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); in mtk_spi_probe()
1227 ret = clk_prepare_enable(mdata->spi_hclk); in mtk_spi_probe()
1231 ret = clk_prepare_enable(mdata->spi_clk); in mtk_spi_probe()
1233 clk_disable_unprepare(mdata->spi_hclk); in mtk_spi_probe()
1237 mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); in mtk_spi_probe()
1239 if (mdata->dev_comp->no_need_unprepare) { in mtk_spi_probe()
1240 clk_disable(mdata->spi_clk); in mtk_spi_probe()
1241 clk_disable(mdata->spi_hclk); in mtk_spi_probe()
1243 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_probe()
1244 clk_disable_unprepare(mdata->spi_hclk); in mtk_spi_probe()
1247 if (mdata->dev_comp->need_pad_sel) { in mtk_spi_probe()
1248 if (mdata->pad_num != host->num_chipselect) in mtk_spi_probe()
1249 return dev_err_probe(dev, -EINVAL, in mtk_spi_probe()
1251 mdata->pad_num, host->num_chipselect); in mtk_spi_probe()
1253 if (!host->cs_gpiods && host->num_chipselect > 1) in mtk_spi_probe()
1254 return dev_err_probe(dev, -EINVAL, in mtk_spi_probe()
1258 if (mdata->dev_comp->dma_ext) in mtk_spi_probe()
1290 if (mdata->use_spimem && !completion_done(&mdata->spimem_done)) in mtk_spi_remove()
1291 complete(&mdata->spimem_done); in mtk_spi_remove()
1293 ret = pm_runtime_get_sync(&pdev->dev); in mtk_spi_remove()
1295 dev_warn(&pdev->dev, "Failed to resume hardware (%pe)\n", ERR_PTR(ret)); in mtk_spi_remove()
1304 if (mdata->dev_comp->no_need_unprepare) { in mtk_spi_remove()
1305 clk_unprepare(mdata->spi_clk); in mtk_spi_remove()
1306 clk_unprepare(mdata->spi_hclk); in mtk_spi_remove()
1310 pm_runtime_put_noidle(&pdev->dev); in mtk_spi_remove()
1311 pm_runtime_disable(&pdev->dev); in mtk_spi_remove()
1326 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_suspend()
1327 clk_disable_unprepare(mdata->spi_hclk); in mtk_spi_suspend()
1344 ret = clk_prepare_enable(mdata->spi_clk); in mtk_spi_resume()
1350 ret = clk_prepare_enable(mdata->spi_hclk); in mtk_spi_resume()
1353 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_resume()
1360 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_resume()
1361 clk_disable_unprepare(mdata->spi_hclk); in mtk_spi_resume()
1374 if (mdata->dev_comp->no_need_unprepare) { in mtk_spi_runtime_suspend()
1375 clk_disable(mdata->spi_clk); in mtk_spi_runtime_suspend()
1376 clk_disable(mdata->spi_hclk); in mtk_spi_runtime_suspend()
1378 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_runtime_suspend()
1379 clk_disable_unprepare(mdata->spi_hclk); in mtk_spi_runtime_suspend()
1391 if (mdata->dev_comp->no_need_unprepare) { in mtk_spi_runtime_resume()
1392 ret = clk_enable(mdata->spi_clk); in mtk_spi_runtime_resume()
1397 ret = clk_enable(mdata->spi_hclk); in mtk_spi_runtime_resume()
1400 clk_disable(mdata->spi_clk); in mtk_spi_runtime_resume()
1404 ret = clk_prepare_enable(mdata->spi_clk); in mtk_spi_runtime_resume()
1410 ret = clk_prepare_enable(mdata->spi_hclk); in mtk_spi_runtime_resume()
1413 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_runtime_resume()
1430 .name = "mtk-spi",
1443 MODULE_ALIAS("platform:mtk-spi");