75 #define REG_CONTROL		(0x00)  macro
128 	u32 control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_disable()
132 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_disable()
163 	u32 control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_enable_ints()
166 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_enable_ints()
171 	u32 control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_disable_ints()
174 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_disable_ints()
211 	control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_set_xfer_size()
214 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_set_xfer_size()
255 	control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_set_framesize()
257 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_set_framesize()
262 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_set_framesize()
312 	u32 control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_init()
315 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_init()
331 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_init()
349 	control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_init()
354 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_init()
361 	control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_set_clk_gen()
368 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_set_clk_gen()
374 	u32 control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_set_mode()
397 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_set_mode()
402 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_set_mode()
405 	mchp_corespi_write(spi, REG_CONTROL, control);  in mchp_corespi_set_mode()