Lines Matching +full:echo +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
71 #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
142 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
191 return __raw_readl(spi->regbase + reg); in lantiq_ssc_readl()
197 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_writel()
203 u32 val = __raw_readl(spi->regbase + reg); in lantiq_ssc_maskl()
207 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_maskl()
212 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in tx_fifo_level()
215 return (fstat >> LTQ_SPI_FSTAT_TXFFL_S) & hwcfg->fifo_size_mask; in tx_fifo_level()
220 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in rx_fifo_level()
223 return (fstat >> LTQ_SPI_FSTAT_RXFFL_S) & hwcfg->fifo_size_mask; in rx_fifo_level()
228 return spi->tx_fifo_size - tx_fifo_level(spi); in tx_fifo_free()
233 u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S; in rx_fifo_reset()
277 * baudrate = -------------- in hw_setup_speed_hz()
280 spi_clk = clk_get_rate(spi->fpi_clk) / 2; in hw_setup_speed_hz()
285 brt = spi_clk / max_speed_hz - 1; in hw_setup_speed_hz()
290 dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n", in hw_setup_speed_hz()
301 /* CON.BM value = bits_per_word - 1 */ in hw_setup_bits_per_word()
302 bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S; in hw_setup_bits_per_word()
347 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in lantiq_ssc_hw_init()
367 hw_setup_bits_per_word(spi, spi->bits_per_word); in lantiq_ssc_hw_init()
384 lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | in lantiq_ssc_hw_init()
390 struct spi_controller *host = spidev->controller; in lantiq_ssc_setup()
395 /* GPIOs are used for CS */ in lantiq_ssc_setup()
399 dev_dbg(spi->dev, "using internal chipselect %u\n", cs); in lantiq_ssc_setup()
401 if (cs < spi->base_cs) { in lantiq_ssc_setup()
402 dev_err(spi->dev, in lantiq_ssc_setup()
403 "chipselect %i too small (min %i)\n", cs, spi->base_cs); in lantiq_ssc_setup()
404 return -EINVAL; in lantiq_ssc_setup()
408 gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S); in lantiq_ssc_setup()
411 if (spidev->mode & SPI_CS_HIGH) in lantiq_ssc_setup()
412 gpocon |= 1 << (cs - spi->base_cs); in lantiq_ssc_setup()
425 hw_setup_clock_mode(spi, message->spi->mode); in lantiq_ssc_prepare_message()
434 unsigned int speed_hz = t->speed_hz; in hw_setup_transfer()
435 unsigned int bits_per_word = t->bits_per_word; in hw_setup_transfer()
438 if (bits_per_word != spi->bits_per_word || in hw_setup_transfer()
439 speed_hz != spi->speed_hz) { in hw_setup_transfer()
445 spi->speed_hz = speed_hz; in hw_setup_transfer()
446 spi->bits_per_word = bits_per_word; in hw_setup_transfer()
451 if (t->tx_buf) in hw_setup_transfer()
456 if (t->rx_buf) in hw_setup_transfer()
469 flush_workqueue(spi->wq); in lantiq_ssc_unprepare_message()
486 spi->fdx_tx_level = 0; in tx_fifo_write()
487 while (spi->tx_todo && tx_free) { in tx_fifo_write()
488 switch (spi->bits_per_word) { in tx_fifo_write()
490 tx8 = spi->tx; in tx_fifo_write()
492 spi->tx_todo--; in tx_fifo_write()
493 spi->tx++; in tx_fifo_write()
496 tx16 = (u16 *) spi->tx; in tx_fifo_write()
498 spi->tx_todo -= 2; in tx_fifo_write()
499 spi->tx += 2; in tx_fifo_write()
502 tx32 = (u32 *) spi->tx; in tx_fifo_write()
504 spi->tx_todo -= 4; in tx_fifo_write()
505 spi->tx += 4; in tx_fifo_write()
514 tx_free--; in tx_fifo_write()
515 spi->fdx_tx_level++; in tx_fifo_write()
531 while (rx_fill != spi->fdx_tx_level) in rx_fifo_read_full_duplex()
537 switch (spi->bits_per_word) { in rx_fifo_read_full_duplex()
539 rx8 = spi->rx; in rx_fifo_read_full_duplex()
541 spi->rx_todo--; in rx_fifo_read_full_duplex()
542 spi->rx++; in rx_fifo_read_full_duplex()
545 rx16 = (u16 *) spi->rx; in rx_fifo_read_full_duplex()
547 spi->rx_todo -= 2; in rx_fifo_read_full_duplex()
548 spi->rx += 2; in rx_fifo_read_full_duplex()
551 rx32 = (u32 *) spi->rx; in rx_fifo_read_full_duplex()
553 spi->rx_todo -= 4; in rx_fifo_read_full_duplex()
554 spi->rx += 4; in rx_fifo_read_full_duplex()
561 rx_fill--; in rx_fifo_read_full_duplex()
573 * In RX-only mode the bits per word value is ignored by HW. A value in rx_fifo_read_half_duplex()
580 if (spi->rx_todo < 4) { in rx_fifo_read_half_duplex()
585 shift = (rxbv - 1) * 8; in rx_fifo_read_half_duplex()
586 rx8 = spi->rx; in rx_fifo_read_half_duplex()
590 rxbv--; in rx_fifo_read_half_duplex()
591 shift -= 8; in rx_fifo_read_half_duplex()
592 spi->rx_todo--; in rx_fifo_read_half_duplex()
593 spi->rx++; in rx_fifo_read_half_duplex()
597 rx32 = (u32 *) spi->rx; in rx_fifo_read_half_duplex()
600 spi->rx_todo -= 4; in rx_fifo_read_half_duplex()
601 spi->rx += 4; in rx_fifo_read_half_duplex()
603 rx_fill--; in rx_fifo_read_half_duplex()
616 rxreq = spi->rx_todo; in rx_request()
617 rxreq_max = spi->rx_fifo_size * 4; in rx_request()
627 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in lantiq_ssc_xmit_interrupt()
628 u32 val = lantiq_ssc_readl(spi, hwcfg->irncr); in lantiq_ssc_xmit_interrupt()
630 spin_lock(&spi->lock); in lantiq_ssc_xmit_interrupt()
631 if (hwcfg->irq_ack) in lantiq_ssc_xmit_interrupt()
632 lantiq_ssc_writel(spi, val, hwcfg->irncr); in lantiq_ssc_xmit_interrupt()
634 if (spi->tx) { in lantiq_ssc_xmit_interrupt()
635 if (spi->rx && spi->rx_todo) in lantiq_ssc_xmit_interrupt()
638 if (spi->tx_todo) in lantiq_ssc_xmit_interrupt()
642 } else if (spi->rx) { in lantiq_ssc_xmit_interrupt()
643 if (spi->rx_todo) { in lantiq_ssc_xmit_interrupt()
646 if (spi->rx_todo) in lantiq_ssc_xmit_interrupt()
655 spin_unlock(&spi->lock); in lantiq_ssc_xmit_interrupt()
659 queue_work(spi->wq, &spi->work); in lantiq_ssc_xmit_interrupt()
660 spin_unlock(&spi->lock); in lantiq_ssc_xmit_interrupt()
668 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in lantiq_ssc_err_interrupt()
670 u32 val = lantiq_ssc_readl(spi, hwcfg->irncr); in lantiq_ssc_err_interrupt()
675 spin_lock(&spi->lock); in lantiq_ssc_err_interrupt()
676 if (hwcfg->irq_ack) in lantiq_ssc_err_interrupt()
677 lantiq_ssc_writel(spi, val, hwcfg->irncr); in lantiq_ssc_err_interrupt()
680 dev_err(spi->dev, "receive underflow error\n"); in lantiq_ssc_err_interrupt()
682 dev_err(spi->dev, "transmit underflow error\n"); in lantiq_ssc_err_interrupt()
684 dev_err(spi->dev, "abort error\n"); in lantiq_ssc_err_interrupt()
686 dev_err(spi->dev, "receive overflow error\n"); in lantiq_ssc_err_interrupt()
688 dev_err(spi->dev, "transmit overflow error\n"); in lantiq_ssc_err_interrupt()
690 dev_err(spi->dev, "mode error\n"); in lantiq_ssc_err_interrupt()
696 if (spi->host->cur_msg) in lantiq_ssc_err_interrupt()
697 spi->host->cur_msg->status = -EIO; in lantiq_ssc_err_interrupt()
698 queue_work(spi->wq, &spi->work); in lantiq_ssc_err_interrupt()
699 spin_unlock(&spi->lock); in lantiq_ssc_err_interrupt()
707 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in intel_lgm_ssc_isr()
708 u32 val = lantiq_ssc_readl(spi, hwcfg->irncr); in intel_lgm_ssc_isr()
716 if ((val & hwcfg->irnen_t) || (val & hwcfg->irnen_r)) in intel_lgm_ssc_isr()
727 spin_lock_irqsave(&spi->lock, flags); in transfer_start()
729 spi->tx = t->tx_buf; in transfer_start()
730 spi->rx = t->rx_buf; in transfer_start()
732 if (t->tx_buf) { in transfer_start()
733 spi->tx_todo = t->len; in transfer_start()
739 if (spi->rx) { in transfer_start()
740 spi->rx_todo = t->len; in transfer_start()
742 /* start shift clock in RX-only mode */ in transfer_start()
743 if (!spi->tx) in transfer_start()
747 spin_unlock_irqrestore(&spi->lock, flags); in transfer_start()
749 return t->len; in transfer_start()
767 do_div(timeout, spi->speed_hz); in lantiq_ssc_bussy_work()
775 spi_finalize_current_transfer(spi->host); in lantiq_ssc_bussy_work()
782 if (spi->host->cur_msg) in lantiq_ssc_bussy_work()
783 spi->host->cur_msg->status = -EIO; in lantiq_ssc_bussy_work()
784 spi_finalize_current_transfer(spi->host); in lantiq_ssc_bussy_work()
799 struct lantiq_ssc_spi *spi = spi_controller_get_devdata(spidev->controller); in lantiq_ssc_set_cs()
803 if (!!(spidev->mode & SPI_CS_HIGH) == enable) in lantiq_ssc_set_cs()
804 fgpo = (1 << (cs - spi->base_cs)); in lantiq_ssc_set_cs()
806 fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S)); in lantiq_ssc_set_cs()
830 return devm_request_irq(&pdev->dev, irq, intel_lgm_ssc_isr, 0, "spi", spi); in intel_lgm_cfg_irq()
841 err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_xmit_interrupt, in lantiq_cfg_irq()
850 err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_xmit_interrupt, in lantiq_cfg_irq()
860 err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_err_interrupt, in lantiq_cfg_irq()
896 { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
897 { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
898 { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
899 { .compatible = "intel,lgm-spi", .data = &intel_ssc_lgm, },
906 struct device *dev = &pdev->dev; in lantiq_ssc_probe()
918 return -ENOMEM; in lantiq_ssc_probe()
921 spi->host = host; in lantiq_ssc_probe()
922 spi->dev = dev; in lantiq_ssc_probe()
923 spi->hwcfg = hwcfg; in lantiq_ssc_probe()
925 spi->regbase = devm_platform_ioremap_resource(pdev, 0); in lantiq_ssc_probe()
926 if (IS_ERR(spi->regbase)) { in lantiq_ssc_probe()
927 err = PTR_ERR(spi->regbase); in lantiq_ssc_probe()
931 err = hwcfg->cfg_irq(pdev, spi); in lantiq_ssc_probe()
935 spi->spi_clk = devm_clk_get_enabled(dev, "gate"); in lantiq_ssc_probe()
936 if (IS_ERR(spi->spi_clk)) { in lantiq_ssc_probe()
937 err = PTR_ERR(spi->spi_clk); in lantiq_ssc_probe()
946 spi->fpi_clk = clk_get_fpi(); in lantiq_ssc_probe()
948 spi->fpi_clk = clk_get(dev, "freq"); in lantiq_ssc_probe()
950 if (IS_ERR(spi->fpi_clk)) { in lantiq_ssc_probe()
951 err = PTR_ERR(spi->fpi_clk); in lantiq_ssc_probe()
956 of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); in lantiq_ssc_probe()
958 spi->base_cs = 1; in lantiq_ssc_probe()
959 of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs); in lantiq_ssc_probe()
961 spin_lock_init(&spi->lock); in lantiq_ssc_probe()
962 spi->bits_per_word = 8; in lantiq_ssc_probe()
963 spi->speed_hz = 0; in lantiq_ssc_probe()
965 host->dev.of_node = pdev->dev.of_node; in lantiq_ssc_probe()
966 host->num_chipselect = num_cs; in lantiq_ssc_probe()
967 host->use_gpio_descriptors = true; in lantiq_ssc_probe()
968 host->setup = lantiq_ssc_setup; in lantiq_ssc_probe()
969 host->set_cs = lantiq_ssc_set_cs; in lantiq_ssc_probe()
970 host->handle_err = lantiq_ssc_handle_err; in lantiq_ssc_probe()
971 host->prepare_message = lantiq_ssc_prepare_message; in lantiq_ssc_probe()
972 host->unprepare_message = lantiq_ssc_unprepare_message; in lantiq_ssc_probe()
973 host->transfer_one = lantiq_ssc_transfer_one; in lantiq_ssc_probe()
974 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH | in lantiq_ssc_probe()
976 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) | in lantiq_ssc_probe()
979 spi->wq = alloc_ordered_workqueue(dev_name(dev), WQ_MEM_RECLAIM); in lantiq_ssc_probe()
980 if (!spi->wq) { in lantiq_ssc_probe()
981 err = -ENOMEM; in lantiq_ssc_probe()
984 INIT_WORK(&spi->work, lantiq_ssc_bussy_work); in lantiq_ssc_probe()
987 spi->tx_fifo_size = (id >> LTQ_SPI_ID_TXFS_S) & hwcfg->fifo_size_mask; in lantiq_ssc_probe()
988 spi->rx_fifo_size = (id >> LTQ_SPI_ID_RXFS_S) & hwcfg->fifo_size_mask; in lantiq_ssc_probe()
996 revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma); in lantiq_ssc_probe()
1007 destroy_workqueue(spi->wq); in lantiq_ssc_probe()
1009 clk_put(spi->fpi_clk); in lantiq_ssc_probe()
1026 destroy_workqueue(spi->wq); in lantiq_ssc_remove()
1027 clk_put(spi->fpi_clk); in lantiq_ssc_remove()
1034 .name = "spi-lantiq-ssc",
1042 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
1044 MODULE_ALIAS("platform:spi-lantiq-ssc");