68 /* Offsets are from @ispi->sregs */
145  * @sregs: Start of software sequencer registers
165 	void __iomem *sregs;  member
221 	if (ispi->sregs) {  in intel_spi_dump_regs()
222 		value = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_dump_regs()
225 			readl(ispi->sregs + PREOP_OPTYPE));  in intel_spi_dump_regs()
227 			readl(ispi->sregs + OPMENU0));  in intel_spi_dump_regs()
229 			readl(ispi->sregs + OPMENU1));  in intel_spi_dump_regs()
326 	return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,  in intel_spi_wait_sw_busy()
353 	writel(opcode, ispi->sregs + OPMENU0);  in intel_spi_opcode_index()
354 	preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_opcode_index()
355 	writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);  in intel_spi_opcode_index()
421 			preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_sw_cycle()
437 	writel(val, ispi->sregs + SSFSTS_CTL);  in intel_spi_sw_cycle()
443 	status = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_sw_cycle()
508 		preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_write_reg()
512 			writel(opcode, ispi->sregs + PREOP_OPTYPE);  in intel_spi_write_reg()
1081 		ispi->sregs = ispi->base + BYT_SSFSTS_CTL;  in intel_spi_init()
1089 		ispi->sregs = ispi->base + LPT_SSFSTS_CTL;  in intel_spi_init()
1097 		ispi->sregs = ispi->base + BXT_SSFSTS_CTL;  in intel_spi_init()
1105 		ispi->sregs = NULL;  in intel_spi_init()
1148 	if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) {  in intel_spi_init()
1160 		val = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_init()
1162 		writel(val, ispi->sregs + SSFSTS_CTL);  in intel_spi_init()
1169 	if (ispi->locked && ispi->sregs) {  in intel_spi_init()
1175 		opmenu0 = readl(ispi->sregs + OPMENU0);  in intel_spi_init()
1176 		opmenu1 = readl(ispi->sregs + OPMENU1);  in intel_spi_init()