Lines Matching +full:software +full:- +full:locked
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016 - 2022, Intel Corporation
13 #include <linux/mtd/spi-nor.h>
17 #include <linux/spi/spi-mem.h>
19 #include "spi-intel.h"
21 /* Offsets are from @ispi->base */
60 /* Offset is from @ispi->pregs */
68 /* Offsets are from @ispi->sregs */
140 * struct intel_spi - Driver private data
145 * @sregs: Start of software sequencer registers
150 * @locked: Is SPI setting locked
152 * @bios_locked: Is BIOS region locked
170 bool locked; member
198 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG)); in intel_spi_dump_regs()
200 value = readl(ispi->base + HSFSTS_CTL); in intel_spi_dump_regs()
201 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value); in intel_spi_dump_regs()
203 dev_dbg(ispi->dev, "-> Locked\n"); in intel_spi_dump_regs()
205 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR)); in intel_spi_dump_regs()
206 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK)); in intel_spi_dump_regs()
209 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n", in intel_spi_dump_regs()
210 i, readl(ispi->base + FDATA(i))); in intel_spi_dump_regs()
212 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC)); in intel_spi_dump_regs()
214 for (i = 0; i < ispi->nregions; i++) in intel_spi_dump_regs()
215 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i, in intel_spi_dump_regs()
216 readl(ispi->base + FREG(i))); in intel_spi_dump_regs()
217 for (i = 0; i < ispi->pr_num; i++) in intel_spi_dump_regs()
218 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i, in intel_spi_dump_regs()
219 readl(ispi->pregs + PR(i))); in intel_spi_dump_regs()
221 if (ispi->sregs) { in intel_spi_dump_regs()
222 value = readl(ispi->sregs + SSFSTS_CTL); in intel_spi_dump_regs()
223 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value); in intel_spi_dump_regs()
224 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n", in intel_spi_dump_regs()
225 readl(ispi->sregs + PREOP_OPTYPE)); in intel_spi_dump_regs()
226 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", in intel_spi_dump_regs()
227 readl(ispi->sregs + OPMENU0)); in intel_spi_dump_regs()
228 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", in intel_spi_dump_regs()
229 readl(ispi->sregs + OPMENU1)); in intel_spi_dump_regs()
232 dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC)); in intel_spi_dump_regs()
233 dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC)); in intel_spi_dump_regs()
235 dev_dbg(ispi->dev, "Protected regions:\n"); in intel_spi_dump_regs()
236 for (i = 0; i < ispi->pr_num; i++) { in intel_spi_dump_regs()
239 value = readl(ispi->pregs + PR(i)); in intel_spi_dump_regs()
246 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n", in intel_spi_dump_regs()
251 dev_dbg(ispi->dev, "Flash regions:\n"); in intel_spi_dump_regs()
252 for (i = 0; i < ispi->nregions; i++) { in intel_spi_dump_regs()
255 region = readl(ispi->base + FREG(i)); in intel_spi_dump_regs()
260 dev_dbg(ispi->dev, " %02d disabled\n", i); in intel_spi_dump_regs()
262 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n", in intel_spi_dump_regs()
266 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n", in intel_spi_dump_regs()
267 ispi->swseq_reg ? 'S' : 'H'); in intel_spi_dump_regs()
268 dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n", in intel_spi_dump_regs()
269 ispi->swseq_erase ? 'S' : 'H'); in intel_spi_dump_regs()
279 return -EINVAL; in intel_spi_read_block()
283 memcpy_fromio(buf, ispi->base + FDATA(i), bytes); in intel_spi_read_block()
284 size -= bytes; in intel_spi_read_block()
300 return -EINVAL; in intel_spi_write_block()
304 memcpy_toio(ispi->base + FDATA(i), buf, bytes); in intel_spi_write_block()
305 size -= bytes; in intel_spi_write_block()
317 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val, in intel_spi_wait_hw_busy()
326 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val, in intel_spi_wait_sw_busy()
333 if (!ispi->info->set_writeable) in intel_spi_set_writeable()
336 return ispi->info->set_writeable(ispi->base, ispi->info->data); in intel_spi_set_writeable()
344 if (ispi->locked) { in intel_spi_opcode_index()
345 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) in intel_spi_opcode_index()
346 if (ispi->opcodes[i] == opcode) in intel_spi_opcode_index()
349 return -EINVAL; in intel_spi_opcode_index()
353 writel(opcode, ispi->sregs + OPMENU0); in intel_spi_opcode_index()
354 preop = readw(ispi->sregs + PREOP_OPTYPE); in intel_spi_opcode_index()
355 writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE); in intel_spi_opcode_index()
366 if (!iop->replacement_op) in intel_spi_hw_cycle()
367 return -EINVAL; in intel_spi_hw_cycle()
369 val = readl(ispi->base + HSFSTS_CTL); in intel_spi_hw_cycle()
371 val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT; in intel_spi_hw_cycle()
374 val |= iop->replacement_op; in intel_spi_hw_cycle()
375 writel(val, ispi->base + HSFSTS_CTL); in intel_spi_hw_cycle()
381 status = readl(ispi->base + HSFSTS_CTL); in intel_spi_hw_cycle()
383 return -EIO; in intel_spi_hw_cycle()
385 return -EACCES; in intel_spi_hw_cycle()
405 atomic_preopcode = ispi->atomic_preopcode; in intel_spi_sw_cycle()
406 ispi->atomic_preopcode = 0; in intel_spi_sw_cycle()
410 val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS; in intel_spi_sw_cycle()
421 preop = readw(ispi->sregs + PREOP_OPTYPE); in intel_spi_sw_cycle()
427 return -EINVAL; in intel_spi_sw_cycle()
434 return -EINVAL; in intel_spi_sw_cycle()
437 writel(val, ispi->sregs + SSFSTS_CTL); in intel_spi_sw_cycle()
443 status = readl(ispi->sregs + SSFSTS_CTL); in intel_spi_sw_cycle()
445 return -EIO; in intel_spi_sw_cycle()
447 return -EACCES; in intel_spi_sw_cycle()
458 return (spi_get_chipselect(mem->spi, 0) == 1) ? ispi->chip0_size : 0; in intel_spi_chip_addr()
465 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; in intel_spi_read_reg()
466 size_t nbytes = op->data.nbytes; in intel_spi_read_reg()
467 u8 opcode = op->cmd.opcode; in intel_spi_read_reg()
470 writel(addr, ispi->base + FADDR); in intel_spi_read_reg()
472 if (ispi->swseq_reg) in intel_spi_read_reg()
481 return intel_spi_read_block(ispi, op->data.buf.in, nbytes); in intel_spi_read_reg()
488 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; in intel_spi_write_reg()
489 size_t nbytes = op->data.nbytes; in intel_spi_write_reg()
490 u8 opcode = op->cmd.opcode; in intel_spi_write_reg()
496 * controller is not locked, program the opcode to the PREOP in intel_spi_write_reg()
505 if (!ispi->swseq_reg) in intel_spi_write_reg()
508 preop = readw(ispi->sregs + PREOP_OPTYPE); in intel_spi_write_reg()
510 if (ispi->locked) in intel_spi_write_reg()
511 return -EINVAL; in intel_spi_write_reg()
512 writel(opcode, ispi->sregs + PREOP_OPTYPE); in intel_spi_write_reg()
519 ispi->atomic_preopcode = opcode; in intel_spi_write_reg()
532 writel(addr, ispi->base + FADDR); in intel_spi_write_reg()
535 ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes); in intel_spi_write_reg()
539 if (ispi->swseq_reg) in intel_spi_write_reg()
549 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; in intel_spi_read()
550 size_t block_size, nbytes = op->data.nbytes; in intel_spi_read()
551 void *read_buf = op->data.buf.in; in intel_spi_read()
559 if (WARN_ON_ONCE(ispi->atomic_preopcode)) in intel_spi_read()
560 ispi->atomic_preopcode = 0; in intel_spi_read()
567 round_up(addr + 1, SZ_4K)) - addr; in intel_spi_read()
569 writel(addr, ispi->base + FADDR); in intel_spi_read()
571 val = readl(ispi->base + HSFSTS_CTL); in intel_spi_read()
574 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; in intel_spi_read()
577 writel(val, ispi->base + HSFSTS_CTL); in intel_spi_read()
583 status = readl(ispi->base + HSFSTS_CTL); in intel_spi_read()
585 ret = -EIO; in intel_spi_read()
587 ret = -EACCES; in intel_spi_read()
590 dev_err(ispi->dev, "read error: %x: %#x\n", addr, status); in intel_spi_read()
598 nbytes -= block_size; in intel_spi_read()
610 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; in intel_spi_write()
611 size_t block_size, nbytes = op->data.nbytes; in intel_spi_write()
612 const void *write_buf = op->data.buf.out; in intel_spi_write()
617 ispi->atomic_preopcode = 0; in intel_spi_write()
624 round_up(addr + 1, SZ_4K)) - addr; in intel_spi_write()
626 writel(addr, ispi->base + FADDR); in intel_spi_write()
628 val = readl(ispi->base + HSFSTS_CTL); in intel_spi_write()
631 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; in intel_spi_write()
636 dev_err(ispi->dev, "failed to write block\n"); in intel_spi_write()
642 writel(val, ispi->base + HSFSTS_CTL); in intel_spi_write()
646 dev_err(ispi->dev, "timeout\n"); in intel_spi_write()
650 status = readl(ispi->base + HSFSTS_CTL); in intel_spi_write()
652 ret = -EIO; in intel_spi_write()
654 ret = -EACCES; in intel_spi_write()
657 dev_err(ispi->dev, "write error: %x: %#x\n", addr, status); in intel_spi_write()
661 nbytes -= block_size; in intel_spi_write()
673 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; in intel_spi_erase()
674 u8 opcode = op->cmd.opcode; in intel_spi_erase()
678 writel(addr, ispi->base + FADDR); in intel_spi_erase()
680 if (ispi->swseq_erase) in intel_spi_erase()
685 ispi->atomic_preopcode = 0; in intel_spi_erase()
687 val = readl(ispi->base + HSFSTS_CTL); in intel_spi_erase()
691 val |= iop->replacement_op; in intel_spi_erase()
692 writel(val, ispi->base + HSFSTS_CTL); in intel_spi_erase()
698 status = readl(ispi->base + HSFSTS_CTL); in intel_spi_erase()
700 return -EIO; in intel_spi_erase()
702 return -EACCES; in intel_spi_erase()
709 op->data.nbytes = clamp_val(op->data.nbytes, 0, INTEL_SPI_FIFO_SZ); in intel_spi_adjust_op_size()
716 if (iop->mem_op.cmd.nbytes != op->cmd.nbytes || in intel_spi_cmp_mem_op()
717 iop->mem_op.cmd.buswidth != op->cmd.buswidth || in intel_spi_cmp_mem_op()
718 iop->mem_op.cmd.dtr != op->cmd.dtr) in intel_spi_cmp_mem_op()
721 if (iop->mem_op.addr.nbytes != op->addr.nbytes || in intel_spi_cmp_mem_op()
722 iop->mem_op.addr.dtr != op->addr.dtr) in intel_spi_cmp_mem_op()
725 if (iop->mem_op.data.dir != op->data.dir || in intel_spi_cmp_mem_op()
726 iop->mem_op.data.dtr != op->data.dtr) in intel_spi_cmp_mem_op()
729 if (iop->mem_op.data.dir != SPI_MEM_NO_DATA) { in intel_spi_cmp_mem_op()
730 if (iop->mem_op.data.buswidth != op->data.buswidth) in intel_spi_cmp_mem_op()
742 for (iop = ispi->mem_ops; iop->mem_op.cmd.opcode; iop++) { in intel_spi_match_mem_op()
743 if (iop->mem_op.cmd.opcode == op->cmd.opcode && in intel_spi_match_mem_op()
754 struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller); in intel_spi_supports_mem_op()
759 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode); in intel_spi_supports_mem_op()
764 * For software sequencer check that the opcode is actually in intel_spi_supports_mem_op()
765 * present in the opmenu if it is locked. in intel_spi_supports_mem_op()
767 if (ispi->swseq_reg && ispi->locked) { in intel_spi_supports_mem_op()
770 /* Check if it is in the locked opcodes list */ in intel_spi_supports_mem_op()
771 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) { in intel_spi_supports_mem_op()
772 if (ispi->opcodes[i] == op->cmd.opcode) in intel_spi_supports_mem_op()
776 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode); in intel_spi_supports_mem_op()
785 struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller); in intel_spi_exec_mem_op()
790 return -EOPNOTSUPP; in intel_spi_exec_mem_op()
792 return iop->exec_op(ispi, mem, iop, op); in intel_spi_exec_mem_op()
797 const struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller); in intel_spi_get_name()
803 return dev_name(ispi->dev); in intel_spi_get_name()
808 struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller); in intel_spi_dirmap_create()
811 iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl); in intel_spi_dirmap_create()
813 return -EOPNOTSUPP; in intel_spi_dirmap_create()
815 desc->priv = (void *)iop; in intel_spi_dirmap_create()
822 struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller); in intel_spi_dirmap_read()
823 const struct intel_spi_mem_op *iop = desc->priv; in intel_spi_dirmap_read()
824 struct spi_mem_op op = desc->info.op_tmpl; in intel_spi_dirmap_read()
832 ret = iop->exec_op(ispi, desc->mem, iop, &op); in intel_spi_dirmap_read()
839 struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller); in intel_spi_dirmap_write()
840 const struct intel_spi_mem_op *iop = desc->priv; in intel_spi_dirmap_write()
841 struct spi_mem_op op = desc->info.op_tmpl; in intel_spi_dirmap_write()
848 ret = iop->exec_op(ispi, desc->mem, iop, &op); in intel_spi_dirmap_write()
983 /* Read with 4-byte address opcode */ \
996 /* Fast read with 4-byte address opcode */ \
1079 switch (ispi->info->type) { in intel_spi_init()
1081 ispi->sregs = ispi->base + BYT_SSFSTS_CTL; in intel_spi_init()
1082 ispi->pregs = ispi->base + BYT_PR; in intel_spi_init()
1083 ispi->nregions = BYT_FREG_NUM; in intel_spi_init()
1084 ispi->pr_num = BYT_PR_NUM; in intel_spi_init()
1085 ispi->swseq_reg = true; in intel_spi_init()
1089 ispi->sregs = ispi->base + LPT_SSFSTS_CTL; in intel_spi_init()
1090 ispi->pregs = ispi->base + LPT_PR; in intel_spi_init()
1091 ispi->nregions = LPT_FREG_NUM; in intel_spi_init()
1092 ispi->pr_num = LPT_PR_NUM; in intel_spi_init()
1093 ispi->swseq_reg = true; in intel_spi_init()
1097 ispi->sregs = ispi->base + BXT_SSFSTS_CTL; in intel_spi_init()
1098 ispi->pregs = ispi->base + BXT_PR; in intel_spi_init()
1099 ispi->nregions = BXT_FREG_NUM; in intel_spi_init()
1100 ispi->pr_num = BXT_PR_NUM; in intel_spi_init()
1105 ispi->sregs = NULL; in intel_spi_init()
1106 ispi->pregs = ispi->base + CNL_PR; in intel_spi_init()
1107 ispi->nregions = CNL_FREG_NUM; in intel_spi_init()
1108 ispi->pr_num = CNL_PR_NUM; in intel_spi_init()
1113 return -EINVAL; in intel_spi_init()
1116 ispi->bios_locked = true; in intel_spi_init()
1120 ispi->bios_locked = false; in intel_spi_init()
1122 dev_warn(ispi->dev, "can't disable chip write protection\n"); in intel_spi_init()
1126 val = readl(ispi->base + HSFSTS_CTL); in intel_spi_init()
1128 writel(val, ispi->base + HSFSTS_CTL); in intel_spi_init()
1138 lvscc = readl(ispi->base + LVSCC); in intel_spi_init()
1139 uvscc = readl(ispi->base + UVSCC); in intel_spi_init()
1141 ispi->swseq_erase = true; in intel_spi_init()
1143 if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase) in intel_spi_init()
1148 if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) { in intel_spi_init()
1149 dev_err(ispi->dev, "software sequencer not supported, but required\n"); in intel_spi_init()
1150 return -EINVAL; in intel_spi_init()
1156 * using software sequencer. in intel_spi_init()
1158 if (ispi->swseq_reg) { in intel_spi_init()
1160 val = readl(ispi->sregs + SSFSTS_CTL); in intel_spi_init()
1162 writel(val, ispi->sregs + SSFSTS_CTL); in intel_spi_init()
1166 val = readl(ispi->base + HSFSTS_CTL); in intel_spi_init()
1167 ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN); in intel_spi_init()
1169 if (ispi->locked && ispi->sregs) { in intel_spi_init()
1175 opmenu0 = readl(ispi->sregs + OPMENU0); in intel_spi_init()
1176 opmenu1 = readl(ispi->sregs + OPMENU1); in intel_spi_init()
1179 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) { in intel_spi_init()
1180 ispi->opcodes[i] = opmenu0 >> i * 8; in intel_spi_init()
1181 ispi->opcodes[i + 4] = opmenu1 >> i * 8; in intel_spi_init()
1187 dev_dbg(ispi->dev, "Using erase_64k memory operations"); in intel_spi_init()
1188 ispi->mem_ops = erase_64k_mem_ops; in intel_spi_init()
1190 dev_dbg(ispi->dev, "Using generic memory operations"); in intel_spi_init()
1191 ispi->mem_ops = generic_mem_ops; in intel_spi_init()
1203 for (i = 0; i < ispi->pr_num; i++) { in intel_spi_is_protected()
1206 pr_value = readl(ispi->pregs + PR(i)); in intel_spi_is_protected()
1233 part->size = 4096; in intel_spi_fill_partition()
1234 part->name = "BIOS"; in intel_spi_fill_partition()
1240 for (i = 1; i < ispi->nregions; i++) { in intel_spi_fill_partition()
1243 region = readl(ispi->base + FREG(i)); in intel_spi_fill_partition()
1252 * whole partition read-only to be on the safe side. in intel_spi_fill_partition()
1258 part->mask_flags |= MTD_WRITEABLE; in intel_spi_fill_partition()
1259 ispi->protected = true; in intel_spi_fill_partition()
1263 if (end > part->size) in intel_spi_fill_partition()
1264 part->size = end; in intel_spi_fill_partition()
1271 if (ispi->chip0_size && part->size > ispi->chip0_size) in intel_spi_fill_partition()
1272 part->size = MTDPART_SIZ_FULL; in intel_spi_fill_partition()
1291 dev_warn(ispi->dev, "failed to read descriptor\n"); in intel_spi_read_desc()
1295 dev_dbg(ispi->dev, "FLVALSIG=0x%08x\n", buf[0]); in intel_spi_read_desc()
1296 dev_dbg(ispi->dev, "FLMAP0=0x%08x\n", buf[1]); in intel_spi_read_desc()
1299 dev_warn(ispi->dev, "descriptor signature not valid\n"); in intel_spi_read_desc()
1300 return -ENODEV; in intel_spi_read_desc()
1304 dev_dbg(ispi->dev, "FCBA=%#x\n", fcba); in intel_spi_read_desc()
1312 dev_warn(ispi->dev, "failed to read FLCOMP\n"); in intel_spi_read_desc()
1313 return -ENODEV; in intel_spi_read_desc()
1316 dev_dbg(ispi->dev, "FLCOMP=0x%08x\n", flcomp); in intel_spi_read_desc()
1320 ispi->chip0_size = SZ_512K; in intel_spi_read_desc()
1323 ispi->chip0_size = SZ_1M; in intel_spi_read_desc()
1326 ispi->chip0_size = SZ_2M; in intel_spi_read_desc()
1329 ispi->chip0_size = SZ_4M; in intel_spi_read_desc()
1332 ispi->chip0_size = SZ_8M; in intel_spi_read_desc()
1335 ispi->chip0_size = SZ_16M; in intel_spi_read_desc()
1338 ispi->chip0_size = SZ_32M; in intel_spi_read_desc()
1341 ispi->chip0_size = SZ_64M; in intel_spi_read_desc()
1344 return -EINVAL; in intel_spi_read_desc()
1347 dev_dbg(ispi->dev, "chip0 size %zd KB\n", ispi->chip0_size / SZ_1K); in intel_spi_read_desc()
1351 ispi->host->num_chipselect = 1; in intel_spi_read_desc()
1353 ispi->host->num_chipselect = 2; in intel_spi_read_desc()
1355 return -EINVAL; in intel_spi_read_desc()
1357 dev_dbg(ispi->dev, "%u flash components found\n", in intel_spi_read_desc()
1358 ispi->host->num_chipselect); in intel_spi_read_desc()
1373 pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL); in intel_spi_populate_chip()
1375 return -ENOMEM; in intel_spi_populate_chip()
1377 pdata->nr_parts = 1; in intel_spi_populate_chip()
1378 pdata->parts = devm_kcalloc(ispi->dev, pdata->nr_parts, in intel_spi_populate_chip()
1379 sizeof(*pdata->parts), GFP_KERNEL); in intel_spi_populate_chip()
1380 if (!pdata->parts) in intel_spi_populate_chip()
1381 return -ENOMEM; in intel_spi_populate_chip()
1383 intel_spi_fill_partition(ispi, pdata->parts); in intel_spi_populate_chip()
1386 snprintf(chip.modalias, 8, "spi-nor"); in intel_spi_populate_chip()
1389 if (!spi_new_device(ispi->host, &chip)) in intel_spi_populate_chip()
1390 return -ENODEV; in intel_spi_populate_chip()
1393 if (ispi->host->num_chipselect < 2) in intel_spi_populate_chip()
1396 pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL); in intel_spi_populate_chip()
1398 return -ENOMEM; in intel_spi_populate_chip()
1400 pdata->name = devm_kasprintf(ispi->dev, GFP_KERNEL, "%s-chip1", in intel_spi_populate_chip()
1401 dev_name(ispi->dev)); in intel_spi_populate_chip()
1402 if (!pdata->name) in intel_spi_populate_chip()
1403 return -ENOMEM; in intel_spi_populate_chip()
1405 pdata->nr_parts = 1; in intel_spi_populate_chip()
1406 parts = devm_kcalloc(ispi->dev, pdata->nr_parts, sizeof(*parts), in intel_spi_populate_chip()
1409 return -ENOMEM; in intel_spi_populate_chip()
1413 pdata->parts = parts; in intel_spi_populate_chip()
1418 if (!spi_new_device(ispi->host, &chip)) in intel_spi_populate_chip()
1419 return -ENODEV; in intel_spi_populate_chip()
1428 return sysfs_emit(buf, "%d\n", ispi->protected); in intel_spi_protected_show()
1437 return sysfs_emit(buf, "%d\n", ispi->locked); in intel_spi_locked_show()
1446 return sysfs_emit(buf, "%d\n", ispi->bios_locked); in intel_spi_bios_locked_show()
1468 * intel_spi_probe() - Probe the Intel SPI flash controller
1485 return -ENOMEM; in intel_spi_probe()
1487 host->mem_ops = &intel_spi_mem_ops; in intel_spi_probe()
1491 ispi->base = devm_ioremap_resource(dev, mem); in intel_spi_probe()
1492 if (IS_ERR(ispi->base)) in intel_spi_probe()
1493 return PTR_ERR(ispi->base); in intel_spi_probe()
1495 ispi->dev = dev; in intel_spi_probe()
1496 ispi->host = host; in intel_spi_probe()
1497 ispi->info = info; in intel_spi_probe()