1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2016 - 2022, Intel Corporation
13 #include <linux/mtd/spi-nor.h>
17 #include <linux/spi/spi-mem.h>
19 #include "spi-intel.h"
21 /* Offsets are from @ispi->base */
31 /* HW sequencer opcodes */
60 /* Offset is from @ispi->pregs */
68 /* Offsets are from @ispi->sregs */
140  * struct intel_spi - Driver private data
145  * @sregs: Start of software sequencer registers
153  * @swseq_reg: Use SW sequencer in register reads/writes
154  * @swseq_erase: Use SW sequencer in erase operation
196 	"Do not block SPI flash chip write access even if it is write-protected (default=0)");
203 	dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));  in intel_spi_dump_regs()
205 	value = readl(ispi->base + HSFSTS_CTL);  in intel_spi_dump_regs()
206 	dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);  in intel_spi_dump_regs()
208 		dev_dbg(ispi->dev, "-> Locked\n");  in intel_spi_dump_regs()
210 	dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));  in intel_spi_dump_regs()
211 	dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));  in intel_spi_dump_regs()
214 		dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",  in intel_spi_dump_regs()
215 			i, readl(ispi->base + FDATA(i)));  in intel_spi_dump_regs()
217 	dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));  in intel_spi_dump_regs()
219 	for (i = 0; i < ispi->nregions; i++)  in intel_spi_dump_regs()
220 		dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,  in intel_spi_dump_regs()
221 			readl(ispi->base + FREG(i)));  in intel_spi_dump_regs()
222 	for (i = 0; i < ispi->pr_num; i++)  in intel_spi_dump_regs()
223 		dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,  in intel_spi_dump_regs()
224 			readl(ispi->pregs + PR(i)));  in intel_spi_dump_regs()
226 	if (ispi->sregs) {  in intel_spi_dump_regs()
227 		value = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_dump_regs()
228 		dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);  in intel_spi_dump_regs()
229 		dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",  in intel_spi_dump_regs()
230 			readl(ispi->sregs + PREOP_OPTYPE));  in intel_spi_dump_regs()
231 		dev_dbg(ispi->dev, "OPMENU0=0x%08x\n",  in intel_spi_dump_regs()
232 			readl(ispi->sregs + OPMENU0));  in intel_spi_dump_regs()
233 		dev_dbg(ispi->dev, "OPMENU1=0x%08x\n",  in intel_spi_dump_regs()
234 			readl(ispi->sregs + OPMENU1));  in intel_spi_dump_regs()
237 	dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));  in intel_spi_dump_regs()
238 	dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));  in intel_spi_dump_regs()
240 	dev_dbg(ispi->dev, "Protected regions:\n");  in intel_spi_dump_regs()
241 	for (i = 0; i < ispi->pr_num; i++) {  in intel_spi_dump_regs()
244 		value = readl(ispi->pregs + PR(i));  in intel_spi_dump_regs()
251 		dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",  in intel_spi_dump_regs()
256 	dev_dbg(ispi->dev, "Flash regions:\n");  in intel_spi_dump_regs()
257 	for (i = 0; i < ispi->nregions; i++) {  in intel_spi_dump_regs()
260 		region = readl(ispi->base + FREG(i));  in intel_spi_dump_regs()
265 			dev_dbg(ispi->dev, " %02d disabled\n", i);  in intel_spi_dump_regs()
267 			dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",  in intel_spi_dump_regs()
271 	dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",  in intel_spi_dump_regs()
272 		ispi->swseq_reg ? 'S' : 'H');  in intel_spi_dump_regs()
273 	dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",  in intel_spi_dump_regs()
274 		ispi->swseq_erase ? 'S' : 'H');  in intel_spi_dump_regs()
284 		return -EINVAL;  in intel_spi_read_block()
288 		memcpy_fromio(buf, ispi->base + FDATA(i), bytes);  in intel_spi_read_block()
289 		size -= bytes;  in intel_spi_read_block()
305 		return -EINVAL;  in intel_spi_write_block()
309 		memcpy_toio(ispi->base + FDATA(i), buf, bytes);  in intel_spi_write_block()
310 		size -= bytes;  in intel_spi_write_block()
322 	return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,  in intel_spi_wait_hw_busy()
331 	return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,  in intel_spi_wait_sw_busy()
338 	if (!ispi->info->set_writeable)  in intel_spi_set_writeable()
341 	return ispi->info->set_writeable(ispi->base, ispi->info->data);  in intel_spi_set_writeable()
349 	if (ispi->locked) {  in intel_spi_opcode_index()
350 		for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)  in intel_spi_opcode_index()
351 			if (ispi->opcodes[i] == opcode)  in intel_spi_opcode_index()
354 		return -EINVAL;  in intel_spi_opcode_index()
358 	writel(opcode, ispi->sregs + OPMENU0);  in intel_spi_opcode_index()
359 	preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_opcode_index()
360 	writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);  in intel_spi_opcode_index()
371 	if (!iop->replacement_op)  in intel_spi_hw_cycle()
372 		return -EINVAL;  in intel_spi_hw_cycle()
374 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
376 	val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;  in intel_spi_hw_cycle()
379 	val |= iop->replacement_op;  in intel_spi_hw_cycle()
380 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
386 	status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
388 		return -EIO;  in intel_spi_hw_cycle()
390 		return -EACCES;  in intel_spi_hw_cycle()
407 	 * Always clear it after each SW sequencer operation regardless  in intel_spi_sw_cycle()
410 	atomic_preopcode = ispi->atomic_preopcode;  in intel_spi_sw_cycle()
411 	ispi->atomic_preopcode = 0;  in intel_spi_sw_cycle()
415 		val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;  in intel_spi_sw_cycle()
426 			preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_sw_cycle()
432 				return -EINVAL;  in intel_spi_sw_cycle()
439 			return -EINVAL;  in intel_spi_sw_cycle()
442 	writel(val, ispi->sregs + SSFSTS_CTL);  in intel_spi_sw_cycle()
448 	status = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_sw_cycle()
450 		return -EIO;  in intel_spi_sw_cycle()
452 		return -EACCES;  in intel_spi_sw_cycle()
463 	return (spi_get_chipselect(mem->spi, 0) == 1) ? ispi->chip0_size : 0;  in intel_spi_chip_addr()
470 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_read_reg()
471 	size_t nbytes = op->data.nbytes;  in intel_spi_read_reg()
472 	u8 opcode = op->cmd.opcode;  in intel_spi_read_reg()
475 	writel(addr, ispi->base + FADDR);  in intel_spi_read_reg()
477 	if (ispi->swseq_reg)  in intel_spi_read_reg()
486 	return intel_spi_read_block(ispi, op->data.buf.in, nbytes);  in intel_spi_read_reg()
493 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_write_reg()
494 	size_t nbytes = op->data.nbytes;  in intel_spi_write_reg()
495 	u8 opcode = op->cmd.opcode;  in intel_spi_write_reg()
504 	 * When hardware sequencer is used there is no need to program  in intel_spi_write_reg()
505 	 * any opcodes (it handles them automatically as part of a command).  in intel_spi_write_reg()
510 		if (!ispi->swseq_reg)  in intel_spi_write_reg()
513 		preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_write_reg()
515 			if (ispi->locked)  in intel_spi_write_reg()
516 				return -EINVAL;  in intel_spi_write_reg()
517 			writel(opcode, ispi->sregs + PREOP_OPTYPE);  in intel_spi_write_reg()
524 		ispi->atomic_preopcode = opcode;  in intel_spi_write_reg()
529 	 * We hope that HW sequencer will do the right thing automatically and  in intel_spi_write_reg()
530 	 * with the SW sequencer we cannot use preopcode anyway, so just ignore  in intel_spi_write_reg()
537 	writel(addr, ispi->base + FADDR);  in intel_spi_write_reg()
540 	ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes);  in intel_spi_write_reg()
544 	if (ispi->swseq_reg)  in intel_spi_write_reg()
554 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_read()
555 	size_t block_size, nbytes = op->data.nbytes;  in intel_spi_read()
556 	void *read_buf = op->data.buf.in;  in intel_spi_read()
561 	 * Atomic sequence is not expected with HW sequencer reads. Make  in intel_spi_read()
564 	if (WARN_ON_ONCE(ispi->atomic_preopcode))  in intel_spi_read()
565 		ispi->atomic_preopcode = 0;  in intel_spi_read()
572 				   round_up(addr + 1, SZ_4K)) - addr;  in intel_spi_read()
574 		writel(addr, ispi->base + FADDR);  in intel_spi_read()
576 		val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_read()
579 		val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;  in intel_spi_read()
582 		writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_read()
588 		status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_read()
590 			ret = -EIO;  in intel_spi_read()
592 			ret = -EACCES;  in intel_spi_read()
595 			dev_err(ispi->dev, "read error: %x: %#x\n", addr, status);  in intel_spi_read()
603 		nbytes -= block_size;  in intel_spi_read()
615 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_write()
616 	size_t block_size, nbytes = op->data.nbytes;  in intel_spi_write()
617 	const void *write_buf = op->data.buf.out;  in intel_spi_write()
621 	/* Not needed with HW sequencer write, make sure it is cleared */  in intel_spi_write()
622 	ispi->atomic_preopcode = 0;  in intel_spi_write()
629 				   round_up(addr + 1, SZ_4K)) - addr;  in intel_spi_write()
631 		writel(addr, ispi->base + FADDR);  in intel_spi_write()
633 		val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_write()
636 		val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;  in intel_spi_write()
641 			dev_err(ispi->dev, "failed to write block\n");  in intel_spi_write()
647 		writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_write()
651 			dev_err(ispi->dev, "timeout\n");  in intel_spi_write()
655 		status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_write()
657 			ret = -EIO;  in intel_spi_write()
659 			ret = -EACCES;  in intel_spi_write()
662 			dev_err(ispi->dev, "write error: %x: %#x\n", addr, status);  in intel_spi_write()
666 		nbytes -= block_size;  in intel_spi_write()
678 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_erase()
679 	u8 opcode = op->cmd.opcode;  in intel_spi_erase()
683 	writel(addr, ispi->base + FADDR);  in intel_spi_erase()
685 	if (ispi->swseq_erase)  in intel_spi_erase()
689 	/* Not needed with HW sequencer erase, make sure it is cleared */  in intel_spi_erase()
690 	ispi->atomic_preopcode = 0;  in intel_spi_erase()
692 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_erase()
696 	val |= iop->replacement_op;  in intel_spi_erase()
697 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_erase()
703 	status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_erase()
705 		return -EIO;  in intel_spi_erase()
707 		return -EACCES;  in intel_spi_erase()
714 	op->data.nbytes = clamp_val(op->data.nbytes, 0, INTEL_SPI_FIFO_SZ);  in intel_spi_adjust_op_size()
721 	if (iop->mem_op.cmd.nbytes != op->cmd.nbytes ||  in intel_spi_cmp_mem_op()
722 	    iop->mem_op.cmd.buswidth != op->cmd.buswidth ||  in intel_spi_cmp_mem_op()
723 	    iop->mem_op.cmd.dtr != op->cmd.dtr)  in intel_spi_cmp_mem_op()
726 	if (iop->mem_op.addr.nbytes != op->addr.nbytes ||  in intel_spi_cmp_mem_op()
727 	    iop->mem_op.addr.dtr != op->addr.dtr)  in intel_spi_cmp_mem_op()
730 	if (iop->mem_op.data.dir != op->data.dir ||  in intel_spi_cmp_mem_op()
731 	    iop->mem_op.data.dtr != op->data.dtr)  in intel_spi_cmp_mem_op()
734 	if (iop->mem_op.data.dir != SPI_MEM_NO_DATA) {  in intel_spi_cmp_mem_op()
735 		if (iop->mem_op.data.buswidth != op->data.buswidth)  in intel_spi_cmp_mem_op()
747 	for (iop = ispi->mem_ops; iop->mem_op.cmd.opcode; iop++) {  in intel_spi_match_mem_op()
748 		if (iop->mem_op.cmd.opcode == op->cmd.opcode &&  in intel_spi_match_mem_op()
759 	struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);  in intel_spi_supports_mem_op()
764 		dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);  in intel_spi_supports_mem_op()
769 	 * For software sequencer check that the opcode is actually  in intel_spi_supports_mem_op()
772 	if (ispi->swseq_reg && ispi->locked) {  in intel_spi_supports_mem_op()
776 		for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) {  in intel_spi_supports_mem_op()
777 			if (ispi->opcodes[i] == op->cmd.opcode)  in intel_spi_supports_mem_op()
781 		dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);  in intel_spi_supports_mem_op()
790 	struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);  in intel_spi_exec_mem_op()
795 		return -EOPNOTSUPP;  in intel_spi_exec_mem_op()
797 	return iop->exec_op(ispi, mem, iop, op);  in intel_spi_exec_mem_op()
802 	const struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);  in intel_spi_get_name()
808 	return dev_name(ispi->dev);  in intel_spi_get_name()
813 	struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);  in intel_spi_dirmap_create()
816 	iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl);  in intel_spi_dirmap_create()
818 		return -EOPNOTSUPP;  in intel_spi_dirmap_create()
820 	desc->priv = (void *)iop;  in intel_spi_dirmap_create()
827 	struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);  in intel_spi_dirmap_read()
828 	const struct intel_spi_mem_op *iop = desc->priv;  in intel_spi_dirmap_read()
829 	struct spi_mem_op op = desc->info.op_tmpl;  in intel_spi_dirmap_read()
837 	ret = iop->exec_op(ispi, desc->mem, iop, &op);  in intel_spi_dirmap_read()
844 	struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);  in intel_spi_dirmap_write()
845 	const struct intel_spi_mem_op *iop = desc->priv;  in intel_spi_dirmap_write()
846 	struct spi_mem_op op = desc->info.op_tmpl;  in intel_spi_dirmap_write()
853 	ret = iop->exec_op(ispi, desc->mem, iop, &op);  in intel_spi_dirmap_write()
988 	/* Read with 4-byte address opcode */				\
1001 	/* Fast read with 4-byte address opcode */			\
1084 	switch (ispi->info->type) {  in intel_spi_init()
1086 		ispi->sregs = ispi->base + BYT_SSFSTS_CTL;  in intel_spi_init()
1087 		ispi->pregs = ispi->base + BYT_PR;  in intel_spi_init()
1088 		ispi->nregions = BYT_FREG_NUM;  in intel_spi_init()
1089 		ispi->pr_num = BYT_PR_NUM;  in intel_spi_init()
1090 		ispi->swseq_reg = true;  in intel_spi_init()
1094 		ispi->sregs = ispi->base + LPT_SSFSTS_CTL;  in intel_spi_init()
1095 		ispi->pregs = ispi->base + LPT_PR;  in intel_spi_init()
1096 		ispi->nregions = LPT_FREG_NUM;  in intel_spi_init()
1097 		ispi->pr_num = LPT_PR_NUM;  in intel_spi_init()
1098 		ispi->swseq_reg = true;  in intel_spi_init()
1102 		ispi->sregs = ispi->base + BXT_SSFSTS_CTL;  in intel_spi_init()
1103 		ispi->pregs = ispi->base + BXT_PR;  in intel_spi_init()
1104 		ispi->nregions = BXT_FREG_NUM;  in intel_spi_init()
1105 		ispi->pr_num = BXT_PR_NUM;  in intel_spi_init()
1110 		ispi->sregs = NULL;  in intel_spi_init()
1111 		ispi->pregs = ispi->base + CNL_PR;  in intel_spi_init()
1112 		ispi->nregions = CNL_FREG_NUM;  in intel_spi_init()
1113 		ispi->pr_num = CNL_PR_NUM;  in intel_spi_init()
1118 		return -EINVAL;  in intel_spi_init()
1121 	ispi->bios_locked = true;  in intel_spi_init()
1125 			ispi->bios_locked = false;  in intel_spi_init()
1127 			dev_warn(ispi->dev, "can't disable chip write protection\n");  in intel_spi_init()
1130 	/* Disable #SMI generation from HW sequencer */  in intel_spi_init()
1131 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_init()
1133 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_init()
1136 	 * Determine whether erase operation should use HW or SW sequencer.  in intel_spi_init()
1138 	 * The HW sequencer has a predefined list of opcodes, with only the  in intel_spi_init()
1141 	 * cannot be done using HW sequencer.  in intel_spi_init()
1143 	lvscc = readl(ispi->base + LVSCC);  in intel_spi_init()
1144 	uvscc = readl(ispi->base + UVSCC);  in intel_spi_init()
1146 		ispi->swseq_erase = true;  in intel_spi_init()
1148 	if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)  in intel_spi_init()
1153 	if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) {  in intel_spi_init()
1154 		dev_err(ispi->dev, "software sequencer not supported, but required\n");  in intel_spi_init()
1155 		return -EINVAL;  in intel_spi_init()
1160 	 * sequencer. All other operations are supposed to be carried out  in intel_spi_init()
1161 	 * using software sequencer.  in intel_spi_init()
1163 	if (ispi->swseq_reg) {  in intel_spi_init()
1164 		/* Disable #SMI generation from SW sequencer */  in intel_spi_init()
1165 		val = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_init()
1167 		writel(val, ispi->sregs + SSFSTS_CTL);  in intel_spi_init()
1171 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_init()
1172 	ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);  in intel_spi_init()
1174 	if (ispi->locked && ispi->sregs) {  in intel_spi_init()
1180 		opmenu0 = readl(ispi->sregs + OPMENU0);  in intel_spi_init()
1181 		opmenu1 = readl(ispi->sregs + OPMENU1);  in intel_spi_init()
1184 			for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {  in intel_spi_init()
1185 				ispi->opcodes[i] = opmenu0 >> i * 8;  in intel_spi_init()
1186 				ispi->opcodes[i + 4] = opmenu1 >> i * 8;  in intel_spi_init()
1192 		dev_dbg(ispi->dev, "Using erase_64k memory operations");  in intel_spi_init()
1193 		ispi->mem_ops = erase_64k_mem_ops;  in intel_spi_init()
1195 		dev_dbg(ispi->dev, "Using generic memory operations");  in intel_spi_init()
1196 		ispi->mem_ops = generic_mem_ops;  in intel_spi_init()
1208 	for (i = 0; i < ispi->pr_num; i++) {  in intel_spi_is_protected()
1211 		pr_value = readl(ispi->pregs + PR(i));  in intel_spi_is_protected()
1238 	part->size = 4096;  in intel_spi_fill_partition()
1239 	part->name = "BIOS";  in intel_spi_fill_partition()
1245 	for (i = 1; i < ispi->nregions; i++) {  in intel_spi_fill_partition()
1248 		region = readl(ispi->base + FREG(i));  in intel_spi_fill_partition()
1258 		 * make the whole partition read-only to be on the safe side.  in intel_spi_fill_partition()
1265 			part->mask_flags |= MTD_WRITEABLE;  in intel_spi_fill_partition()
1266 			ispi->protected = true;  in intel_spi_fill_partition()
1270 		if (end > part->size)  in intel_spi_fill_partition()
1271 			part->size = end;  in intel_spi_fill_partition()
1278 	if (ispi->chip0_size && part->size > ispi->chip0_size)  in intel_spi_fill_partition()
1279 		part->size = MTDPART_SIZ_FULL;  in intel_spi_fill_partition()
1298 		dev_warn(ispi->dev, "failed to read descriptor\n");  in intel_spi_read_desc()
1302 	dev_dbg(ispi->dev, "FLVALSIG=0x%08x\n", buf[0]);  in intel_spi_read_desc()
1303 	dev_dbg(ispi->dev, "FLMAP0=0x%08x\n", buf[1]);  in intel_spi_read_desc()
1306 		dev_warn(ispi->dev, "descriptor signature not valid\n");  in intel_spi_read_desc()
1307 		return -ENODEV;  in intel_spi_read_desc()
1311 	dev_dbg(ispi->dev, "FCBA=%#x\n", fcba);  in intel_spi_read_desc()
1319 		dev_warn(ispi->dev, "failed to read FLCOMP\n");  in intel_spi_read_desc()
1320 		return -ENODEV;  in intel_spi_read_desc()
1323 	dev_dbg(ispi->dev, "FLCOMP=0x%08x\n", flcomp);  in intel_spi_read_desc()
1327 		ispi->chip0_size = SZ_512K;  in intel_spi_read_desc()
1330 		ispi->chip0_size = SZ_1M;  in intel_spi_read_desc()
1333 		ispi->chip0_size = SZ_2M;  in intel_spi_read_desc()
1336 		ispi->chip0_size = SZ_4M;  in intel_spi_read_desc()
1339 		ispi->chip0_size = SZ_8M;  in intel_spi_read_desc()
1342 		ispi->chip0_size = SZ_16M;  in intel_spi_read_desc()
1345 		ispi->chip0_size = SZ_32M;  in intel_spi_read_desc()
1348 		ispi->chip0_size = SZ_64M;  in intel_spi_read_desc()
1351 		return -EINVAL;  in intel_spi_read_desc()
1354 	dev_dbg(ispi->dev, "chip0 size %zd KB\n", ispi->chip0_size / SZ_1K);  in intel_spi_read_desc()
1358 		ispi->host->num_chipselect = 1;  in intel_spi_read_desc()
1360 		ispi->host->num_chipselect = 2;  in intel_spi_read_desc()
1362 		return -EINVAL;  in intel_spi_read_desc()
1364 	dev_dbg(ispi->dev, "%u flash components found\n",  in intel_spi_read_desc()
1365 		ispi->host->num_chipselect);  in intel_spi_read_desc()
1380 	pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL);  in intel_spi_populate_chip()
1382 		return -ENOMEM;  in intel_spi_populate_chip()
1384 	pdata->nr_parts = 1;  in intel_spi_populate_chip()
1385 	pdata->parts = devm_kcalloc(ispi->dev, pdata->nr_parts,  in intel_spi_populate_chip()
1386 				    sizeof(*pdata->parts), GFP_KERNEL);  in intel_spi_populate_chip()
1387 	if (!pdata->parts)  in intel_spi_populate_chip()
1388 		return -ENOMEM;  in intel_spi_populate_chip()
1390 	intel_spi_fill_partition(ispi, pdata->parts);  in intel_spi_populate_chip()
1393 	snprintf(chip.modalias, 8, "spi-nor");  in intel_spi_populate_chip()
1396 	if (!spi_new_device(ispi->host, &chip))  in intel_spi_populate_chip()
1397 		return -ENODEV;  in intel_spi_populate_chip()
1400 	if (ispi->host->num_chipselect < 2)  in intel_spi_populate_chip()
1403 	pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL);  in intel_spi_populate_chip()
1405 		return -ENOMEM;  in intel_spi_populate_chip()
1407 	pdata->name = devm_kasprintf(ispi->dev, GFP_KERNEL, "%s-chip1",  in intel_spi_populate_chip()
1408 				     dev_name(ispi->dev));  in intel_spi_populate_chip()
1409 	if (!pdata->name)  in intel_spi_populate_chip()
1410 		return -ENOMEM;  in intel_spi_populate_chip()
1412 	pdata->nr_parts = 1;  in intel_spi_populate_chip()
1413 	parts = devm_kcalloc(ispi->dev, pdata->nr_parts, sizeof(*parts),  in intel_spi_populate_chip()
1416 		return -ENOMEM;  in intel_spi_populate_chip()
1420 	pdata->parts = parts;  in intel_spi_populate_chip()
1425 	if (!spi_new_device(ispi->host, &chip))  in intel_spi_populate_chip()
1426 		return -ENODEV;  in intel_spi_populate_chip()
1435 	return sysfs_emit(buf, "%d\n", ispi->protected);  in intel_spi_protected_show()
1444 	return sysfs_emit(buf, "%d\n", ispi->locked);  in intel_spi_locked_show()
1453 	return sysfs_emit(buf, "%d\n", ispi->bios_locked);  in intel_spi_bios_locked_show()
1475  * intel_spi_probe() - Probe the Intel SPI flash controller
1492 		return -ENOMEM;  in intel_spi_probe()
1494 	host->mem_ops = &intel_spi_mem_ops;  in intel_spi_probe()
1498 	ispi->base = base;  in intel_spi_probe()
1499 	ispi->dev = dev;  in intel_spi_probe()
1500 	ispi->host = host;  in intel_spi_probe()
1501 	ispi->info = info;  in intel_spi_probe()