Lines Matching full:se

16 #include <linux/soc/qcom/geni-se.h>
20 /* SPI SE specific registers and respective register fields */
79 struct geni_se se; member
108 struct geni_se *se = &mas->se; in spi_slv_setup() local
110 writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN); in spi_slv_setup()
111 writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL); in spi_slv_setup()
112 writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START); in spi_slv_setup()
125 ret = geni_se_clk_freq_match(&mas->se, in get_spi_clk_cfg()
153 struct geni_se *se = &mas->se; in handle_se_timeout() local
158 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in handle_se_timeout()
173 geni_se_cancel_m_cmd(se); in handle_se_timeout()
182 geni_se_abort_m_cmd(se); in handle_se_timeout()
202 writel(1, se->base + SE_DMA_TX_FSM_RST); in handle_se_timeout()
211 writel(1, se->base + SE_DMA_RX_FSM_RST); in handle_se_timeout()
255 struct geni_se *se = &mas->se; in spi_geni_is_abort_still_pending() local
268 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in spi_geni_is_abort_still_pending()
269 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); in spi_geni_is_abort_still_pending()
291 struct geni_se *se = &mas->se; in spi_geni_set_cs() local
317 geni_se_select_mode(se, mas->cur_xfer_mode); in spi_geni_set_cs()
321 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); in spi_geni_set_cs()
323 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); in spi_geni_set_cs()
341 struct geni_se *se = &mas->se; in spi_setup_word_len() local
352 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, in spi_setup_word_len()
355 writel(word_len, se->base + SE_SPI_WORD_LEN); in spi_setup_word_len()
362 struct geni_se *se = &mas->se; in geni_spi_set_clock_and_bw() local
385 writel(clk_sel, se->base + SE_GENI_CLK_SEL); in geni_spi_set_clock_and_bw()
386 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); in geni_spi_set_clock_and_bw()
389 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); in geni_spi_set_clock_and_bw()
390 ret = geni_icc_set_bw(se); in geni_spi_set_clock_and_bw()
401 struct geni_se *se = &mas->se; in setup_fifo_params() local
422 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); in setup_fifo_params()
423 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); in setup_fifo_params()
424 writel(cpha, se->base + SE_SPI_CPHA); in setup_fifo_params()
425 writel(cpol, se->base + SE_SPI_CPOL); in setup_fifo_params()
426 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); in setup_fifo_params()
569 /* Set SE DMA mode for SPI target. */ in geni_can_dma()
659 struct geni_se *se = &mas->se; in spi_geni_init() local
666 proto = geni_se_read_proto(se); in spi_geni_init()
678 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); in spi_geni_init()
681 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); in spi_geni_init()
687 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); in spi_geni_init()
690 ver = geni_se_get_qup_hw_version(se); in spi_geni_init()
699 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; in spi_geni_init()
705 geni_se_select_mode(se, GENI_GPI_DMA); in spi_geni_init()
720 geni_se_select_mode(se, GENI_SE_FIFO); in spi_geni_init()
727 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
729 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
753 struct geni_se *se = &mas->se; in geni_spi_handle_tx() local
761 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
779 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); in geni_spi_handle_tx()
783 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
791 struct geni_se *se = &mas->se; in geni_spi_handle_rx() local
799 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); in geni_spi_handle_rx()
811 readl(se->base + SE_GENI_RX_FIFOn); in geni_spi_handle_rx()
826 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); in geni_spi_handle_rx()
839 struct geni_se *se = &mas->se; in setup_se_xfer() local
876 writel(len, se->base + SE_SPI_TX_TRANS_LEN); in setup_se_xfer()
881 writel(len, se->base + SE_SPI_RX_TRANS_LEN); in setup_se_xfer()
899 geni_se_select_mode(se, mas->cur_xfer_mode); in setup_se_xfer()
906 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); in setup_se_xfer()
910 geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl), in setup_se_xfer()
913 geni_se_tx_init_dma(se, sg_dma_address(xfer->tx_sg.sgl), in setup_se_xfer()
917 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); in setup_se_xfer()
952 struct geni_se *se = &mas->se; in geni_spi_isr() local
955 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in geni_spi_isr()
991 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_isr()
1004 u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT); in geni_spi_isr()
1005 u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT); in geni_spi_isr()
1008 writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR); in geni_spi_isr()
1010 writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR); in geni_spi_isr()
1043 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); in geni_spi_isr()
1071 clk = devm_clk_get(dev, "se"); in spi_geni_probe()
1083 mas->se.dev = dev; in spi_geni_probe()
1084 mas->se.wrapper = dev_get_drvdata(dev->parent); in spi_geni_probe()
1085 mas->se.base = base; in spi_geni_probe()
1086 mas->se.clk = clk; in spi_geni_probe()
1088 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); in spi_geni_probe()
1120 ret = geni_icc_get(&mas->se, NULL); in spi_geni_probe()
1134 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); in spi_geni_probe()
1135 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in spi_geni_probe()
1137 ret = geni_icc_set_bw(&mas->se); in spi_geni_probe()
1175 ret = geni_se_resources_off(&mas->se); in spi_geni_runtime_suspend()
1179 return geni_icc_disable(&mas->se); in spi_geni_runtime_suspend()
1188 ret = geni_icc_enable(&mas->se); in spi_geni_runtime_resume()
1192 ret = geni_se_resources_on(&mas->se); in spi_geni_runtime_resume()