Lines Matching full:q
295 static bool needs_swap_endian(struct fsl_qspi *q)
297 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN);
300 static bool needs_4x_clock(struct fsl_qspi *q)
302 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK);
305 static bool needs_fill_txfifo(struct fsl_qspi *q)
307 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890);
310 static bool needs_wakeup_wait_mode(struct fsl_qspi *q)
312 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618);
315 static bool needs_amba_base_offset(struct fsl_qspi *q)
317 return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
320 static bool needs_tdh_setting(struct fsl_qspi *q)
322 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING);
325 static bool needs_clk_disable(struct fsl_qspi *q)
327 return !(q->devtype_data->quirks & QUADSPI_QUIRK_SKIP_CLK_DISABLE);
334 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
336 return needs_swap_endian(q) ? __swab32(a) : a;
346 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
348 if (q->devtype_data->little_endian)
354 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
356 if (q->devtype_data->little_endian)
364 struct fsl_qspi *q = dev_id;
368 reg = qspi_readl(q, q->iobase + QUADSPI_FR);
369 qspi_writel(q, reg, q->iobase + QUADSPI_FR);
372 complete(&q->c);
374 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
378 static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
393 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);
396 ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
399 ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
402 ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
405 ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
426 (op->data.nbytes > q->devtype_data->ahb_buf_size ||
427 (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
432 op->data.nbytes > q->devtype_data->txfifo)
438 static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
441 void __iomem *base = q->iobase;
482 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
483 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
487 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
490 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
491 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
494 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
498 ret = clk_prepare_enable(q->clk_en);
502 ret = clk_prepare_enable(q->clk);
504 clk_disable_unprepare(q->clk_en);
508 if (needs_wakeup_wait_mode(q))
509 cpu_latency_qos_add_request(&q->pm_qos_req, 0);
514 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
516 if (needs_wakeup_wait_mode(q))
517 cpu_latency_qos_remove_request(&q->pm_qos_req);
519 clk_disable_unprepare(q->clk);
520 clk_disable_unprepare(q->clk_en);
530 static void fsl_qspi_invalidate(struct fsl_qspi *q)
534 reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
536 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
545 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
548 static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi,
554 if (q->selected == spi_get_chipselect(spi, 0))
557 if (needs_4x_clock(q))
560 if (needs_clk_disable(q))
561 fsl_qspi_clk_disable_unprep(q);
563 ret = clk_set_rate(q->clk, rate);
567 if (needs_clk_disable(q)) {
568 ret = fsl_qspi_clk_prep_enable(q);
573 q->selected = spi_get_chipselect(spi, 0);
575 fsl_qspi_invalidate(q);
578 static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
581 q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
585 static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
588 void __iomem *base = q->iobase;
594 val = fsl_qspi_endian_xchg(q, val);
595 qspi_writel(q, val, base + QUADSPI_TBDR);
600 val = fsl_qspi_endian_xchg(q, val);
601 qspi_writel(q, val, base + QUADSPI_TBDR);
604 if (needs_fill_txfifo(q)) {
606 qspi_writel(q, 0, base + QUADSPI_TBDR);
610 static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
613 void __iomem *base = q->iobase;
619 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
620 val = fsl_qspi_endian_xchg(q, val);
625 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
626 val = fsl_qspi_endian_xchg(q, val);
631 static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
633 void __iomem *base = q->iobase;
636 init_completion(&q->c);
643 qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
647 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
651 fsl_qspi_read_rxfifo(q, op);
656 static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
661 if (!q->devtype_data->little_endian)
670 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);
671 void __iomem *base = q->iobase;
674 int invalid_mstrid = q->devtype_data->invalid_mstrid;
676 mutex_lock(&q->lock);
679 fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
682 fsl_qspi_select_mem(q, mem->spi, op);
684 if (needs_amba_base_offset(q))
685 addr_offset = q->memmap_phy;
687 qspi_writel(q,
688 q->selected * q->devtype_data->ahb_buf_size + addr_offset,
691 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
695 qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
698 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR);
699 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR);
700 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR);
702 fsl_qspi_prepare_lut(q, op);
709 if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
711 fsl_qspi_read_ahb(q, op);
713 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
717 fsl_qspi_fill_txfifo(q, op);
719 err = fsl_qspi_do_op(q, op);
723 fsl_qspi_invalidate(q);
725 mutex_unlock(&q->lock);
732 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);
735 if (op->data.nbytes > q->devtype_data->txfifo)
736 op->data.nbytes = q->devtype_data->txfifo;
738 if (op->data.nbytes > q->devtype_data->ahb_buf_size)
739 op->data.nbytes = q->devtype_data->ahb_buf_size;
740 else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
747 static int fsl_qspi_default_setup(struct fsl_qspi *q)
749 void __iomem *base = q->iobase;
755 fsl_qspi_clk_disable_unprep(q);
758 ret = clk_set_rate(q->clk, 66000000);
762 ret = fsl_qspi_clk_prep_enable(q);
767 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
772 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
780 if (needs_tdh_setting(q))
781 qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
785 reg = qspi_readl(q, base + QUADSPI_SMPR);
786 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
792 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
793 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
794 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
796 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
797 q->iobase + QUADSPI_BFGENCR);
798 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
799 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
800 QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
803 if (needs_amba_base_offset(q))
804 addr_offset = q->memmap_phy;
816 sfa_size = q->devtype_data->sfa_size ? : q->devtype_data->ahb_buf_size;
817 qspi_writel(q, addr_offset + 1 * sfa_size, base + QUADSPI_SFA1AD);
818 qspi_writel(q, addr_offset + 2 * sfa_size, base + QUADSPI_SFA2AD);
819 qspi_writel(q, addr_offset + 3 * sfa_size, base + QUADSPI_SFB1AD);
820 qspi_writel(q, addr_offset + 4 * sfa_size, base + QUADSPI_SFB2AD);
822 q->selected = -1;
825 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
829 qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
832 qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
839 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);
848 if (of_get_available_child_count(q->dev->of_node) == 1)
849 return dev_name(q->dev);
852 "%s-%d", dev_name(q->dev),
876 struct fsl_qspi *q = data;
879 qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
880 qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
885 struct fsl_qspi *q = data;
887 reset_control_assert(q->resets);
889 fsl_qspi_clk_disable_unprep(q);
891 mutex_destroy(&q->lock);
900 struct fsl_qspi *q;
903 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*q));
910 q = spi_controller_get_devdata(ctlr);
911 q->dev = dev;
912 q->devtype_data = of_device_get_match_data(dev);
913 if (!q->devtype_data)
916 platform_set_drvdata(pdev, q);
919 q->iobase = devm_platform_ioremap_resource_byname(pdev, "QuadSPI");
920 if (IS_ERR(q->iobase))
921 return PTR_ERR(q->iobase);
927 q->memmap_phy = res->start;
929 q->ahb_addr = devm_ioremap(dev, q->memmap_phy,
930 (q->devtype_data->ahb_buf_size * 4));
931 if (!q->ahb_addr)
934 q->resets = devm_reset_control_array_get_optional_exclusive(dev);
935 if (IS_ERR(q->resets))
936 return PTR_ERR(q->resets);
939 q->clk_en = devm_clk_get(dev, "qspi_en");
940 if (IS_ERR(q->clk_en))
941 return PTR_ERR(q->clk_en);
943 q->clk = devm_clk_get(dev, "qspi");
944 if (IS_ERR(q->clk))
945 return PTR_ERR(q->clk);
947 mutex_init(&q->lock);
949 ret = fsl_qspi_clk_prep_enable(q);
955 ret = devm_add_action_or_reset(dev, fsl_qspi_cleanup, q);
959 ret = reset_control_deassert(q->resets);
969 fsl_qspi_irq_handler, 0, pdev->name, q);
980 fsl_qspi_default_setup(q);
984 ret = devm_add_action_or_reset(dev, fsl_qspi_disable, q);
1002 struct fsl_qspi *q = dev_get_drvdata(dev);
1004 fsl_qspi_default_setup(q);