Lines Matching +full:spi +full:- +full:only +full:- +full:use +full:- +full:cs1 +full:- +full:sel
1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-mapping.h>
22 #include <linux/dma/imx-dma.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/spi_bitbang.h>
34 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
144 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
145 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
153 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
155 if (fsl_lpspi->rx_buf) { \
156 *(type *)fsl_lpspi->rx_buf = val; \
157 fsl_lpspi->rx_buf += sizeof(type); \
166 if (fsl_lpspi->tx_buf) { \
167 val = *(type *)fsl_lpspi->tx_buf; \
168 fsl_lpspi->tx_buf += sizeof(type); \
171 fsl_lpspi->remain -= sizeof(type); \
172 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
185 writel(enable, fsl_lpspi->base + IMX7ULP_IER);
194 struct spi_device *spi,
199 if (!controller->dma_rx)
202 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
222 ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
224 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
236 pm_runtime_mark_last_busy(fsl_lpspi->dev);
237 pm_runtime_put_autosuspend(fsl_lpspi->dev);
247 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
249 while (txfifo_cnt < fsl_lpspi->txfifosize) {
250 if (!fsl_lpspi->remain)
252 fsl_lpspi->tx(fsl_lpspi);
256 if (txfifo_cnt < fsl_lpspi->txfifosize) {
257 if (!fsl_lpspi->is_target) {
258 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
260 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
270 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
271 fsl_lpspi->rx(fsl_lpspi);
278 temp |= fsl_lpspi->config.bpw - 1;
279 temp |= (fsl_lpspi->config.mode & 0x3) << 30;
280 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
281 if (!fsl_lpspi->is_target) {
282 temp |= fsl_lpspi->config.prescale << 27;
288 if (!fsl_lpspi->usedma) {
290 if (fsl_lpspi->is_first_byte)
296 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
298 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
305 if (!fsl_lpspi->usedma)
306 temp = fsl_lpspi->watermark >> 1 |
307 (fsl_lpspi->watermark >> 1) << 16;
309 temp = fsl_lpspi->watermark >> 1;
311 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
313 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
318 struct lpspi_config config = fsl_lpspi->config;
324 perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
325 prescale_max = fsl_lpspi->devtype_data->prescale_max;
328 dev_err(fsl_lpspi->dev,
330 return -EINVAL;
334 dev_err(fsl_lpspi->dev,
335 "per-clk should be at least two times of transfer speed");
336 return -EINVAL;
342 scldiv = div / (1 << prescale) - 2;
344 fsl_lpspi->config.prescale = prescale;
350 return -EINVAL;
353 fsl_lpspi->base + IMX7ULP_CCR);
355 fsl_lpspi->config.effective_speed_hz = perclk_rate / (scldiv + 2) *
358 dev_dbg(fsl_lpspi->dev, "perclk=%u, speed=%u, prescale=%u, scldiv=%d\n",
372 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
383 return -EINVAL;
387 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
390 ret = dmaengine_slave_config(controller->dma_tx, &tx);
392 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
398 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
401 ret = dmaengine_slave_config(controller->dma_rx, &rx);
403 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
416 if (!fsl_lpspi->is_target) {
424 if (!fsl_lpspi->is_target)
428 if (fsl_lpspi->config.mode & SPI_CS_HIGH)
430 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
432 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
434 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
437 if (fsl_lpspi->usedma)
439 writel(temp, fsl_lpspi->base + IMX7ULP_DER);
445 struct spi_device *spi,
449 spi_controller_get_devdata(spi->controller);
452 return -EINVAL;
454 fsl_lpspi->config.mode = spi->mode;
455 fsl_lpspi->config.bpw = t->bits_per_word;
456 fsl_lpspi->config.speed_hz = t->speed_hz;
457 if (fsl_lpspi->is_only_cs1)
458 fsl_lpspi->config.chip_select = 1;
460 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0);
462 if (!fsl_lpspi->config.speed_hz)
463 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
464 if (!fsl_lpspi->config.bpw)
465 fsl_lpspi->config.bpw = spi->bits_per_word;
468 if (fsl_lpspi->config.bpw <= 8) {
469 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
470 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
471 } else if (fsl_lpspi->config.bpw <= 16) {
472 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
473 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
475 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
476 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
479 if (t->len <= fsl_lpspi->txfifosize)
480 fsl_lpspi->watermark = t->len;
482 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
484 if (fsl_lpspi_can_dma(controller, spi, t))
485 fsl_lpspi->usedma = true;
487 fsl_lpspi->usedma = false;
497 fsl_lpspi->target_aborted = true;
498 if (!fsl_lpspi->usedma)
499 complete(&fsl_lpspi->xfer_done);
501 complete(&fsl_lpspi->dma_tx_completion);
502 complete(&fsl_lpspi->dma_rx_completion);
513 if (fsl_lpspi->is_target) {
514 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
515 fsl_lpspi->target_aborted) {
516 dev_dbg(fsl_lpspi->dev, "interrupted\n");
517 return -EINTR;
520 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
521 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
522 return -ETIMEDOUT;
533 if (!fsl_lpspi->usedma) {
540 writel(temp, fsl_lpspi->base + IMX7ULP_SR);
544 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
553 complete(&fsl_lpspi->dma_rx_completion);
560 complete(&fsl_lpspi->dma_tx_completion);
569 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
585 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
592 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
593 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
596 return -EINVAL;
598 desc_rx->callback = fsl_lpspi_dma_rx_callback;
599 desc_rx->callback_param = (void *)fsl_lpspi;
601 reinit_completion(&fsl_lpspi->dma_rx_completion);
602 dma_async_issue_pending(controller->dma_rx);
604 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
605 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
608 dmaengine_terminate_all(controller->dma_tx);
609 return -EINVAL;
612 desc_tx->callback = fsl_lpspi_dma_tx_callback;
613 desc_tx->callback_param = (void *)fsl_lpspi;
615 reinit_completion(&fsl_lpspi->dma_tx_completion);
616 dma_async_issue_pending(controller->dma_tx);
618 fsl_lpspi->target_aborted = false;
620 if (!fsl_lpspi->is_target) {
622 transfer->len);
625 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
628 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
629 dmaengine_terminate_all(controller->dma_tx);
630 dmaengine_terminate_all(controller->dma_rx);
632 return -ETIMEDOUT;
635 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
638 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
639 dmaengine_terminate_all(controller->dma_tx);
640 dmaengine_terminate_all(controller->dma_rx);
642 return -ETIMEDOUT;
645 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
646 fsl_lpspi->target_aborted) {
647 dev_dbg(fsl_lpspi->dev,
649 dmaengine_terminate_all(controller->dma_tx);
650 dmaengine_terminate_all(controller->dma_rx);
652 return -EINTR;
655 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
656 fsl_lpspi->target_aborted) {
657 dev_dbg(fsl_lpspi->dev,
659 dmaengine_terminate_all(controller->dma_tx);
660 dmaengine_terminate_all(controller->dma_rx);
662 return -EINTR;
673 if (controller->dma_rx) {
674 dma_release_channel(controller->dma_rx);
675 controller->dma_rx = NULL;
678 if (controller->dma_tx) {
679 dma_release_channel(controller->dma_tx);
680 controller->dma_tx = NULL;
691 controller->dma_tx = dma_request_chan(dev, "tx");
692 if (IS_ERR(controller->dma_tx)) {
693 ret = PTR_ERR(controller->dma_tx);
695 controller->dma_tx = NULL;
700 controller->dma_rx = dma_request_chan(dev, "rx");
701 if (IS_ERR(controller->dma_rx)) {
702 ret = PTR_ERR(controller->dma_rx);
704 controller->dma_rx = NULL;
708 init_completion(&fsl_lpspi->dma_rx_completion);
709 init_completion(&fsl_lpspi->dma_tx_completion);
710 controller->can_dma = fsl_lpspi_can_dma;
711 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
726 fsl_lpspi->tx_buf = t->tx_buf;
727 fsl_lpspi->rx_buf = t->rx_buf;
728 fsl_lpspi->remain = t->len;
730 reinit_completion(&fsl_lpspi->xfer_done);
731 fsl_lpspi->target_aborted = false;
745 struct spi_device *spi,
752 fsl_lpspi->is_first_byte = true;
753 ret = fsl_lpspi_setup_transfer(controller, spi, t);
757 t->effective_speed_hz = fsl_lpspi->config.effective_speed_hz;
760 fsl_lpspi->is_first_byte = false;
762 if (fsl_lpspi->usedma)
777 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
779 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
789 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
790 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
796 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
797 complete(&fsl_lpspi->xfer_done);
813 ret = clk_prepare_enable(fsl_lpspi->clk_per);
817 ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
819 clk_disable_unprepare(fsl_lpspi->clk_per);
833 clk_disable_unprepare(fsl_lpspi->clk_per);
834 clk_disable_unprepare(fsl_lpspi->clk_ipg);
842 struct device *dev = fsl_lpspi->dev;
862 devtype_data = of_device_get_match_data(&pdev->dev);
864 return -ENODEV;
866 is_target = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
868 controller = devm_spi_alloc_target(&pdev->dev,
871 controller = devm_spi_alloc_host(&pdev->dev,
875 return -ENOMEM;
880 fsl_lpspi->dev = &pdev->dev;
881 fsl_lpspi->is_target = is_target;
882 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
883 "fsl,spi-only-use-cs1-sel");
884 fsl_lpspi->devtype_data = devtype_data;
886 init_completion(&fsl_lpspi->xfer_done);
888 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
889 if (IS_ERR(fsl_lpspi->base)) {
890 ret = PTR_ERR(fsl_lpspi->base);
893 fsl_lpspi->base_phys = res->start;
901 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, IRQF_NO_AUTOEN,
902 dev_name(&pdev->dev), fsl_lpspi);
904 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
908 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
909 if (IS_ERR(fsl_lpspi->clk_per)) {
910 ret = PTR_ERR(fsl_lpspi->clk_per);
914 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
915 if (IS_ERR(fsl_lpspi->clk_ipg)) {
916 ret = PTR_ERR(fsl_lpspi->clk_ipg);
925 ret = pm_runtime_get_sync(fsl_lpspi->dev);
927 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
931 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
932 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
933 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
934 if (of_property_read_u32((&pdev->dev)->of_node, "num-cs",
936 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx93-spi"))
942 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
943 controller->transfer_one = fsl_lpspi_transfer_one;
944 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
945 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
946 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
947 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
948 controller->dev.of_node = pdev->dev.of_node;
949 controller->bus_num = pdev->id;
950 controller->num_chipselect = num_cs;
951 controller->target_abort = fsl_lpspi_target_abort;
952 if (!fsl_lpspi->is_target)
953 controller->use_gpio_descriptors = true;
955 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
956 if (ret == -EPROBE_DEFER)
959 dev_warn(&pdev->dev, "dma setup error %d, use pio\n", ret);
963 ret = devm_spi_register_controller(&pdev->dev, controller);
965 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n");
969 pm_runtime_mark_last_busy(fsl_lpspi->dev);
970 pm_runtime_put_autosuspend(fsl_lpspi->dev);
977 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
978 pm_runtime_put_sync(fsl_lpspi->dev);
979 pm_runtime_disable(fsl_lpspi->dev);
992 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
993 pm_runtime_disable(fsl_lpspi->dev);