Lines Matching +full:cs +full:- +full:extra +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
23 #include <linux/dma/imx-dma.h>
36 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
154 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
155 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
156 { .compatible = "nxp,s32g2-lpspi", .data = &s32g_lpspi_devtype_data,},
164 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
166 if (fsl_lpspi->rx_buf) { \
167 *(type *)fsl_lpspi->rx_buf = val; \
168 fsl_lpspi->rx_buf += sizeof(type); \
177 if (fsl_lpspi->tx_buf) { \
178 val = *(type *)fsl_lpspi->tx_buf; \
179 fsl_lpspi->tx_buf += sizeof(type); \
182 fsl_lpspi->remain -= sizeof(type); \
183 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
196 writel(enable, fsl_lpspi->base + IMX7ULP_IER); in LPSPI_BUF_TX()
210 if (!controller->dma_rx) in fsl_lpspi_can_dma()
213 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word); in fsl_lpspi_can_dma()
233 ret = pm_runtime_resume_and_get(fsl_lpspi->dev); in lpspi_prepare_xfer_hardware()
235 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); in lpspi_prepare_xfer_hardware()
247 pm_runtime_put_autosuspend(fsl_lpspi->dev); in lpspi_unprepare_xfer_hardware()
257 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; in fsl_lpspi_write_tx_fifo()
259 while (txfifo_cnt < fsl_lpspi->txfifosize) { in fsl_lpspi_write_tx_fifo()
260 if (!fsl_lpspi->remain) in fsl_lpspi_write_tx_fifo()
262 fsl_lpspi->tx(fsl_lpspi); in fsl_lpspi_write_tx_fifo()
266 if (txfifo_cnt < fsl_lpspi->txfifosize) { in fsl_lpspi_write_tx_fifo()
267 if (!fsl_lpspi->is_target) { in fsl_lpspi_write_tx_fifo()
268 temp = readl(fsl_lpspi->base + IMX7ULP_TCR); in fsl_lpspi_write_tx_fifo()
270 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); in fsl_lpspi_write_tx_fifo()
280 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY)) in fsl_lpspi_read_rx_fifo()
281 fsl_lpspi->rx(fsl_lpspi); in fsl_lpspi_read_rx_fifo()
288 temp |= fsl_lpspi->config.bpw - 1; in fsl_lpspi_set_cmd()
289 temp |= (fsl_lpspi->config.mode & 0x3) << 30; in fsl_lpspi_set_cmd()
290 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24; in fsl_lpspi_set_cmd()
291 if (!fsl_lpspi->is_target) { in fsl_lpspi_set_cmd()
292 temp |= fsl_lpspi->config.prescale << 27; in fsl_lpspi_set_cmd()
298 if (!fsl_lpspi->usedma) { in fsl_lpspi_set_cmd()
300 if (fsl_lpspi->is_first_byte) in fsl_lpspi_set_cmd()
306 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); in fsl_lpspi_set_cmd()
308 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp); in fsl_lpspi_set_cmd()
315 if (!fsl_lpspi->usedma) in fsl_lpspi_set_watermark()
316 temp = fsl_lpspi->watermark >> 1 | in fsl_lpspi_set_watermark()
317 (fsl_lpspi->watermark >> 1) << 16; in fsl_lpspi_set_watermark()
319 temp = fsl_lpspi->watermark >> 1; in fsl_lpspi_set_watermark()
321 writel(temp, fsl_lpspi->base + IMX7ULP_FCR); in fsl_lpspi_set_watermark()
323 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp); in fsl_lpspi_set_watermark()
328 struct lpspi_config config = fsl_lpspi->config; in fsl_lpspi_set_bitrate()
334 perclk_rate = clk_get_rate(fsl_lpspi->clk_per); in fsl_lpspi_set_bitrate()
335 prescale_max = fsl_lpspi->devtype_data->prescale_max ?: 7; in fsl_lpspi_set_bitrate()
338 dev_err(fsl_lpspi->dev, in fsl_lpspi_set_bitrate()
340 return -EINVAL; in fsl_lpspi_set_bitrate()
350 scldiv = div / (1 << prescale) - 2; in fsl_lpspi_set_bitrate()
352 fsl_lpspi->config.prescale = prescale; in fsl_lpspi_set_bitrate()
358 return -EINVAL; in fsl_lpspi_set_bitrate()
361 fsl_lpspi->base + IMX7ULP_CCR); in fsl_lpspi_set_bitrate()
363 fsl_lpspi->config.effective_speed_hz = perclk_rate / (scldiv + 2) * in fsl_lpspi_set_bitrate()
366 dev_dbg(fsl_lpspi->dev, "perclk=%u, speed=%u, prescale=%u, scldiv=%d\n", in fsl_lpspi_set_bitrate()
380 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) { in fsl_lpspi_dma_configure()
391 return -EINVAL; in fsl_lpspi_dma_configure()
395 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR; in fsl_lpspi_dma_configure()
398 ret = dmaengine_slave_config(controller->dma_tx, &tx); in fsl_lpspi_dma_configure()
400 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n", in fsl_lpspi_dma_configure()
406 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR; in fsl_lpspi_dma_configure()
409 ret = dmaengine_slave_config(controller->dma_rx, &rx); in fsl_lpspi_dma_configure()
411 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n", in fsl_lpspi_dma_configure()
424 if (!fsl_lpspi->is_target) { in fsl_lpspi_config()
432 if (!fsl_lpspi->is_target) in fsl_lpspi_config()
436 if (fsl_lpspi->config.mode & SPI_CS_HIGH) in fsl_lpspi_config()
438 BIT(fsl_lpspi->config.chip_select)); in fsl_lpspi_config()
440 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1); in fsl_lpspi_config()
442 temp = readl(fsl_lpspi->base + IMX7ULP_CR); in fsl_lpspi_config()
444 writel(temp, fsl_lpspi->base + IMX7ULP_CR); in fsl_lpspi_config()
447 if (fsl_lpspi->usedma) in fsl_lpspi_config()
449 writel(temp, fsl_lpspi->base + IMX7ULP_DER); in fsl_lpspi_config()
459 spi_controller_get_devdata(spi->controller); in fsl_lpspi_setup_transfer()
462 return -EINVAL; in fsl_lpspi_setup_transfer()
464 fsl_lpspi->config.mode = spi->mode; in fsl_lpspi_setup_transfer()
465 fsl_lpspi->config.bpw = t->bits_per_word; in fsl_lpspi_setup_transfer()
466 fsl_lpspi->config.speed_hz = t->speed_hz; in fsl_lpspi_setup_transfer()
467 if (fsl_lpspi->is_only_cs1) in fsl_lpspi_setup_transfer()
468 fsl_lpspi->config.chip_select = 1; in fsl_lpspi_setup_transfer()
470 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0); in fsl_lpspi_setup_transfer()
472 if (!fsl_lpspi->config.speed_hz) in fsl_lpspi_setup_transfer()
473 fsl_lpspi->config.speed_hz = spi->max_speed_hz; in fsl_lpspi_setup_transfer()
474 if (!fsl_lpspi->config.bpw) in fsl_lpspi_setup_transfer()
475 fsl_lpspi->config.bpw = spi->bits_per_word; in fsl_lpspi_setup_transfer()
478 if (fsl_lpspi->config.bpw <= 8) { in fsl_lpspi_setup_transfer()
479 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8; in fsl_lpspi_setup_transfer()
480 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8; in fsl_lpspi_setup_transfer()
481 } else if (fsl_lpspi->config.bpw <= 16) { in fsl_lpspi_setup_transfer()
482 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16; in fsl_lpspi_setup_transfer()
483 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16; in fsl_lpspi_setup_transfer()
485 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32; in fsl_lpspi_setup_transfer()
486 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32; in fsl_lpspi_setup_transfer()
489 fsl_lpspi->watermark = min_t(typeof(fsl_lpspi->watermark), in fsl_lpspi_setup_transfer()
490 fsl_lpspi->txfifosize, in fsl_lpspi_setup_transfer()
491 t->len); in fsl_lpspi_setup_transfer()
494 fsl_lpspi->usedma = true; in fsl_lpspi_setup_transfer()
496 fsl_lpspi->usedma = false; in fsl_lpspi_setup_transfer()
506 fsl_lpspi->target_aborted = true; in fsl_lpspi_target_abort()
507 if (!fsl_lpspi->usedma) in fsl_lpspi_target_abort()
508 complete(&fsl_lpspi->xfer_done); in fsl_lpspi_target_abort()
510 complete(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_target_abort()
511 complete(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_target_abort()
522 if (fsl_lpspi->is_target) { in fsl_lpspi_wait_for_completion()
523 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) || in fsl_lpspi_wait_for_completion()
524 fsl_lpspi->target_aborted) { in fsl_lpspi_wait_for_completion()
525 dev_dbg(fsl_lpspi->dev, "interrupted\n"); in fsl_lpspi_wait_for_completion()
526 return -EINTR; in fsl_lpspi_wait_for_completion()
529 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) { in fsl_lpspi_wait_for_completion()
530 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n"); in fsl_lpspi_wait_for_completion()
531 return -ETIMEDOUT; in fsl_lpspi_wait_for_completion()
542 if (!fsl_lpspi->usedma) { in fsl_lpspi_reset()
549 writel(temp, fsl_lpspi->base + IMX7ULP_CR); in fsl_lpspi_reset()
552 writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_reset()
561 complete(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_dma_rx_callback()
568 complete(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_dma_tx_callback()
576 /* Time with actual data transfer and CS change delay related to HW */ in fsl_lpspi_calculate_timeout()
577 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz; in fsl_lpspi_calculate_timeout()
579 /* Add extra second for scheduler related activities */ in fsl_lpspi_calculate_timeout()
593 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; in fsl_lpspi_dma_transfer()
600 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, in fsl_lpspi_dma_transfer()
601 rx->sgl, rx->nents, DMA_DEV_TO_MEM, in fsl_lpspi_dma_transfer()
604 return -EINVAL; in fsl_lpspi_dma_transfer()
606 desc_rx->callback = fsl_lpspi_dma_rx_callback; in fsl_lpspi_dma_transfer()
607 desc_rx->callback_param = (void *)fsl_lpspi; in fsl_lpspi_dma_transfer()
609 reinit_completion(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_dma_transfer()
610 dma_async_issue_pending(controller->dma_rx); in fsl_lpspi_dma_transfer()
612 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, in fsl_lpspi_dma_transfer()
613 tx->sgl, tx->nents, DMA_MEM_TO_DEV, in fsl_lpspi_dma_transfer()
616 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
617 return -EINVAL; in fsl_lpspi_dma_transfer()
620 desc_tx->callback = fsl_lpspi_dma_tx_callback; in fsl_lpspi_dma_transfer()
621 desc_tx->callback_param = (void *)fsl_lpspi; in fsl_lpspi_dma_transfer()
623 reinit_completion(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_dma_transfer()
624 dma_async_issue_pending(controller->dma_tx); in fsl_lpspi_dma_transfer()
626 fsl_lpspi->target_aborted = false; in fsl_lpspi_dma_transfer()
628 if (!fsl_lpspi->is_target) { in fsl_lpspi_dma_transfer()
630 transfer->len); in fsl_lpspi_dma_transfer()
633 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion, in fsl_lpspi_dma_transfer()
636 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n"); in fsl_lpspi_dma_transfer()
637 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
638 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
640 return -ETIMEDOUT; in fsl_lpspi_dma_transfer()
643 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion, in fsl_lpspi_dma_transfer()
646 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n"); in fsl_lpspi_dma_transfer()
647 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
648 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
650 return -ETIMEDOUT; in fsl_lpspi_dma_transfer()
653 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) || in fsl_lpspi_dma_transfer()
654 fsl_lpspi->target_aborted) { in fsl_lpspi_dma_transfer()
655 dev_dbg(fsl_lpspi->dev, in fsl_lpspi_dma_transfer()
657 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
658 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
660 return -EINTR; in fsl_lpspi_dma_transfer()
663 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) || in fsl_lpspi_dma_transfer()
664 fsl_lpspi->target_aborted) { in fsl_lpspi_dma_transfer()
665 dev_dbg(fsl_lpspi->dev, in fsl_lpspi_dma_transfer()
667 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
668 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
670 return -EINTR; in fsl_lpspi_dma_transfer()
681 if (controller->dma_rx) { in fsl_lpspi_dma_exit()
682 dma_release_channel(controller->dma_rx); in fsl_lpspi_dma_exit()
683 controller->dma_rx = NULL; in fsl_lpspi_dma_exit()
686 if (controller->dma_tx) { in fsl_lpspi_dma_exit()
687 dma_release_channel(controller->dma_tx); in fsl_lpspi_dma_exit()
688 controller->dma_tx = NULL; in fsl_lpspi_dma_exit()
699 controller->dma_tx = dma_request_chan(dev, "tx"); in fsl_lpspi_dma_init()
700 if (IS_ERR(controller->dma_tx)) { in fsl_lpspi_dma_init()
701 ret = PTR_ERR(controller->dma_tx); in fsl_lpspi_dma_init()
703 controller->dma_tx = NULL; in fsl_lpspi_dma_init()
708 controller->dma_rx = dma_request_chan(dev, "rx"); in fsl_lpspi_dma_init()
709 if (IS_ERR(controller->dma_rx)) { in fsl_lpspi_dma_init()
710 ret = PTR_ERR(controller->dma_rx); in fsl_lpspi_dma_init()
712 controller->dma_rx = NULL; in fsl_lpspi_dma_init()
716 init_completion(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_dma_init()
717 init_completion(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_dma_init()
718 controller->can_dma = fsl_lpspi_can_dma; in fsl_lpspi_dma_init()
719 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES; in fsl_lpspi_dma_init()
734 fsl_lpspi->tx_buf = t->tx_buf; in fsl_lpspi_pio_transfer()
735 fsl_lpspi->rx_buf = t->rx_buf; in fsl_lpspi_pio_transfer()
736 fsl_lpspi->remain = t->len; in fsl_lpspi_pio_transfer()
738 reinit_completion(&fsl_lpspi->xfer_done); in fsl_lpspi_pio_transfer()
739 fsl_lpspi->target_aborted = false; in fsl_lpspi_pio_transfer()
758 fsl_lpspi->is_first_byte = true; in fsl_lpspi_transfer_one()
763 t->effective_speed_hz = fsl_lpspi->config.effective_speed_hz; in fsl_lpspi_transfer_one()
766 fsl_lpspi->is_first_byte = false; in fsl_lpspi_transfer_one()
768 if (fsl_lpspi->usedma) in fsl_lpspi_transfer_one()
783 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER); in fsl_lpspi_isr()
785 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_isr()
795 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) { in fsl_lpspi_isr()
796 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_isr()
802 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_isr()
803 complete(&fsl_lpspi->xfer_done); in fsl_lpspi_isr()
819 ret = clk_prepare_enable(fsl_lpspi->clk_per); in fsl_lpspi_runtime_resume()
823 ret = clk_prepare_enable(fsl_lpspi->clk_ipg); in fsl_lpspi_runtime_resume()
825 clk_disable_unprepare(fsl_lpspi->clk_per); in fsl_lpspi_runtime_resume()
839 clk_disable_unprepare(fsl_lpspi->clk_per); in fsl_lpspi_runtime_suspend()
840 clk_disable_unprepare(fsl_lpspi->clk_ipg); in fsl_lpspi_runtime_suspend()
848 struct device *dev = fsl_lpspi->dev; in fsl_lpspi_init_rpm()
868 devtype_data = of_device_get_match_data(&pdev->dev); in fsl_lpspi_probe()
870 return -ENODEV; in fsl_lpspi_probe()
872 is_target = of_property_read_bool((&pdev->dev)->of_node, "spi-slave"); in fsl_lpspi_probe()
874 controller = devm_spi_alloc_target(&pdev->dev, in fsl_lpspi_probe()
877 controller = devm_spi_alloc_host(&pdev->dev, in fsl_lpspi_probe()
881 return -ENOMEM; in fsl_lpspi_probe()
886 fsl_lpspi->dev = &pdev->dev; in fsl_lpspi_probe()
887 fsl_lpspi->is_target = is_target; in fsl_lpspi_probe()
888 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node, in fsl_lpspi_probe()
889 "fsl,spi-only-use-cs1-sel"); in fsl_lpspi_probe()
890 fsl_lpspi->devtype_data = devtype_data; in fsl_lpspi_probe()
892 init_completion(&fsl_lpspi->xfer_done); in fsl_lpspi_probe()
894 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in fsl_lpspi_probe()
895 if (IS_ERR(fsl_lpspi->base)) { in fsl_lpspi_probe()
896 ret = PTR_ERR(fsl_lpspi->base); in fsl_lpspi_probe()
899 fsl_lpspi->base_phys = res->start; in fsl_lpspi_probe()
907 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, IRQF_NO_AUTOEN, in fsl_lpspi_probe()
908 dev_name(&pdev->dev), fsl_lpspi); in fsl_lpspi_probe()
910 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); in fsl_lpspi_probe()
914 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per"); in fsl_lpspi_probe()
915 if (IS_ERR(fsl_lpspi->clk_per)) { in fsl_lpspi_probe()
916 ret = PTR_ERR(fsl_lpspi->clk_per); in fsl_lpspi_probe()
920 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in fsl_lpspi_probe()
921 if (IS_ERR(fsl_lpspi->clk_ipg)) { in fsl_lpspi_probe()
922 ret = PTR_ERR(fsl_lpspi->clk_ipg); in fsl_lpspi_probe()
931 ret = pm_runtime_get_sync(fsl_lpspi->dev); in fsl_lpspi_probe()
933 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); in fsl_lpspi_probe()
937 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM); in fsl_lpspi_probe()
938 fsl_lpspi->txfifosize = 1 << (temp & 0x0f); in fsl_lpspi_probe()
939 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f); in fsl_lpspi_probe()
940 if (of_property_read_u32((&pdev->dev)->of_node, "num-cs", in fsl_lpspi_probe()
942 if (devtype_data->query_hw_for_num_cs) in fsl_lpspi_probe()
948 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); in fsl_lpspi_probe()
949 controller->transfer_one = fsl_lpspi_transfer_one; in fsl_lpspi_probe()
950 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; in fsl_lpspi_probe()
951 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware; in fsl_lpspi_probe()
952 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in fsl_lpspi_probe()
953 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; in fsl_lpspi_probe()
954 controller->dev.of_node = pdev->dev.of_node; in fsl_lpspi_probe()
955 controller->bus_num = pdev->id; in fsl_lpspi_probe()
956 controller->num_chipselect = num_cs; in fsl_lpspi_probe()
957 controller->target_abort = fsl_lpspi_target_abort; in fsl_lpspi_probe()
958 if (!fsl_lpspi->is_target) in fsl_lpspi_probe()
959 controller->use_gpio_descriptors = true; in fsl_lpspi_probe()
961 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller); in fsl_lpspi_probe()
962 if (ret == -EPROBE_DEFER) in fsl_lpspi_probe()
965 dev_warn(&pdev->dev, "dma setup error %d, use pio\n", ret); in fsl_lpspi_probe()
969 ret = devm_spi_register_controller(&pdev->dev, controller); in fsl_lpspi_probe()
971 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n"); in fsl_lpspi_probe()
975 pm_runtime_put_autosuspend(fsl_lpspi->dev); in fsl_lpspi_probe()
982 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev); in fsl_lpspi_probe()
983 pm_runtime_put_sync(fsl_lpspi->dev); in fsl_lpspi_probe()
984 pm_runtime_disable(fsl_lpspi->dev); in fsl_lpspi_probe()
997 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev); in fsl_lpspi_remove()
998 pm_runtime_disable(fsl_lpspi->dev); in fsl_lpspi_remove()