Lines Matching full:espi
3 * Freescale eSPI controller driver.
22 /* eSPI Controller registers */
23 #define ESPI_SPMODE 0x00 /* eSPI mode register */
24 #define ESPI_SPIE 0x04 /* eSPI event register */
25 #define ESPI_SPIM 0x08 /* eSPI mask register */
26 #define ESPI_SPCOM 0x0c /* eSPI command register */
27 #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
28 #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
29 #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
33 /* eSPI Controller mode register definitions */
39 /* eSPI Controller CS mode register definitions */
54 /* Default mode/csmode for eSPI controller */
116 static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset) in fsl_espi_read_reg() argument
118 return ioread32be(espi->reg_base + offset); in fsl_espi_read_reg()
121 static inline u16 fsl_espi_read_reg16(struct fsl_espi *espi, int offset) in fsl_espi_read_reg16() argument
123 return ioread16be(espi->reg_base + offset); in fsl_espi_read_reg16()
126 static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset) in fsl_espi_read_reg8() argument
128 return ioread8(espi->reg_base + offset); in fsl_espi_read_reg8()
131 static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset, in fsl_espi_write_reg() argument
134 iowrite32be(val, espi->reg_base + offset); in fsl_espi_write_reg()
137 static inline void fsl_espi_write_reg16(struct fsl_espi *espi, int offset, in fsl_espi_write_reg16() argument
140 iowrite16be(val, espi->reg_base + offset); in fsl_espi_write_reg16()
143 static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset, in fsl_espi_write_reg8() argument
146 iowrite8(val, espi->reg_base + offset); in fsl_espi_write_reg8()
151 struct fsl_espi *espi = spi_controller_get_devdata(m->spi->controller); in fsl_espi_check_message() local
155 dev_err(espi->dev, "message too long, size is %u bytes\n", in fsl_espi_check_message()
166 dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n"); in fsl_espi_check_message()
171 /* ESPI supports MSB-first transfers for word size 8 / 16 only */ in fsl_espi_check_message()
174 dev_err(espi->dev, in fsl_espi_check_message()
189 * prerequisites for ESPI rxskip mode: in fsl_espi_check_rxskip_mode()
214 static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events) in fsl_espi_fill_tx_fifo() argument
223 tx_left = espi->tx_t->len - espi->tx_pos; in fsl_espi_fill_tx_fifo()
224 tx_buf = espi->tx_t->tx_buf; in fsl_espi_fill_tx_fifo()
228 fsl_espi_write_reg(espi, ESPI_SPITF, 0); in fsl_espi_fill_tx_fifo()
229 else if (espi->swab) in fsl_espi_fill_tx_fifo()
230 fsl_espi_write_reg(espi, ESPI_SPITF, in fsl_espi_fill_tx_fifo()
231 swahb32p(tx_buf + espi->tx_pos)); in fsl_espi_fill_tx_fifo()
233 fsl_espi_write_reg(espi, ESPI_SPITF, in fsl_espi_fill_tx_fifo()
234 *(u32 *)(tx_buf + espi->tx_pos)); in fsl_espi_fill_tx_fifo()
235 espi->tx_pos += 4; in fsl_espi_fill_tx_fifo()
238 } else if (tx_left >= 2 && tx_buf && espi->swab) { in fsl_espi_fill_tx_fifo()
239 fsl_espi_write_reg16(espi, ESPI_SPITF, in fsl_espi_fill_tx_fifo()
240 swab16p(tx_buf + espi->tx_pos)); in fsl_espi_fill_tx_fifo()
241 espi->tx_pos += 2; in fsl_espi_fill_tx_fifo()
246 fsl_espi_write_reg8(espi, ESPI_SPITF, 0); in fsl_espi_fill_tx_fifo()
248 fsl_espi_write_reg8(espi, ESPI_SPITF, in fsl_espi_fill_tx_fifo()
249 *(u8 *)(tx_buf + espi->tx_pos)); in fsl_espi_fill_tx_fifo()
250 espi->tx_pos += 1; in fsl_espi_fill_tx_fifo()
258 if (list_is_last(&espi->tx_t->transfer_list, in fsl_espi_fill_tx_fifo()
259 espi->m_transfers) || espi->rxskip) { in fsl_espi_fill_tx_fifo()
260 espi->tx_done = true; in fsl_espi_fill_tx_fifo()
263 espi->tx_t = list_next_entry(espi->tx_t, transfer_list); in fsl_espi_fill_tx_fifo()
264 espi->tx_pos = 0; in fsl_espi_fill_tx_fifo()
271 static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events) in fsl_espi_read_rx_fifo() argument
278 rx_left = espi->rx_t->len - espi->rx_pos; in fsl_espi_read_rx_fifo()
279 rx_buf = espi->rx_t->rx_buf; in fsl_espi_read_rx_fifo()
282 u32 val = fsl_espi_read_reg(espi, ESPI_SPIRF); in fsl_espi_read_rx_fifo()
284 if (rx_buf && espi->swab) in fsl_espi_read_rx_fifo()
285 *(u32 *)(rx_buf + espi->rx_pos) = swahb32(val); in fsl_espi_read_rx_fifo()
287 *(u32 *)(rx_buf + espi->rx_pos) = val; in fsl_espi_read_rx_fifo()
288 espi->rx_pos += 4; in fsl_espi_read_rx_fifo()
291 } else if (rx_left >= 2 && rx_buf && espi->swab) { in fsl_espi_read_rx_fifo()
292 u16 val = fsl_espi_read_reg16(espi, ESPI_SPIRF); in fsl_espi_read_rx_fifo()
294 *(u16 *)(rx_buf + espi->rx_pos) = swab16(val); in fsl_espi_read_rx_fifo()
295 espi->rx_pos += 2; in fsl_espi_read_rx_fifo()
299 u8 val = fsl_espi_read_reg8(espi, ESPI_SPIRF); in fsl_espi_read_rx_fifo()
302 *(u8 *)(rx_buf + espi->rx_pos) = val; in fsl_espi_read_rx_fifo()
303 espi->rx_pos += 1; in fsl_espi_read_rx_fifo()
310 if (list_is_last(&espi->rx_t->transfer_list, in fsl_espi_read_rx_fifo()
311 espi->m_transfers)) { in fsl_espi_read_rx_fifo()
312 espi->rx_done = true; in fsl_espi_read_rx_fifo()
315 espi->rx_t = list_next_entry(espi->rx_t, transfer_list); in fsl_espi_read_rx_fifo()
316 espi->rx_pos = 0; in fsl_espi_read_rx_fifo()
326 struct fsl_espi *espi = spi_controller_get_devdata(spi->controller); in fsl_espi_setup_transfer() local
337 pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1; in fsl_espi_setup_transfer()
341 pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1; in fsl_espi_setup_transfer()
348 fsl_espi_write_reg(espi, ESPI_SPMODEx(spi_get_chipselect(spi, 0)), in fsl_espi_setup_transfer()
354 struct fsl_espi *espi = spi_controller_get_devdata(spi->controller); in fsl_espi_bufs() local
359 reinit_completion(&espi->done); in fsl_espi_bufs()
366 if (espi->rxskip) { in fsl_espi_bufs()
367 spcom |= SPCOM_RXSKIP(espi->rxskip); in fsl_espi_bufs()
368 rx_len = t->len - espi->rxskip; in fsl_espi_bufs()
373 fsl_espi_write_reg(espi, ESPI_SPCOM, spcom); in fsl_espi_bufs()
379 fsl_espi_write_reg(espi, ESPI_SPIM, mask); in fsl_espi_bufs()
382 spin_lock_irq(&espi->lock); in fsl_espi_bufs()
383 fsl_espi_fill_tx_fifo(espi, 0); in fsl_espi_bufs()
384 spin_unlock_irq(&espi->lock); in fsl_espi_bufs()
387 ret = wait_for_completion_timeout(&espi->done, 2 * HZ); in fsl_espi_bufs()
389 dev_err(espi->dev, "Transfer timed out!\n"); in fsl_espi_bufs()
392 fsl_espi_write_reg(espi, ESPI_SPIM, 0); in fsl_espi_bufs()
399 struct fsl_espi *espi = spi_controller_get_devdata(m->spi->controller); in fsl_espi_trans() local
404 espi->swab = spi->mode & SPI_LSB_FIRST && trans->bits_per_word > 8; in fsl_espi_trans()
406 espi->m_transfers = &m->transfers; in fsl_espi_trans()
407 espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer, in fsl_espi_trans()
409 espi->tx_pos = 0; in fsl_espi_trans()
410 espi->tx_done = false; in fsl_espi_trans()
411 espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer, in fsl_espi_trans()
413 espi->rx_pos = 0; in fsl_espi_trans()
414 espi->rx_done = false; in fsl_espi_trans()
416 espi->rxskip = fsl_espi_check_rxskip_mode(m); in fsl_espi_trans()
417 if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) { in fsl_espi_trans()
418 dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n"); in fsl_espi_trans()
423 if (espi->rxskip) in fsl_espi_trans()
424 espi->rx_t = list_next_entry(espi->rx_t, transfer_list); in fsl_espi_trans()
480 struct fsl_espi *espi; in fsl_espi_setup() local
491 espi = spi_controller_get_devdata(spi->controller); in fsl_espi_setup()
493 pm_runtime_get_sync(espi->dev); in fsl_espi_setup()
495 cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi_get_chipselect(spi, 0))); in fsl_espi_setup()
508 loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE); in fsl_espi_setup()
512 fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode); in fsl_espi_setup()
516 pm_runtime_mark_last_busy(espi->dev); in fsl_espi_setup()
517 pm_runtime_put_autosuspend(espi->dev); in fsl_espi_setup()
530 static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events) in fsl_espi_cpu_irq() argument
532 if (!espi->rx_done) in fsl_espi_cpu_irq()
533 fsl_espi_read_rx_fifo(espi, events); in fsl_espi_cpu_irq()
535 if (!espi->tx_done) in fsl_espi_cpu_irq()
536 fsl_espi_fill_tx_fifo(espi, events); in fsl_espi_cpu_irq()
538 if (!espi->tx_done || !espi->rx_done) in fsl_espi_cpu_irq()
542 events = fsl_espi_read_reg(espi, ESPI_SPIE); in fsl_espi_cpu_irq()
545 dev_err(espi->dev, in fsl_espi_cpu_irq()
549 dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n"); in fsl_espi_cpu_irq()
550 dev_err(espi->dev, "SPIE_RXCNT = %d, SPIE_TXCNT = %d\n", in fsl_espi_cpu_irq()
554 complete(&espi->done); in fsl_espi_cpu_irq()
559 struct fsl_espi *espi = context_data; in fsl_espi_irq() local
562 spin_lock(&espi->lock); in fsl_espi_irq()
565 events = fsl_espi_read_reg(espi, ESPI_SPIE); in fsl_espi_irq()
566 mask = fsl_espi_read_reg(espi, ESPI_SPIM); in fsl_espi_irq()
568 spin_unlock(&espi->lock); in fsl_espi_irq()
572 dev_vdbg(espi->dev, "%s: events %x\n", __func__, events); in fsl_espi_irq()
574 fsl_espi_cpu_irq(espi, events); in fsl_espi_irq()
577 fsl_espi_write_reg(espi, ESPI_SPIE, events); in fsl_espi_irq()
579 spin_unlock(&espi->lock); in fsl_espi_irq()
588 struct fsl_espi *espi = spi_controller_get_devdata(host); in fsl_espi_runtime_suspend() local
591 regval = fsl_espi_read_reg(espi, ESPI_SPMODE); in fsl_espi_runtime_suspend()
593 fsl_espi_write_reg(espi, ESPI_SPMODE, regval); in fsl_espi_runtime_suspend()
601 struct fsl_espi *espi = spi_controller_get_devdata(host); in fsl_espi_runtime_resume() local
604 regval = fsl_espi_read_reg(espi, ESPI_SPMODE); in fsl_espi_runtime_resume()
606 fsl_espi_write_reg(espi, ESPI_SPMODE, regval); in fsl_espi_runtime_resume()
620 struct fsl_espi *espi = spi_controller_get_devdata(host); in fsl_espi_init_regs() local
626 fsl_espi_write_reg(espi, ESPI_SPMODE, 0); in fsl_espi_init_regs()
627 fsl_espi_write_reg(espi, ESPI_SPIM, 0); in fsl_espi_init_regs()
628 fsl_espi_write_reg(espi, ESPI_SPCOM, 0); in fsl_espi_init_regs()
629 fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff); in fsl_espi_init_regs()
631 /* Init eSPI CS mode register */ in fsl_espi_init_regs()
654 fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode); in fsl_espi_init_regs()
661 fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE); in fsl_espi_init_regs()
668 struct fsl_espi *espi; in fsl_espi_probe() local
688 espi = spi_controller_get_devdata(host); in fsl_espi_probe()
689 spin_lock_init(&espi->lock); in fsl_espi_probe()
691 espi->dev = dev; in fsl_espi_probe()
692 espi->spibrg = fsl_get_sys_freq(); in fsl_espi_probe()
693 if (espi->spibrg == -1) { in fsl_espi_probe()
699 host->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16); in fsl_espi_probe()
700 host->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4); in fsl_espi_probe()
702 init_completion(&espi->done); in fsl_espi_probe()
704 espi->reg_base = devm_ioremap_resource(dev, mem); in fsl_espi_probe()
705 if (IS_ERR(espi->reg_base)) { in fsl_espi_probe()
706 ret = PTR_ERR(espi->reg_base); in fsl_espi_probe()
711 ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi); in fsl_espi_probe()
749 ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs); in of_fsl_espi_get_chipselects()
751 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); in of_fsl_espi_get_chipselects()
767 dev_err(dev, "mode property is not supported on ESPI!\n"); in of_fsl_espi_probe()
826 { .compatible = "fsl,mpc8536-espi" },