142 	int (*dma_init)(struct device *dev, struct dw_spi *dws);
143 	void (*dma_exit)(struct dw_spi *dws);
144 	int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
147 	int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
148 	void (*dma_stop)(struct dw_spi *dws);
179 	irqreturn_t		(*transfer_handler)(struct dw_spi *dws);
205 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)  in dw_readl()  argument
207 	return __raw_readl(dws->regs + offset);  in dw_readl()
210 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)  in dw_writel()  argument
212 	__raw_writel(val, dws->regs + offset);  in dw_writel()
215 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)  in dw_read_io_reg()  argument
217 	switch (dws->reg_io_width) {  in dw_read_io_reg()
219 		return readw_relaxed(dws->regs + offset);  in dw_read_io_reg()
222 		return readl_relaxed(dws->regs + offset);  in dw_read_io_reg()
226 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)  in dw_write_io_reg()  argument
228 	switch (dws->reg_io_width) {  in dw_write_io_reg()
230 		writew_relaxed(val, dws->regs + offset);  in dw_write_io_reg()
234 		writel_relaxed(val, dws->regs + offset);  in dw_write_io_reg()
239 static inline void dw_spi_enable_chip(struct dw_spi *dws, int enable)  in dw_spi_enable_chip()  argument
241 	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));  in dw_spi_enable_chip()
244 static inline void dw_spi_set_clk(struct dw_spi *dws, u16 div)  in dw_spi_set_clk()  argument
246 	dw_writel(dws, DW_SPI_BAUDR, div);  in dw_spi_set_clk()
250 static inline void dw_spi_mask_intr(struct dw_spi *dws, u32 mask)  in dw_spi_mask_intr()  argument
254 	new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;  in dw_spi_mask_intr()
255 	dw_writel(dws, DW_SPI_IMR, new_mask);  in dw_spi_mask_intr()
259 static inline void dw_spi_umask_intr(struct dw_spi *dws, u32 mask)  in dw_spi_umask_intr()  argument
263 	new_mask = dw_readl(dws, DW_SPI_IMR) | mask;  in dw_spi_umask_intr()
264 	dw_writel(dws, DW_SPI_IMR, new_mask);  in dw_spi_umask_intr()
272 static inline void dw_spi_reset_chip(struct dw_spi *dws)  in dw_spi_reset_chip()  argument
274 	dw_spi_enable_chip(dws, 0);  in dw_spi_reset_chip()
275 	dw_spi_mask_intr(dws, 0xff);  in dw_spi_reset_chip()
276 	dw_readl(dws, DW_SPI_ICR);  in dw_spi_reset_chip()
277 	dw_writel(dws, DW_SPI_SER, 0);  in dw_spi_reset_chip()
278 	dw_spi_enable_chip(dws, 1);  in dw_spi_reset_chip()
281 static inline void dw_spi_shutdown_chip(struct dw_spi *dws)  in dw_spi_shutdown_chip()  argument
283 	dw_spi_enable_chip(dws, 0);  in dw_spi_shutdown_chip()
284 	dw_spi_set_clk(dws, 0);  in dw_spi_shutdown_chip()
288 extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
290 extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
291 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
292 extern void dw_spi_remove_host(struct dw_spi *dws);
293 extern int dw_spi_suspend_host(struct dw_spi *dws);
294 extern int dw_spi_resume_host(struct dw_spi *dws);
298 extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
299 extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
303 static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}  in dw_spi_dma_setup_mfld()  argument
304 static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}  in dw_spi_dma_setup_generic()  argument