Lines Matching refs:dws
37 static void dw_spi_dma_maxburst_init(struct dw_spi *dws) in dw_spi_dma_maxburst_init() argument
43 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
45 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
51 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
52 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); in dw_spi_dma_maxburst_init()
54 ret = dma_get_slave_caps(dws->txchan, &caps); in dw_spi_dma_maxburst_init()
71 dws->txburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
72 dw_writel(dws, DW_SPI_DMATDLR, dws->txburst); in dw_spi_dma_maxburst_init()
75 static int dw_spi_dma_caps_init(struct dw_spi *dws) in dw_spi_dma_caps_init() argument
80 ret = dma_get_slave_caps(dws->txchan, &tx); in dw_spi_dma_caps_init()
84 ret = dma_get_slave_caps(dws->rxchan, &rx); in dw_spi_dma_caps_init()
93 dws->dma_sg_burst = min(tx.max_sg_burst, rx.max_sg_burst); in dw_spi_dma_caps_init()
95 dws->dma_sg_burst = tx.max_sg_burst; in dw_spi_dma_caps_init()
97 dws->dma_sg_burst = rx.max_sg_burst; in dw_spi_dma_caps_init()
99 dws->dma_sg_burst = 0; in dw_spi_dma_caps_init()
106 dws->dma_addr_widths = tx.dst_addr_widths & rx.src_addr_widths; in dw_spi_dma_caps_init()
111 static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws) in dw_spi_dma_init_mfld() argument
132 dws->rxchan = dma_request_channel(mask, dw_spi_dma_chan_filter, rx); in dw_spi_dma_init_mfld()
133 if (!dws->rxchan) in dw_spi_dma_init_mfld()
138 dws->txchan = dma_request_channel(mask, dw_spi_dma_chan_filter, tx); in dw_spi_dma_init_mfld()
139 if (!dws->txchan) in dw_spi_dma_init_mfld()
142 dws->host->dma_rx = dws->rxchan; in dw_spi_dma_init_mfld()
143 dws->host->dma_tx = dws->txchan; in dw_spi_dma_init_mfld()
145 init_completion(&dws->dma_completion); in dw_spi_dma_init_mfld()
147 ret = dw_spi_dma_caps_init(dws); in dw_spi_dma_init_mfld()
151 dw_spi_dma_maxburst_init(dws); in dw_spi_dma_init_mfld()
158 dma_release_channel(dws->txchan); in dw_spi_dma_init_mfld()
159 dws->txchan = NULL; in dw_spi_dma_init_mfld()
161 dma_release_channel(dws->rxchan); in dw_spi_dma_init_mfld()
162 dws->rxchan = NULL; in dw_spi_dma_init_mfld()
168 static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws) in dw_spi_dma_init_generic() argument
172 dws->rxchan = dma_request_chan(dev, "rx"); in dw_spi_dma_init_generic()
173 if (IS_ERR(dws->rxchan)) { in dw_spi_dma_init_generic()
174 ret = PTR_ERR(dws->rxchan); in dw_spi_dma_init_generic()
175 dws->rxchan = NULL; in dw_spi_dma_init_generic()
179 dws->txchan = dma_request_chan(dev, "tx"); in dw_spi_dma_init_generic()
180 if (IS_ERR(dws->txchan)) { in dw_spi_dma_init_generic()
181 ret = PTR_ERR(dws->txchan); in dw_spi_dma_init_generic()
182 dws->txchan = NULL; in dw_spi_dma_init_generic()
186 dws->host->dma_rx = dws->rxchan; in dw_spi_dma_init_generic()
187 dws->host->dma_tx = dws->txchan; in dw_spi_dma_init_generic()
189 init_completion(&dws->dma_completion); in dw_spi_dma_init_generic()
191 ret = dw_spi_dma_caps_init(dws); in dw_spi_dma_init_generic()
195 dw_spi_dma_maxburst_init(dws); in dw_spi_dma_init_generic()
200 dma_release_channel(dws->txchan); in dw_spi_dma_init_generic()
201 dws->txchan = NULL; in dw_spi_dma_init_generic()
203 dma_release_channel(dws->rxchan); in dw_spi_dma_init_generic()
204 dws->rxchan = NULL; in dw_spi_dma_init_generic()
209 static void dw_spi_dma_exit(struct dw_spi *dws) in dw_spi_dma_exit() argument
211 if (dws->txchan) { in dw_spi_dma_exit()
212 dmaengine_terminate_sync(dws->txchan); in dw_spi_dma_exit()
213 dma_release_channel(dws->txchan); in dw_spi_dma_exit()
216 if (dws->rxchan) { in dw_spi_dma_exit()
217 dmaengine_terminate_sync(dws->rxchan); in dw_spi_dma_exit()
218 dma_release_channel(dws->rxchan); in dw_spi_dma_exit()
222 static irqreturn_t dw_spi_dma_transfer_handler(struct dw_spi *dws) in dw_spi_dma_transfer_handler() argument
224 dw_spi_check_status(dws, false); in dw_spi_dma_transfer_handler()
226 complete(&dws->dma_completion); in dw_spi_dma_transfer_handler()
248 struct dw_spi *dws = spi_controller_get_devdata(host); in dw_spi_can_dma() local
251 if (xfer->len <= dws->fifo_len) in dw_spi_can_dma()
254 dma_bus_width = dw_spi_dma_convert_width(dws->n_bytes); in dw_spi_can_dma()
256 return dws->dma_addr_widths & BIT(dma_bus_width); in dw_spi_can_dma()
259 static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed) in dw_spi_dma_wait() argument
270 ms = wait_for_completion_timeout(&dws->dma_completion, in dw_spi_dma_wait()
274 dev_err(&dws->host->cur_msg->spi->dev, in dw_spi_dma_wait()
282 static inline bool dw_spi_dma_tx_busy(struct dw_spi *dws) in dw_spi_dma_tx_busy() argument
284 return !(dw_readl(dws, DW_SPI_SR) & DW_SPI_SR_TF_EMPT); in dw_spi_dma_tx_busy()
287 static int dw_spi_dma_wait_tx_done(struct dw_spi *dws, in dw_spi_dma_wait_tx_done() argument
294 nents = dw_readl(dws, DW_SPI_TXFLR); in dw_spi_dma_wait_tx_done()
296 delay.value = nents * dws->n_bytes * BITS_PER_BYTE; in dw_spi_dma_wait_tx_done()
298 while (dw_spi_dma_tx_busy(dws) && retry--) in dw_spi_dma_wait_tx_done()
302 dev_err(&dws->host->dev, "Tx hanged up\n"); in dw_spi_dma_wait_tx_done()
315 struct dw_spi *dws = arg; in dw_spi_dma_tx_done() local
317 clear_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_tx_done()
318 if (test_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy)) in dw_spi_dma_tx_done()
321 complete(&dws->dma_completion); in dw_spi_dma_tx_done()
324 static int dw_spi_dma_config_tx(struct dw_spi *dws) in dw_spi_dma_config_tx() argument
330 txconf.dst_addr = dws->dma_addr; in dw_spi_dma_config_tx()
331 txconf.dst_maxburst = dws->txburst; in dw_spi_dma_config_tx()
333 txconf.dst_addr_width = dw_spi_dma_convert_width(dws->n_bytes); in dw_spi_dma_config_tx()
336 return dmaengine_slave_config(dws->txchan, &txconf); in dw_spi_dma_config_tx()
339 static int dw_spi_dma_submit_tx(struct dw_spi *dws, struct scatterlist *sgl, in dw_spi_dma_submit_tx() argument
346 txdesc = dmaengine_prep_slave_sg(dws->txchan, sgl, nents, in dw_spi_dma_submit_tx()
353 txdesc->callback_param = dws; in dw_spi_dma_submit_tx()
358 dmaengine_terminate_sync(dws->txchan); in dw_spi_dma_submit_tx()
362 set_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_submit_tx()
367 static inline bool dw_spi_dma_rx_busy(struct dw_spi *dws) in dw_spi_dma_rx_busy() argument
369 return !!(dw_readl(dws, DW_SPI_SR) & DW_SPI_SR_RF_NOT_EMPT); in dw_spi_dma_rx_busy()
372 static int dw_spi_dma_wait_rx_done(struct dw_spi *dws) in dw_spi_dma_wait_rx_done() argument
388 nents = dw_readl(dws, DW_SPI_RXFLR); in dw_spi_dma_wait_rx_done()
389 ns = 4U * NSEC_PER_SEC / dws->max_freq * nents; in dw_spi_dma_wait_rx_done()
399 while (dw_spi_dma_rx_busy(dws) && retry--) in dw_spi_dma_wait_rx_done()
403 dev_err(&dws->host->dev, "Rx hanged up\n"); in dw_spi_dma_wait_rx_done()
416 struct dw_spi *dws = arg; in dw_spi_dma_rx_done() local
418 clear_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_rx_done()
419 if (test_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy)) in dw_spi_dma_rx_done()
422 complete(&dws->dma_completion); in dw_spi_dma_rx_done()
425 static int dw_spi_dma_config_rx(struct dw_spi *dws) in dw_spi_dma_config_rx() argument
431 rxconf.src_addr = dws->dma_addr; in dw_spi_dma_config_rx()
432 rxconf.src_maxburst = dws->rxburst; in dw_spi_dma_config_rx()
434 rxconf.src_addr_width = dw_spi_dma_convert_width(dws->n_bytes); in dw_spi_dma_config_rx()
437 return dmaengine_slave_config(dws->rxchan, &rxconf); in dw_spi_dma_config_rx()
440 static int dw_spi_dma_submit_rx(struct dw_spi *dws, struct scatterlist *sgl, in dw_spi_dma_submit_rx() argument
447 rxdesc = dmaengine_prep_slave_sg(dws->rxchan, sgl, nents, in dw_spi_dma_submit_rx()
454 rxdesc->callback_param = dws; in dw_spi_dma_submit_rx()
459 dmaengine_terminate_sync(dws->rxchan); in dw_spi_dma_submit_rx()
463 set_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_submit_rx()
468 static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer) in dw_spi_dma_setup() argument
477 ret = dw_spi_dma_config_tx(dws); in dw_spi_dma_setup()
482 ret = dw_spi_dma_config_rx(dws); in dw_spi_dma_setup()
491 dw_writel(dws, DW_SPI_DMACR, dma_ctrl); in dw_spi_dma_setup()
497 dw_spi_umask_intr(dws, imr); in dw_spi_dma_setup()
499 reinit_completion(&dws->dma_completion); in dw_spi_dma_setup()
501 dws->transfer_handler = dw_spi_dma_transfer_handler; in dw_spi_dma_setup()
506 static int dw_spi_dma_transfer_all(struct dw_spi *dws, in dw_spi_dma_transfer_all() argument
512 ret = dw_spi_dma_submit_tx(dws, xfer->tx_sg.sgl, xfer->tx_sg.nents); in dw_spi_dma_transfer_all()
518 ret = dw_spi_dma_submit_rx(dws, xfer->rx_sg.sgl, in dw_spi_dma_transfer_all()
524 dma_async_issue_pending(dws->rxchan); in dw_spi_dma_transfer_all()
527 dma_async_issue_pending(dws->txchan); in dw_spi_dma_transfer_all()
529 ret = dw_spi_dma_wait(dws, xfer->len, xfer->effective_speed_hz); in dw_spi_dma_transfer_all()
532 dw_writel(dws, DW_SPI_DMACR, 0); in dw_spi_dma_transfer_all()
569 static int dw_spi_dma_transfer_one(struct dw_spi *dws, in dw_spi_dma_transfer_one() argument
601 ret = dw_spi_dma_submit_tx(dws, &tx_tmp, 1); in dw_spi_dma_transfer_one()
606 ret = dw_spi_dma_submit_rx(dws, &rx_tmp, 1); in dw_spi_dma_transfer_one()
611 dma_async_issue_pending(dws->rxchan); in dw_spi_dma_transfer_one()
613 dma_async_issue_pending(dws->txchan); in dw_spi_dma_transfer_one()
621 ret = dw_spi_dma_wait(dws, len, xfer->effective_speed_hz); in dw_spi_dma_transfer_one()
625 reinit_completion(&dws->dma_completion); in dw_spi_dma_transfer_one()
633 dw_writel(dws, DW_SPI_DMACR, 0); in dw_spi_dma_transfer_one()
638 static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer) in dw_spi_dma_transfer() argument
652 if (!dws->dma_sg_burst || !xfer->rx_buf || nents <= dws->dma_sg_burst) in dw_spi_dma_transfer()
653 ret = dw_spi_dma_transfer_all(dws, xfer); in dw_spi_dma_transfer()
655 ret = dw_spi_dma_transfer_one(dws, xfer); in dw_spi_dma_transfer()
659 if (dws->host->cur_msg->status == -EINPROGRESS) { in dw_spi_dma_transfer()
660 ret = dw_spi_dma_wait_tx_done(dws, xfer); in dw_spi_dma_transfer()
665 if (xfer->rx_buf && dws->host->cur_msg->status == -EINPROGRESS) in dw_spi_dma_transfer()
666 ret = dw_spi_dma_wait_rx_done(dws); in dw_spi_dma_transfer()
671 static void dw_spi_dma_stop(struct dw_spi *dws) in dw_spi_dma_stop() argument
673 if (test_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy)) { in dw_spi_dma_stop()
674 dmaengine_terminate_sync(dws->txchan); in dw_spi_dma_stop()
675 clear_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_stop()
677 if (test_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy)) { in dw_spi_dma_stop()
678 dmaengine_terminate_sync(dws->rxchan); in dw_spi_dma_stop()
679 clear_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_stop()
692 void dw_spi_dma_setup_mfld(struct dw_spi *dws) in dw_spi_dma_setup_mfld() argument
694 dws->dma_ops = &dw_spi_dma_mfld_ops; in dw_spi_dma_setup_mfld()
707 void dw_spi_dma_setup_generic(struct dw_spi *dws) in dw_spi_dma_setup_generic() argument
709 dws->dma_ops = &dw_spi_dma_generic_ops; in dw_spi_dma_setup_generic()