Lines Matching refs:cr0
31 u32 cr0; member
270 u32 cr0 = 0; in dw_spi_prepare_cr0() local
274 cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_FRF_MASK, DW_SPI_CTRLR0_FRF_MOTO_SPI); in dw_spi_prepare_cr0()
282 cr0 |= DW_PSSI_CTRLR0_SCPOL; in dw_spi_prepare_cr0()
284 cr0 |= DW_PSSI_CTRLR0_SCPHA; in dw_spi_prepare_cr0()
288 cr0 |= DW_PSSI_CTRLR0_SRL; in dw_spi_prepare_cr0()
291 cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_FRF_MASK, DW_SPI_CTRLR0_FRF_MOTO_SPI); in dw_spi_prepare_cr0()
299 cr0 |= DW_HSSI_CTRLR0_SCPOL; in dw_spi_prepare_cr0()
301 cr0 |= DW_HSSI_CTRLR0_SCPHA; in dw_spi_prepare_cr0()
305 cr0 |= DW_HSSI_CTRLR0_SRL; in dw_spi_prepare_cr0()
309 cr0 |= DW_HSSI_CTRLR0_MST; in dw_spi_prepare_cr0()
312 return cr0; in dw_spi_prepare_cr0()
319 u32 cr0 = chip->cr0; in dw_spi_update_config() local
324 cr0 |= (cfg->dfs - 1) << dws->dfs_offset; in dw_spi_update_config()
328 cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_TMOD_MASK, cfg->tmode); in dw_spi_update_config()
331 cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode); in dw_spi_update_config()
333 dw_writel(dws, DW_SPI_CTRLR0, cr0); in dw_spi_update_config()
805 chip->cr0 = dw_spi_prepare_cr0(dws, spi); in dw_spi_setup()
875 u32 cr0, tmp = dw_readl(dws, DW_SPI_CTRLR0); in dw_spi_hw_init() local
879 cr0 = dw_readl(dws, DW_SPI_CTRLR0); in dw_spi_hw_init()
883 if (!(cr0 & DW_PSSI_CTRLR0_DFS_MASK)) { in dw_spi_hw_init()