Lines Matching defs:transfer

97 	 * proceed with data transfer. So in order to activate the SPI
226 	 * final stage of the transfer. By doing so we'll get the next IRQ
240 	 * have the TXE IRQ flood at the final stage of the transfer.
366 	 * will be adjusted at the final stage of the IRQ-based SPI transfer
381  * The iterative procedure of the poll-based transfer is simple: write as much
386  * Note this method the same way as the IRQ-based transfer won't work well for
391 				struct spi_transfer *transfer)
404 		spi_delay_exec(&delay, transfer);
418 			       struct spi_transfer *transfer)
423 		.dfs = transfer->bits_per_word,
424 		.freq = transfer->speed_hz,
429 	dws->n_bytes = spi_bpw_to_bytes(transfer->bits_per_word);
430 	dws->tx = (void *)transfer->tx_buf;
431 	dws->tx_len = transfer->len / dws->n_bytes;
432 	dws->rx = transfer->rx_buf;
442 	transfer->effective_speed_hz = dws->current_freq;
444 	/* Check if current transfer is a DMA transaction */
445 	dws->dma_mapped = spi_xfer_is_dma_mapped(ctlr, spi, transfer);
451 		ret = dws->dma_ops->dma_setup(dws, transfer);
459 		return dws->dma_ops->dma_transfer(dws, transfer);
461 		return dw_spi_poll_transfer(dws, transfer);
515 	 * Calculate the total length of the EEPROM command transfer and
532 	 * buffer. If it's a transfer with data to be sent, also copy it into the
719 	 * fatal, since the transfer procedure preemption may cause the Tx FIFO
721 	 * transfer will most likely cause the data loss. Secondly the
722 	 * EEPROM-read or Read-only DW SPI transfer modes imply the incoming
734 	 * here just won't keep up with the SPI bus data transfer. Such
752 	 * would be due to an error detected on the data transfer.