Lines Matching +full:zynqmp +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
27 #include <linux/reset.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
324 if (ret != -ETIMEDOUT) in cqspi_wait_for_bit()
327 timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US; in cqspi_wait_for_bit()
337 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
344 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); in cqspi_get_rd_sram_level()
354 dma_status = readl(cqspi->iobase + in cqspi_get_versal_dma_status()
356 writel(dma_status, cqspi->iobase + in cqspi_get_versal_dma_status()
365 const struct cqspi_driver_platdata *ddata = cqspi->ddata; in cqspi_irq_handler()
369 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
372 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
374 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { in cqspi_irq_handler()
375 if (ddata->get_dma_status(cqspi)) { in cqspi_irq_handler()
376 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
381 else if (!cqspi->slow_sram) in cqspi_irq_handler()
387 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
396 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; in cqspi_calc_rdreg()
397 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; in cqspi_calc_rdreg()
398 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; in cqspi_calc_rdreg()
407 if (!op->dummy.nbytes) in cqspi_calc_dummy()
410 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); in cqspi_calc_dummy()
411 if (op->cmd.dtr) in cqspi_calc_dummy()
440 dev_err(&cqspi->pdev->dev, in cqspi_wait_idle()
443 return -ETIMEDOUT; in cqspi_wait_idle()
452 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd()
462 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL, in cqspi_exec_flash_cmd()
465 dev_err(&cqspi->pdev->dev, in cqspi_exec_flash_cmd()
478 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_setup_opcode_ext()
479 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext()
483 if (op->cmd.nbytes != 2) in cqspi_setup_opcode_ext()
484 return -EINVAL; in cqspi_setup_opcode_ext()
487 ext = op->cmd.opcode & 0xff; in cqspi_setup_opcode_ext()
500 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_enable_dtr()
501 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr()
511 if (op->cmd.dtr) { in cqspi_enable_dtr()
535 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_read()
536 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read()
537 u8 *rxbuf = op->data.buf.in; in cqspi_command_read()
539 size_t n_rx = op->data.nbytes; in cqspi_command_read()
551 dev_err(&cqspi->pdev->dev, in cqspi_command_read()
554 return -EINVAL; in cqspi_command_read()
557 if (op->cmd.dtr) in cqspi_command_read()
558 opcode = op->cmd.opcode >> 8; in cqspi_command_read()
560 opcode = op->cmd.opcode; in cqspi_command_read()
569 return -EOPNOTSUPP; in cqspi_command_read()
578 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) in cqspi_command_read()
582 if (op->addr.nbytes) { in cqspi_command_read()
584 reg |= ((op->addr.nbytes - 1) & in cqspi_command_read()
588 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_read()
605 read_len = n_rx - read_len; in cqspi_command_read()
609 /* Reset CMD_CTRL Reg once command read completes */ in cqspi_command_read()
618 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_write()
619 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write()
621 const u8 *txbuf = op->data.buf.out; in cqspi_command_write()
622 size_t n_tx = op->data.nbytes; in cqspi_command_write()
633 dev_err(&cqspi->pdev->dev, in cqspi_command_write()
636 return -EINVAL; in cqspi_command_write()
642 if (op->cmd.dtr) in cqspi_command_write()
643 opcode = op->cmd.opcode >> 8; in cqspi_command_write()
645 opcode = op->cmd.opcode; in cqspi_command_write()
649 if (op->addr.nbytes) { in cqspi_command_write()
651 reg |= ((op->addr.nbytes - 1) & in cqspi_command_write()
655 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_write()
660 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) in cqspi_command_write()
670 write_len = n_tx - 4; in cqspi_command_write()
678 /* Reset CMD_CTRL Reg once command write completes */ in cqspi_command_write()
687 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read_setup()
688 void __iomem *reg_base = cqspi->iobase; in cqspi_read_setup()
698 if (op->cmd.dtr) in cqspi_read_setup()
699 opcode = op->cmd.opcode >> 8; in cqspi_read_setup()
701 opcode = op->cmd.opcode; in cqspi_read_setup()
710 return -EOPNOTSUPP; in cqspi_read_setup()
721 reg |= (op->addr.nbytes - 1); in cqspi_read_setup()
731 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_read_execute()
732 bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ); in cqspi_indirect_read_execute()
733 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_read_execute()
734 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_read_execute()
735 void __iomem *ahb_base = cqspi->ahb_base; in cqspi_indirect_read_execute()
742 if (!refcount_read(&cqspi->refcount)) in cqspi_indirect_read_execute()
743 return -ENODEV; in cqspi_indirect_read_execute()
759 if (use_irq && cqspi->slow_sram) in cqspi_indirect_read_execute()
766 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
773 !wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_read_execute()
775 ret = -ETIMEDOUT; in cqspi_indirect_read_execute()
781 if (cqspi->slow_sram) in cqspi_indirect_read_execute()
794 bytes_to_read *= cqspi->fifo_width; in cqspi_indirect_read_execute()
807 (rxbuf_end - rxbuf), in cqspi_indirect_read_execute()
811 remaining -= bytes_to_read; in cqspi_indirect_read_execute()
816 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
817 if (cqspi->slow_sram) in cqspi_indirect_read_execute()
823 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD, in cqspi_indirect_read_execute()
852 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_device_reset()
854 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_device_reset()
859 writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_device_reset()
861 writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_device_reset()
863 writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_device_reset()
869 void __iomem *reg_base = cqspi->iobase; in cqspi_controller_enable()
886 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_versal_indirect_read_dma()
887 struct device *dev = &cqspi->pdev->dev; in cqspi_versal_indirect_read_dma()
888 void __iomem *reg_base = cqspi->iobase; in cqspi_versal_indirect_read_dma()
897 bytes_to_dma = (n_rx - bytes_rem); in cqspi_versal_indirect_read_dma()
902 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); in cqspi_versal_indirect_read_dma()
908 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
910 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
917 return -ENOMEM; in cqspi_versal_indirect_read_dma()
942 writel(cqspi->trigger_address, reg_base + in cqspi_versal_indirect_read_dma()
955 reinit_completion(&cqspi->transfer_complete); in cqspi_versal_indirect_read_dma()
957 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_versal_indirect_read_dma()
959 ret = -ETIMEDOUT; in cqspi_versal_indirect_read_dma()
964 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); in cqspi_versal_indirect_read_dma()
968 cqspi->iobase + CQSPI_REG_INDIRECTRD); in cqspi_versal_indirect_read_dma()
973 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
975 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
979 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, in cqspi_versal_indirect_read_dma()
1006 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
1008 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
1010 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); in cqspi_versal_indirect_read_dma()
1020 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write_setup()
1021 void __iomem *reg_base = cqspi->iobase; in cqspi_write_setup()
1028 if (op->cmd.dtr) in cqspi_write_setup()
1029 opcode = op->cmd.opcode >> 8; in cqspi_write_setup()
1031 opcode = op->cmd.opcode; in cqspi_write_setup()
1035 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; in cqspi_write_setup()
1036 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; in cqspi_write_setup()
1044 * cypress Semper flash expect a 4-byte dummy address in the Read SR in cqspi_write_setup()
1048 * command when doing auto-HW polling. So, disable write completion in cqspi_write_setup()
1049 * polling on the controller's side. spinand and spi-nor will take in cqspi_write_setup()
1052 if (cqspi->wr_completion) { in cqspi_write_setup()
1061 cqspi->use_direct_mode_wr = false; in cqspi_write_setup()
1066 reg |= (op->addr.nbytes - 1); in cqspi_write_setup()
1076 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_write_execute()
1077 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_write_execute()
1078 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_write_execute()
1083 if (!refcount_read(&cqspi->refcount)) in cqspi_indirect_write_execute()
1084 return -ENODEV; in cqspi_indirect_write_execute()
1094 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
1106 if (cqspi->wr_delay) in cqspi_indirect_write_execute()
1107 ndelay(cqspi->wr_delay); in cqspi_indirect_write_execute()
1113 if (cqspi->apb_ahb_hazard) in cqspi_indirect_write_execute()
1124 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); in cqspi_indirect_write_execute()
1131 iowrite32(temp, cqspi->ahb_base); in cqspi_indirect_write_execute()
1135 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_write_execute()
1138 ret = -ETIMEDOUT; in cqspi_indirect_write_execute()
1142 remaining -= write_bytes; in cqspi_indirect_write_execute()
1145 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
1149 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR, in cqspi_indirect_write_execute()
1178 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_chipselect()
1179 void __iomem *reg_base = cqspi->iobase; in cqspi_chipselect()
1180 unsigned int chip_select = f_pdata->cs; in cqspi_chipselect()
1184 if (cqspi->is_decoded_cs) { in cqspi_chipselect()
1218 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_delay()
1219 void __iomem *iobase = cqspi->iobase; in cqspi_delay()
1220 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_delay()
1226 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); in cqspi_delay()
1228 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); in cqspi_delay()
1233 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); in cqspi_delay()
1234 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); in cqspi_delay()
1235 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); in cqspi_delay()
1250 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_config_baudrate_div()
1251 void __iomem *reg_base = cqspi->iobase; in cqspi_config_baudrate_div()
1255 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; in cqspi_config_baudrate_div()
1260 dev_warn(&cqspi->pdev->dev, in cqspi_config_baudrate_div()
1262 cqspi->sclk, ref_clk_hz/((div+1)*2)); in cqspi_config_baudrate_div()
1275 void __iomem *reg_base = cqspi->iobase; in cqspi_readdata_capture()
1297 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_configure()
1298 int switch_cs = (cqspi->current_cs != f_pdata->cs); in cqspi_configure()
1299 int switch_ck = (cqspi->sclk != sclk); in cqspi_configure()
1306 cqspi->current_cs = f_pdata->cs; in cqspi_configure()
1312 cqspi->sclk = sclk; in cqspi_configure()
1315 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, in cqspi_configure()
1316 f_pdata->read_delay); in cqspi_configure()
1326 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write()
1327 loff_t to = op->addr.val; in cqspi_write()
1328 size_t len = op->data.nbytes; in cqspi_write()
1329 const u_char *buf = op->data.buf.out; in cqspi_write()
1337 * Some flashes like the Cypress Semper flash expect a dummy 4-byte in cqspi_write()
1344 if (!op->cmd.dtr && cqspi->use_direct_mode && in cqspi_write()
1345 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { in cqspi_write()
1346 memcpy_toio(cqspi->ahb_base + to, buf, len); in cqspi_write()
1357 complete(&cqspi->rx_dma_complete); in cqspi_rx_dma_callback()
1363 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_direct_read_execute()
1364 struct device *dev = &cqspi->pdev->dev; in cqspi_direct_read_execute()
1366 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; in cqspi_direct_read_execute()
1373 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { in cqspi_direct_read_execute()
1374 memcpy_fromio(buf, cqspi->ahb_base + from, len); in cqspi_direct_read_execute()
1378 ddev = cqspi->rx_chan->device->dev; in cqspi_direct_read_execute()
1382 return -ENOMEM; in cqspi_direct_read_execute()
1384 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, in cqspi_direct_read_execute()
1388 ret = -EIO; in cqspi_direct_read_execute()
1392 tx->callback = cqspi_rx_dma_callback; in cqspi_direct_read_execute()
1393 tx->callback_param = cqspi; in cqspi_direct_read_execute()
1394 cookie = tx->tx_submit(tx); in cqspi_direct_read_execute()
1395 reinit_completion(&cqspi->rx_dma_complete); in cqspi_direct_read_execute()
1400 ret = -EIO; in cqspi_direct_read_execute()
1404 dma_async_issue_pending(cqspi->rx_chan); in cqspi_direct_read_execute()
1405 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, in cqspi_direct_read_execute()
1407 dmaengine_terminate_sync(cqspi->rx_chan); in cqspi_direct_read_execute()
1409 ret = -ETIMEDOUT; in cqspi_direct_read_execute()
1422 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read()
1423 const struct cqspi_driver_platdata *ddata = cqspi->ddata; in cqspi_read()
1424 loff_t from = op->addr.val; in cqspi_read()
1425 size_t len = op->data.nbytes; in cqspi_read()
1426 u_char *buf = op->data.buf.in; in cqspi_read()
1434 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) in cqspi_read()
1437 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && in cqspi_read()
1439 return ddata->indirect_read_dma(f_pdata, buf, from, len); in cqspi_read()
1446 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_mem_process()
1449 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; in cqspi_mem_process()
1450 cqspi_configure(f_pdata, op->max_freq); in cqspi_mem_process()
1452 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { in cqspi_mem_process()
1458 if (!op->addr.nbytes || in cqspi_mem_process()
1459 (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX && in cqspi_mem_process()
1460 !cqspi->disable_stig_mode)) in cqspi_mem_process()
1466 if (!op->addr.nbytes || !op->data.buf.out) in cqspi_mem_process()
1475 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_exec_mem_op()
1476 struct device *dev = &cqspi->pdev->dev; in cqspi_exec_mem_op()
1479 if (refcount_read(&cqspi->inflight_ops) == 0) in cqspi_exec_mem_op()
1480 return -ENODEV; in cqspi_exec_mem_op()
1482 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { in cqspi_exec_mem_op()
1485 dev_err(&mem->spi->dev, "resume failed with %d\n", ret); in cqspi_exec_mem_op()
1490 if (!refcount_read(&cqspi->refcount)) in cqspi_exec_mem_op()
1491 return -EBUSY; in cqspi_exec_mem_op()
1493 refcount_inc(&cqspi->inflight_ops); in cqspi_exec_mem_op()
1495 if (!refcount_read(&cqspi->refcount)) { in cqspi_exec_mem_op()
1496 if (refcount_read(&cqspi->inflight_ops)) in cqspi_exec_mem_op()
1497 refcount_dec(&cqspi->inflight_ops); in cqspi_exec_mem_op()
1498 return -EBUSY; in cqspi_exec_mem_op()
1503 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) in cqspi_exec_mem_op()
1507 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); in cqspi_exec_mem_op()
1509 if (refcount_read(&cqspi->inflight_ops) > 1) in cqspi_exec_mem_op()
1510 refcount_dec(&cqspi->inflight_ops); in cqspi_exec_mem_op()
1521 * op->dummy.dtr is required for converting nbytes into ncycles. in cqspi_supports_mem_op()
1524 all_true = op->cmd.dtr && in cqspi_supports_mem_op()
1525 (!op->addr.nbytes || op->addr.dtr) && in cqspi_supports_mem_op()
1526 (!op->dummy.nbytes || op->dummy.dtr) && in cqspi_supports_mem_op()
1527 (!op->data.nbytes || op->data.dtr); in cqspi_supports_mem_op()
1529 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && in cqspi_supports_mem_op()
1530 !op->data.dtr; in cqspi_supports_mem_op()
1533 /* Right now we only support 8-8-8 DTR mode. */ in cqspi_supports_mem_op()
1534 if (op->cmd.nbytes && op->cmd.buswidth != 8) in cqspi_supports_mem_op()
1536 if (op->addr.nbytes && op->addr.buswidth != 8) in cqspi_supports_mem_op()
1538 if (op->data.nbytes && op->data.buswidth != 8) in cqspi_supports_mem_op()
1552 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { in cqspi_of_get_flash_pdata()
1553 dev_err(&pdev->dev, "couldn't determine read-delay\n"); in cqspi_of_get_flash_pdata()
1554 return -ENXIO; in cqspi_of_get_flash_pdata()
1557 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { in cqspi_of_get_flash_pdata()
1558 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); in cqspi_of_get_flash_pdata()
1559 return -ENXIO; in cqspi_of_get_flash_pdata()
1562 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { in cqspi_of_get_flash_pdata()
1563 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); in cqspi_of_get_flash_pdata()
1564 return -ENXIO; in cqspi_of_get_flash_pdata()
1567 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { in cqspi_of_get_flash_pdata()
1568 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); in cqspi_of_get_flash_pdata()
1569 return -ENXIO; in cqspi_of_get_flash_pdata()
1572 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { in cqspi_of_get_flash_pdata()
1573 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); in cqspi_of_get_flash_pdata()
1574 return -ENXIO; in cqspi_of_get_flash_pdata()
1577 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { in cqspi_of_get_flash_pdata()
1578 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); in cqspi_of_get_flash_pdata()
1579 return -ENXIO; in cqspi_of_get_flash_pdata()
1587 struct device *dev = &cqspi->pdev->dev; in cqspi_of_get_pdata()
1588 struct device_node *np = dev->of_node; in cqspi_of_get_pdata()
1591 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); in cqspi_of_get_pdata()
1593 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { in cqspi_of_get_pdata()
1595 cqspi->fifo_depth = 0; in cqspi_of_get_pdata()
1598 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { in cqspi_of_get_pdata()
1599 dev_err(dev, "couldn't determine fifo-width\n"); in cqspi_of_get_pdata()
1600 return -ENXIO; in cqspi_of_get_pdata()
1603 if (of_property_read_u32(np, "cdns,trigger-address", in cqspi_of_get_pdata()
1604 &cqspi->trigger_address)) { in cqspi_of_get_pdata()
1605 dev_err(dev, "couldn't determine trigger-address\n"); in cqspi_of_get_pdata()
1606 return -ENXIO; in cqspi_of_get_pdata()
1609 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) in cqspi_of_get_pdata()
1610 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; in cqspi_of_get_pdata()
1612 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); in cqspi_of_get_pdata()
1614 if (!of_property_read_u32_array(np, "power-domains", id, in cqspi_of_get_pdata()
1616 cqspi->pd_dev_id = id[1]; in cqspi_of_get_pdata()
1626 writel(0, cqspi->iobase + CQSPI_REG_REMAP); in cqspi_controller_init()
1629 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); in cqspi_controller_init()
1632 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_init()
1635 writel(cqspi->trigger_address, in cqspi_controller_init()
1636 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); in cqspi_controller_init()
1638 /* Program read watermark -- 1/2 of the FIFO. */ in cqspi_controller_init()
1639 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, in cqspi_controller_init()
1640 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); in cqspi_controller_init()
1641 /* Program write watermark -- 1/8 of the FIFO. */ in cqspi_controller_init()
1642 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, in cqspi_controller_init()
1643 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); in cqspi_controller_init()
1646 if (!cqspi->use_direct_mode) { in cqspi_controller_init()
1647 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1649 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1653 if (cqspi->use_dma_read) { in cqspi_controller_init()
1654 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1656 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1662 struct device *dev = &cqspi->pdev->dev; in cqspi_controller_detect_fifo_depth()
1666 * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N in cqspi_controller_detect_fifo_depth()
1669 writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_detect_fifo_depth()
1670 reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_detect_fifo_depth()
1674 if (cqspi->fifo_depth == 0) { in cqspi_controller_detect_fifo_depth()
1675 cqspi->fifo_depth = fifo_depth; in cqspi_controller_detect_fifo_depth()
1677 } else if (fifo_depth != cqspi->fifo_depth) { in cqspi_controller_detect_fifo_depth()
1679 fifo_depth, cqspi->fifo_depth); in cqspi_controller_detect_fifo_depth()
1690 cqspi->rx_chan = dma_request_chan_by_mask(&mask); in cqspi_request_mmap_dma()
1691 if (IS_ERR(cqspi->rx_chan)) { in cqspi_request_mmap_dma()
1692 int ret = PTR_ERR(cqspi->rx_chan); in cqspi_request_mmap_dma()
1694 cqspi->rx_chan = NULL; in cqspi_request_mmap_dma()
1695 if (ret == -ENODEV) { in cqspi_request_mmap_dma()
1697 dev_info(&cqspi->pdev->dev, "No Rx DMA available\n"); in cqspi_request_mmap_dma()
1701 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); in cqspi_request_mmap_dma()
1703 init_completion(&cqspi->rx_dma_complete); in cqspi_request_mmap_dma()
1710 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_get_name()
1711 struct device *dev = &cqspi->pdev->dev; in cqspi_get_name()
1714 spi_get_chipselect(mem->spi, 0)); in cqspi_get_name()
1730 struct platform_device *pdev = cqspi->pdev; in cqspi_setup_flash()
1731 struct device *dev = &pdev->dev; in cqspi_setup_flash()
1733 int ret, cs, max_cs = -1; in cqspi_setup_flash()
1736 for_each_available_child_of_node_scoped(dev->of_node, np) { in cqspi_setup_flash()
1743 if (cs >= cqspi->num_chipselect) { in cqspi_setup_flash()
1745 return -EINVAL; in cqspi_setup_flash()
1750 f_pdata = &cqspi->f_pdata[cs]; in cqspi_setup_flash()
1751 f_pdata->cqspi = cqspi; in cqspi_setup_flash()
1752 f_pdata->cs = cs; in cqspi_setup_flash()
1761 return -ENODEV; in cqspi_setup_flash()
1764 cqspi->num_chipselect = max_cs + 1; in cqspi_setup_flash()
1777 ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); in cqspi_jh7110_clk_init()
1779 dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); in cqspi_jh7110_clk_init()
1783 cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk; in cqspi_jh7110_clk_init()
1784 cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk; in cqspi_jh7110_clk_init()
1786 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_clk_init()
1788 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); in cqspi_jh7110_clk_init()
1792 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); in cqspi_jh7110_clk_init()
1794 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); in cqspi_jh7110_clk_init()
1798 cqspi->is_jh7110 = true; in cqspi_jh7110_clk_init()
1803 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_clk_init()
1810 clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); in cqspi_jh7110_disable_clk()
1811 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_disable_clk()
1817 struct device *dev = &pdev->dev; in cqspi_probe()
1824 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); in cqspi_probe()
1826 return -ENOMEM; in cqspi_probe()
1828 host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; in cqspi_probe()
1829 host->mem_ops = &cqspi_mem_ops; in cqspi_probe()
1830 host->mem_caps = &cqspi_mem_caps; in cqspi_probe()
1831 host->dev.of_node = pdev->dev.of_node; in cqspi_probe()
1835 cqspi->pdev = pdev; in cqspi_probe()
1836 cqspi->host = host; in cqspi_probe()
1837 cqspi->is_jh7110 = false; in cqspi_probe()
1838 cqspi->ddata = ddata = of_device_get_match_data(dev); in cqspi_probe()
1845 return -ENODEV; in cqspi_probe()
1849 cqspi->clk = devm_clk_get(dev, NULL); in cqspi_probe()
1850 if (IS_ERR(cqspi->clk)) { in cqspi_probe()
1852 ret = PTR_ERR(cqspi->clk); in cqspi_probe()
1857 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); in cqspi_probe()
1858 if (IS_ERR(cqspi->iobase)) { in cqspi_probe()
1860 ret = PTR_ERR(cqspi->iobase); in cqspi_probe()
1865 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); in cqspi_probe()
1866 if (IS_ERR(cqspi->ahb_base)) { in cqspi_probe()
1868 ret = PTR_ERR(cqspi->ahb_base); in cqspi_probe()
1871 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; in cqspi_probe()
1872 cqspi->ahb_size = resource_size(res_ahb); in cqspi_probe()
1874 init_completion(&cqspi->transfer_complete); in cqspi_probe()
1879 return -ENXIO; in cqspi_probe()
1886 ret = clk_prepare_enable(cqspi->clk); in cqspi_probe()
1892 /* Obtain QSPI reset control */ in cqspi_probe()
1896 dev_err(dev, "Cannot get QSPI reset.\n"); in cqspi_probe()
1900 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); in cqspi_probe()
1903 dev_err(dev, "Cannot get QSPI OCP reset.\n"); in cqspi_probe()
1907 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { in cqspi_probe()
1911 dev_err(dev, "Cannot get QSPI REF reset.\n"); in cqspi_probe()
1924 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); in cqspi_probe()
1925 host->max_speed_hz = cqspi->master_ref_clk_hz; in cqspi_probe()
1928 cqspi->wr_completion = true; in cqspi_probe()
1931 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) in cqspi_probe()
1932 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, in cqspi_probe()
1933 cqspi->master_ref_clk_hz); in cqspi_probe()
1934 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) in cqspi_probe()
1935 host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; in cqspi_probe()
1936 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_QUAD) in cqspi_probe()
1937 host->mode_bits |= SPI_TX_QUAD; in cqspi_probe()
1938 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { in cqspi_probe()
1939 cqspi->use_direct_mode = true; in cqspi_probe()
1940 cqspi->use_direct_mode_wr = true; in cqspi_probe()
1942 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) in cqspi_probe()
1943 cqspi->use_dma_read = true; in cqspi_probe()
1944 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) in cqspi_probe()
1945 cqspi->wr_completion = false; in cqspi_probe()
1946 if (ddata->quirks & CQSPI_SLOW_SRAM) in cqspi_probe()
1947 cqspi->slow_sram = true; in cqspi_probe()
1948 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) in cqspi_probe()
1949 cqspi->apb_ahb_hazard = true; in cqspi_probe()
1951 if (ddata->jh7110_clk_init) { in cqspi_probe()
1956 if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) in cqspi_probe()
1957 cqspi->disable_stig_mode = true; in cqspi_probe()
1959 if (ddata->quirks & CQSPI_DMA_SET_MASK) { in cqspi_probe()
1960 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); in cqspi_probe()
1966 refcount_set(&cqspi->refcount, 1); in cqspi_probe()
1967 refcount_set(&cqspi->inflight_ops, 1); in cqspi_probe()
1970 pdev->name, cqspi); in cqspi_probe()
1981 cqspi->current_cs = -1; in cqspi_probe()
1982 cqspi->sclk = 0; in cqspi_probe()
1990 host->num_chipselect = cqspi->num_chipselect; in cqspi_probe()
1992 if (ddata && (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET)) in cqspi_probe()
1995 if (cqspi->use_direct_mode) { in cqspi_probe()
1997 if (ret == -EPROBE_DEFER) in cqspi_probe()
2001 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { in cqspi_probe()
2010 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); in cqspi_probe()
2014 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { in cqspi_probe()
2023 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) in cqspi_probe()
2026 if (cqspi->is_jh7110) in cqspi_probe()
2028 clk_disable_unprepare(cqspi->clk); in cqspi_probe()
2037 struct device *dev = &pdev->dev; in cqspi_remove()
2041 refcount_set(&cqspi->refcount, 0); in cqspi_remove()
2043 if (!refcount_dec_and_test(&cqspi->inflight_ops)) in cqspi_remove()
2046 spi_unregister_controller(cqspi->host); in cqspi_remove()
2049 if (cqspi->rx_chan) in cqspi_remove()
2050 dma_release_channel(cqspi->rx_chan); in cqspi_remove()
2052 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) in cqspi_remove()
2053 if (pm_runtime_get_sync(&pdev->dev) >= 0) in cqspi_remove()
2054 clk_disable(cqspi->clk); in cqspi_remove()
2056 if (cqspi->is_jh7110) in cqspi_remove()
2059 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { in cqspi_remove()
2060 pm_runtime_put_sync(&pdev->dev); in cqspi_remove()
2061 pm_runtime_disable(&pdev->dev); in cqspi_remove()
2070 clk_disable_unprepare(cqspi->clk); in cqspi_runtime_suspend()
2078 clk_prepare_enable(cqspi->clk); in cqspi_runtime_resume()
2084 cqspi->current_cs = -1; in cqspi_runtime_resume()
2085 cqspi->sclk = 0; in cqspi_runtime_resume()
2094 ret = spi_controller_suspend(cqspi->host); in cqspi_suspend()
2112 return spi_controller_resume(cqspi->host); in cqspi_resume()
2179 .compatible = "cdns,qspi-nor",
2183 .compatible = "ti,k2g-qspi",
2187 .compatible = "ti,am654-ospi",
2191 .compatible = "intel,lgm-qspi",
2195 .compatible = "xlnx,versal-ospi-1.0",
2199 .compatible = "intel,socfpga-qspi",
2203 .compatible = "starfive,jh7110-qspi",
2207 .compatible = "amd,pensando-elba-qspi",
2211 .compatible = "mobileye,eyeq5-ospi",
2215 .compatible = "amd,versal2-ospi",