Lines Matching +full:no +full:- +full:cs +full:- +full:readback
1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
72 u8 cs;
321 if (ret != -ETIMEDOUT)
324 timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US;
334 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
341 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
351 dma_status = readl(cqspi->iobase +
353 writel(dma_status, cqspi->iobase +
362 const struct cqspi_driver_platdata *ddata = cqspi->ddata;
366 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
369 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
371 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) {
372 if (ddata->get_dma_status(cqspi)) {
373 complete(&cqspi->transfer_complete);
378 else if (!cqspi->slow_sram)
384 complete(&cqspi->transfer_complete);
393 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
394 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
395 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
404 if (!op->dummy.nbytes)
407 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
408 if (op->cmd.dtr)
437 dev_err(&cqspi->pdev->dev,
440 return -ETIMEDOUT;
449 void __iomem *reg_base = cqspi->iobase;
459 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL,
462 dev_err(&cqspi->pdev->dev,
475 struct cqspi_st *cqspi = f_pdata->cqspi;
476 void __iomem *reg_base = cqspi->iobase;
480 if (op->cmd.nbytes != 2)
481 return -EINVAL;
484 ext = op->cmd.opcode & 0xff;
497 struct cqspi_st *cqspi = f_pdata->cqspi;
498 void __iomem *reg_base = cqspi->iobase;
508 if (op->cmd.dtr) {
532 struct cqspi_st *cqspi = f_pdata->cqspi;
533 void __iomem *reg_base = cqspi->iobase;
534 u8 *rxbuf = op->data.buf.in;
536 size_t n_rx = op->data.nbytes;
548 dev_err(&cqspi->pdev->dev,
551 return -EINVAL;
554 if (op->cmd.dtr)
555 opcode = op->cmd.opcode >> 8;
557 opcode = op->cmd.opcode;
566 return -EOPNOTSUPP;
575 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
579 if (op->addr.nbytes) {
581 reg |= ((op->addr.nbytes - 1) &
585 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
602 read_len = n_rx - read_len;
615 struct cqspi_st *cqspi = f_pdata->cqspi;
616 void __iomem *reg_base = cqspi->iobase;
618 const u8 *txbuf = op->data.buf.out;
619 size_t n_tx = op->data.nbytes;
630 dev_err(&cqspi->pdev->dev,
633 return -EINVAL;
639 if (op->cmd.dtr)
640 opcode = op->cmd.opcode >> 8;
642 opcode = op->cmd.opcode;
646 if (op->addr.nbytes) {
648 reg |= ((op->addr.nbytes - 1) &
652 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
657 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
667 write_len = n_tx - 4;
684 struct cqspi_st *cqspi = f_pdata->cqspi;
685 void __iomem *reg_base = cqspi->iobase;
695 if (op->cmd.dtr)
696 opcode = op->cmd.opcode >> 8;
698 opcode = op->cmd.opcode;
707 return -EOPNOTSUPP;
718 reg |= (op->addr.nbytes - 1);
727 struct cqspi_st *cqspi = f_pdata->cqspi;
728 bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ);
729 struct device *dev = &cqspi->pdev->dev;
730 void __iomem *reg_base = cqspi->iobase;
731 void __iomem *ahb_base = cqspi->ahb_base;
752 if (use_irq && cqspi->slow_sram)
759 reinit_completion(&cqspi->transfer_complete);
765 !wait_for_completion_timeout(&cqspi->transfer_complete,
767 ret = -ETIMEDOUT;
773 if (cqspi->slow_sram)
779 dev_err(dev, "Indirect read timeout, no bytes\n");
786 bytes_to_read *= cqspi->fifo_width;
799 (rxbuf_end - rxbuf),
803 remaining -= bytes_to_read;
808 reinit_completion(&cqspi->transfer_complete);
809 if (cqspi->slow_sram)
815 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD,
844 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
846 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
851 writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);
853 writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);
855 writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);
861 void __iomem *reg_base = cqspi->iobase;
878 struct cqspi_st *cqspi = f_pdata->cqspi;
879 struct device *dev = &cqspi->pdev->dev;
880 void __iomem *reg_base = cqspi->iobase;
889 bytes_to_dma = (n_rx - bytes_rem);
894 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA);
900 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
902 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
909 return -ENOMEM;
934 writel(cqspi->trigger_address, reg_base +
947 reinit_completion(&cqspi->transfer_complete);
949 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
951 ret = -ETIMEDOUT;
956 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
960 cqspi->iobase + CQSPI_REG_INDIRECTRD);
965 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
967 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
971 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
998 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1000 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1002 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR);
1012 struct cqspi_st *cqspi = f_pdata->cqspi;
1013 void __iomem *reg_base = cqspi->iobase;
1020 if (op->cmd.dtr)
1021 opcode = op->cmd.opcode >> 8;
1023 opcode = op->cmd.opcode;
1027 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
1028 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
1036 * cypress Semper flash expect a 4-byte dummy address in the Read SR
1040 * command when doing auto-HW polling. So, disable write completion
1041 * polling on the controller's side. spinand and spi-nor will take
1044 if (cqspi->wr_completion) {
1053 cqspi->use_direct_mode_wr = false;
1058 reg |= (op->addr.nbytes - 1);
1067 struct cqspi_st *cqspi = f_pdata->cqspi;
1068 struct device *dev = &cqspi->pdev->dev;
1069 void __iomem *reg_base = cqspi->iobase;
1082 reinit_completion(&cqspi->transfer_complete);
1092 if (cqspi->wr_delay)
1093 ndelay(cqspi->wr_delay);
1097 * dummy readback from the controller to ensure synchronization.
1099 if (cqspi->apb_ahb_hazard)
1110 iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
1117 iowrite32(temp, cqspi->ahb_base);
1121 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
1124 ret = -ETIMEDOUT;
1128 remaining -= write_bytes;
1131 reinit_completion(&cqspi->transfer_complete);
1135 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR,
1164 struct cqspi_st *cqspi = f_pdata->cqspi;
1165 void __iomem *reg_base = cqspi->iobase;
1166 unsigned int chip_select = f_pdata->cs;
1170 if (cqspi->is_decoded_cs) {
1175 /* Convert CS if without decoder.
1204 struct cqspi_st *cqspi = f_pdata->cqspi;
1205 void __iomem *iobase = cqspi->iobase;
1206 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1212 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
1214 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
1219 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
1220 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
1221 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
1236 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1237 void __iomem *reg_base = cqspi->iobase;
1241 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
1246 dev_warn(&cqspi->pdev->dev,
1248 cqspi->sclk, ref_clk_hz/((div+1)*2));
1261 void __iomem *reg_base = cqspi->iobase;
1283 struct cqspi_st *cqspi = f_pdata->cqspi;
1284 int switch_cs = (cqspi->current_cs != f_pdata->cs);
1285 int switch_ck = (cqspi->sclk != sclk);
1292 cqspi->current_cs = f_pdata->cs;
1298 cqspi->sclk = sclk;
1301 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
1302 f_pdata->read_delay);
1312 struct cqspi_st *cqspi = f_pdata->cqspi;
1313 loff_t to = op->addr.val;
1314 size_t len = op->data.nbytes;
1315 const u_char *buf = op->data.buf.out;
1323 * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1330 if (!op->cmd.dtr && cqspi->use_direct_mode &&
1331 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
1332 memcpy_toio(cqspi->ahb_base + to, buf, len);
1343 complete(&cqspi->rx_dma_complete);
1349 struct cqspi_st *cqspi = f_pdata->cqspi;
1350 struct device *dev = &cqspi->pdev->dev;
1352 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
1359 if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
1360 memcpy_fromio(buf, cqspi->ahb_base + from, len);
1364 ddev = cqspi->rx_chan->device->dev;
1368 return -ENOMEM;
1370 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1374 ret = -EIO;
1378 tx->callback = cqspi_rx_dma_callback;
1379 tx->callback_param = cqspi;
1380 cookie = tx->tx_submit(tx);
1381 reinit_completion(&cqspi->rx_dma_complete);
1386 ret = -EIO;
1390 dma_async_issue_pending(cqspi->rx_chan);
1391 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1393 dmaengine_terminate_sync(cqspi->rx_chan);
1395 ret = -ETIMEDOUT;
1408 struct cqspi_st *cqspi = f_pdata->cqspi;
1409 const struct cqspi_driver_platdata *ddata = cqspi->ddata;
1410 loff_t from = op->addr.val;
1411 size_t len = op->data.nbytes;
1412 u_char *buf = op->data.buf.in;
1420 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1423 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
1425 return ddata->indirect_read_dma(f_pdata, buf, from, len);
1432 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1435 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)];
1436 cqspi_configure(f_pdata, op->max_freq);
1438 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
1444 if (!op->addr.nbytes ||
1445 (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX &&
1446 !cqspi->disable_stig_mode))
1452 if (!op->addr.nbytes || !op->data.buf.out)
1461 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1462 struct device *dev = &cqspi->pdev->dev;
1466 dev_err(&mem->spi->dev, "resume failed with %d\n", ret);
1476 dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
1487 * op->dummy.dtr is required for converting nbytes into ncycles.
1490 all_true = op->cmd.dtr &&
1491 (!op->addr.nbytes || op->addr.dtr) &&
1492 (!op->dummy.nbytes || op->dummy.dtr) &&
1493 (!op->data.nbytes || op->data.dtr);
1495 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
1496 !op->data.dtr;
1499 /* Right now we only support 8-8-8 DTR mode. */
1500 if (op->cmd.nbytes && op->cmd.buswidth != 8)
1502 if (op->addr.nbytes && op->addr.buswidth != 8)
1504 if (op->data.nbytes && op->data.buswidth != 8)
1518 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1519 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1520 return -ENXIO;
1523 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1524 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1525 return -ENXIO;
1528 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1529 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1530 return -ENXIO;
1533 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1534 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1535 return -ENXIO;
1538 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1539 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1540 return -ENXIO;
1543 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1544 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1545 return -ENXIO;
1553 struct device *dev = &cqspi->pdev->dev;
1554 struct device_node *np = dev->of_node;
1557 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1559 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1561 cqspi->fifo_depth = 0;
1564 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1565 dev_err(dev, "couldn't determine fifo-width\n");
1566 return -ENXIO;
1569 if (of_property_read_u32(np, "cdns,trigger-address",
1570 &cqspi->trigger_address)) {
1571 dev_err(dev, "couldn't determine trigger-address\n");
1572 return -ENXIO;
1575 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1576 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1578 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1580 if (!of_property_read_u32_array(np, "power-domains", id,
1582 cqspi->pd_dev_id = id[1];
1591 /* Configure the remap address register, no remap */
1592 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1595 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1598 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1601 writel(cqspi->trigger_address,
1602 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1604 /* Program read watermark -- 1/2 of the FIFO. */
1605 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1606 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1607 /* Program write watermark -- 1/8 of the FIFO. */
1608 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1609 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1612 if (!cqspi->use_direct_mode) {
1613 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1615 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1619 if (cqspi->use_dma_read) {
1620 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1622 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1628 struct device *dev = &cqspi->pdev->dev;
1632 * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N
1635 writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1636 reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1639 /* FIFO depth of zero means no value from devicetree was provided. */
1640 if (cqspi->fifo_depth == 0) {
1641 cqspi->fifo_depth = fifo_depth;
1643 } else if (fifo_depth != cqspi->fifo_depth) {
1645 fifo_depth, cqspi->fifo_depth);
1656 cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1657 if (IS_ERR(cqspi->rx_chan)) {
1658 int ret = PTR_ERR(cqspi->rx_chan);
1660 cqspi->rx_chan = NULL;
1661 if (ret == -ENODEV) {
1663 dev_info(&cqspi->pdev->dev, "No Rx DMA available\n");
1667 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1669 init_completion(&cqspi->rx_dma_complete);
1676 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1677 struct device *dev = &cqspi->pdev->dev;
1680 spi_get_chipselect(mem->spi, 0));
1696 unsigned int max_cs = cqspi->num_chipselect - 1;
1697 struct platform_device *pdev = cqspi->pdev;
1698 struct device *dev = &pdev->dev;
1700 unsigned int cs;
1704 for_each_available_child_of_node_scoped(dev->of_node, np) {
1705 ret = of_property_read_u32(np, "reg", &cs);
1711 if (cs >= cqspi->num_chipselect) {
1712 dev_err(dev, "Chip select %d out of range.\n", cs);
1713 return -EINVAL;
1714 } else if (cs < max_cs) {
1715 max_cs = cs;
1718 f_pdata = &cqspi->f_pdata[cs];
1719 f_pdata->cqspi = cqspi;
1720 f_pdata->cs = cs;
1727 cqspi->num_chipselect = max_cs + 1;
1740 ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk);
1742 dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__);
1746 cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk;
1747 cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk;
1749 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]);
1751 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__);
1755 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]);
1757 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__);
1761 cqspi->is_jh7110 = true;
1766 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);
1773 clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]);
1774 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);
1780 struct device *dev = &pdev->dev;
1787 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi));
1789 return -ENOMEM;
1791 host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1792 host->mem_ops = &cqspi_mem_ops;
1793 host->mem_caps = &cqspi_mem_caps;
1794 host->dev.of_node = pdev->dev.of_node;
1798 cqspi->pdev = pdev;
1799 cqspi->host = host;
1800 cqspi->is_jh7110 = false;
1801 cqspi->ddata = ddata = of_device_get_match_data(dev);
1808 return -ENODEV;
1812 cqspi->clk = devm_clk_get(dev, NULL);
1813 if (IS_ERR(cqspi->clk)) {
1815 ret = PTR_ERR(cqspi->clk);
1820 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
1821 if (IS_ERR(cqspi->iobase)) {
1823 ret = PTR_ERR(cqspi->iobase);
1828 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb);
1829 if (IS_ERR(cqspi->ahb_base)) {
1831 ret = PTR_ERR(cqspi->ahb_base);
1834 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1835 cqspi->ahb_size = resource_size(res_ahb);
1837 init_completion(&cqspi->transfer_complete);
1842 return -ENXIO;
1849 ret = clk_prepare_enable(cqspi->clk);
1863 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1870 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
1887 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1888 host->max_speed_hz = cqspi->master_ref_clk_hz;
1891 cqspi->wr_completion = true;
1894 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1895 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1896 cqspi->master_ref_clk_hz);
1897 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1898 host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1899 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_QUAD)
1900 host->mode_bits |= SPI_TX_QUAD;
1901 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) {
1902 cqspi->use_direct_mode = true;
1903 cqspi->use_direct_mode_wr = true;
1905 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
1906 cqspi->use_dma_read = true;
1907 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
1908 cqspi->wr_completion = false;
1909 if (ddata->quirks & CQSPI_SLOW_SRAM)
1910 cqspi->slow_sram = true;
1911 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR)
1912 cqspi->apb_ahb_hazard = true;
1914 if (ddata->jh7110_clk_init) {
1919 if (ddata->quirks & CQSPI_DISABLE_STIG_MODE)
1920 cqspi->disable_stig_mode = true;
1922 if (ddata->quirks & CQSPI_DMA_SET_MASK) {
1923 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1930 pdev->name, cqspi);
1941 cqspi->current_cs = -1;
1942 cqspi->sclk = 0;
1950 host->num_chipselect = cqspi->num_chipselect;
1952 if (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET)
1955 if (cqspi->use_direct_mode) {
1957 if (ret == -EPROBE_DEFER)
1963 if (cqspi->rx_chan)
1964 dma_release_channel(cqspi->rx_chan);
1974 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
1985 if (cqspi->is_jh7110)
1987 clk_disable_unprepare(cqspi->clk);
1996 spi_unregister_controller(cqspi->host);
1999 if (cqspi->rx_chan)
2000 dma_release_channel(cqspi->rx_chan);
2002 clk_disable_unprepare(cqspi->clk);
2004 if (cqspi->is_jh7110)
2007 pm_runtime_put_sync(&pdev->dev);
2008 pm_runtime_disable(&pdev->dev);
2016 clk_disable_unprepare(cqspi->clk);
2024 clk_prepare_enable(cqspi->clk);
2030 cqspi->current_cs = -1;
2031 cqspi->sclk = 0;
2040 ret = spi_controller_suspend(cqspi->host);
2058 return spi_controller_resume(cqspi->host);
2124 .compatible = "cdns,qspi-nor",
2128 .compatible = "ti,k2g-qspi",
2132 .compatible = "ti,am654-ospi",
2136 .compatible = "intel,lgm-qspi",
2140 .compatible = "xlnx,versal-ospi-1.0",
2144 .compatible = "intel,socfpga-qspi",
2148 .compatible = "starfive,jh7110-qspi",
2152 .compatible = "amd,pensando-elba-qspi",
2156 .compatible = "mobileye,eyeq5-ospi",
2160 .compatible = "amd,versal2-ospi",