Lines Matching +full:mixed +full:- +full:signals
1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
316 if (ret != -ETIMEDOUT) in cqspi_wait_for_bit()
319 timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US; in cqspi_wait_for_bit()
329 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
336 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); in cqspi_get_rd_sram_level()
346 dma_status = readl(cqspi->iobase + in cqspi_get_versal_dma_status()
348 writel(dma_status, cqspi->iobase + in cqspi_get_versal_dma_status()
357 const struct cqspi_driver_platdata *ddata = cqspi->ddata; in cqspi_irq_handler()
361 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
364 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
366 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { in cqspi_irq_handler()
367 if (ddata->get_dma_status(cqspi)) { in cqspi_irq_handler()
368 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
373 else if (!cqspi->slow_sram) in cqspi_irq_handler()
379 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
388 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; in cqspi_calc_rdreg()
389 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; in cqspi_calc_rdreg()
390 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; in cqspi_calc_rdreg()
399 if (!op->dummy.nbytes) in cqspi_calc_dummy()
402 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); in cqspi_calc_dummy()
403 if (op->cmd.dtr) in cqspi_calc_dummy()
432 dev_err(&cqspi->pdev->dev, in cqspi_wait_idle()
435 return -ETIMEDOUT; in cqspi_wait_idle()
444 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd()
454 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL, in cqspi_exec_flash_cmd()
457 dev_err(&cqspi->pdev->dev, in cqspi_exec_flash_cmd()
470 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_setup_opcode_ext()
471 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext()
475 if (op->cmd.nbytes != 2) in cqspi_setup_opcode_ext()
476 return -EINVAL; in cqspi_setup_opcode_ext()
479 ext = op->cmd.opcode & 0xff; in cqspi_setup_opcode_ext()
492 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_enable_dtr()
493 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr()
503 if (op->cmd.dtr) { in cqspi_enable_dtr()
527 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_read()
528 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read()
529 u8 *rxbuf = op->data.buf.in; in cqspi_command_read()
531 size_t n_rx = op->data.nbytes; in cqspi_command_read()
543 dev_err(&cqspi->pdev->dev, in cqspi_command_read()
546 return -EINVAL; in cqspi_command_read()
549 if (op->cmd.dtr) in cqspi_command_read()
550 opcode = op->cmd.opcode >> 8; in cqspi_command_read()
552 opcode = op->cmd.opcode; in cqspi_command_read()
561 return -EOPNOTSUPP; in cqspi_command_read()
570 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) in cqspi_command_read()
574 if (op->addr.nbytes) { in cqspi_command_read()
576 reg |= ((op->addr.nbytes - 1) & in cqspi_command_read()
580 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_read()
597 read_len = n_rx - read_len; in cqspi_command_read()
610 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_write()
611 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write()
613 const u8 *txbuf = op->data.buf.out; in cqspi_command_write()
614 size_t n_tx = op->data.nbytes; in cqspi_command_write()
625 dev_err(&cqspi->pdev->dev, in cqspi_command_write()
628 return -EINVAL; in cqspi_command_write()
634 if (op->cmd.dtr) in cqspi_command_write()
635 opcode = op->cmd.opcode >> 8; in cqspi_command_write()
637 opcode = op->cmd.opcode; in cqspi_command_write()
641 if (op->addr.nbytes) { in cqspi_command_write()
643 reg |= ((op->addr.nbytes - 1) & in cqspi_command_write()
647 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_write()
652 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) in cqspi_command_write()
662 write_len = n_tx - 4; in cqspi_command_write()
679 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read_setup()
680 void __iomem *reg_base = cqspi->iobase; in cqspi_read_setup()
690 if (op->cmd.dtr) in cqspi_read_setup()
691 opcode = op->cmd.opcode >> 8; in cqspi_read_setup()
693 opcode = op->cmd.opcode; in cqspi_read_setup()
702 return -EOPNOTSUPP; in cqspi_read_setup()
713 reg |= (op->addr.nbytes - 1); in cqspi_read_setup()
722 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_read_execute()
723 bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ); in cqspi_indirect_read_execute()
724 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_read_execute()
725 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_read_execute()
726 void __iomem *ahb_base = cqspi->ahb_base; in cqspi_indirect_read_execute()
747 if (use_irq && cqspi->slow_sram) in cqspi_indirect_read_execute()
754 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
760 !wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_read_execute()
762 ret = -ETIMEDOUT; in cqspi_indirect_read_execute()
768 if (cqspi->slow_sram) in cqspi_indirect_read_execute()
781 bytes_to_read *= cqspi->fifo_width; in cqspi_indirect_read_execute()
794 (rxbuf_end - rxbuf), in cqspi_indirect_read_execute()
798 remaining -= bytes_to_read; in cqspi_indirect_read_execute()
803 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
804 if (cqspi->slow_sram) in cqspi_indirect_read_execute()
810 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD, in cqspi_indirect_read_execute()
837 void __iomem *reg_base = cqspi->iobase; in cqspi_controller_enable()
854 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_versal_indirect_read_dma()
855 struct device *dev = &cqspi->pdev->dev; in cqspi_versal_indirect_read_dma()
856 void __iomem *reg_base = cqspi->iobase; in cqspi_versal_indirect_read_dma()
865 bytes_to_dma = (n_rx - bytes_rem); in cqspi_versal_indirect_read_dma()
870 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); in cqspi_versal_indirect_read_dma()
876 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
878 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
885 return -ENOMEM; in cqspi_versal_indirect_read_dma()
910 writel(cqspi->trigger_address, reg_base + in cqspi_versal_indirect_read_dma()
923 reinit_completion(&cqspi->transfer_complete); in cqspi_versal_indirect_read_dma()
925 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_versal_indirect_read_dma()
927 ret = -ETIMEDOUT; in cqspi_versal_indirect_read_dma()
932 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); in cqspi_versal_indirect_read_dma()
936 cqspi->iobase + CQSPI_REG_INDIRECTRD); in cqspi_versal_indirect_read_dma()
941 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
943 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
947 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, in cqspi_versal_indirect_read_dma()
974 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
976 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
978 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); in cqspi_versal_indirect_read_dma()
988 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write_setup()
989 void __iomem *reg_base = cqspi->iobase; in cqspi_write_setup()
996 if (op->cmd.dtr) in cqspi_write_setup()
997 opcode = op->cmd.opcode >> 8; in cqspi_write_setup()
999 opcode = op->cmd.opcode; in cqspi_write_setup()
1003 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; in cqspi_write_setup()
1004 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; in cqspi_write_setup()
1012 * cypress Semper flash expect a 4-byte dummy address in the Read SR in cqspi_write_setup()
1016 * command when doing auto-HW polling. So, disable write completion in cqspi_write_setup()
1017 * polling on the controller's side. spinand and spi-nor will take in cqspi_write_setup()
1020 if (cqspi->wr_completion) { in cqspi_write_setup()
1029 cqspi->use_direct_mode_wr = false; in cqspi_write_setup()
1034 reg |= (op->addr.nbytes - 1); in cqspi_write_setup()
1043 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_write_execute()
1044 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_write_execute()
1045 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_write_execute()
1058 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
1068 if (cqspi->wr_delay) in cqspi_indirect_write_execute()
1069 ndelay(cqspi->wr_delay); in cqspi_indirect_write_execute()
1075 if (cqspi->apb_ahb_hazard) in cqspi_indirect_write_execute()
1086 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); in cqspi_indirect_write_execute()
1093 iowrite32(temp, cqspi->ahb_base); in cqspi_indirect_write_execute()
1097 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_write_execute()
1100 ret = -ETIMEDOUT; in cqspi_indirect_write_execute()
1104 remaining -= write_bytes; in cqspi_indirect_write_execute()
1107 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
1111 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR, in cqspi_indirect_write_execute()
1140 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_chipselect()
1141 void __iomem *reg_base = cqspi->iobase; in cqspi_chipselect()
1142 unsigned int chip_select = f_pdata->cs; in cqspi_chipselect()
1146 if (cqspi->is_decoded_cs) { in cqspi_chipselect()
1180 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_delay()
1181 void __iomem *iobase = cqspi->iobase; in cqspi_delay()
1182 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_delay()
1188 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); in cqspi_delay()
1190 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); in cqspi_delay()
1195 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); in cqspi_delay()
1196 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); in cqspi_delay()
1197 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); in cqspi_delay()
1212 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_config_baudrate_div()
1213 void __iomem *reg_base = cqspi->iobase; in cqspi_config_baudrate_div()
1217 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; in cqspi_config_baudrate_div()
1222 dev_warn(&cqspi->pdev->dev, in cqspi_config_baudrate_div()
1224 cqspi->sclk, ref_clk_hz/((div+1)*2)); in cqspi_config_baudrate_div()
1237 void __iomem *reg_base = cqspi->iobase; in cqspi_readdata_capture()
1259 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_configure()
1260 int switch_cs = (cqspi->current_cs != f_pdata->cs); in cqspi_configure()
1261 int switch_ck = (cqspi->sclk != sclk); in cqspi_configure()
1268 cqspi->current_cs = f_pdata->cs; in cqspi_configure()
1274 cqspi->sclk = sclk; in cqspi_configure()
1277 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, in cqspi_configure()
1278 f_pdata->read_delay); in cqspi_configure()
1288 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write()
1289 loff_t to = op->addr.val; in cqspi_write()
1290 size_t len = op->data.nbytes; in cqspi_write()
1291 const u_char *buf = op->data.buf.out; in cqspi_write()
1299 * Some flashes like the Cypress Semper flash expect a dummy 4-byte in cqspi_write()
1306 if (!op->cmd.dtr && cqspi->use_direct_mode && in cqspi_write()
1307 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { in cqspi_write()
1308 memcpy_toio(cqspi->ahb_base + to, buf, len); in cqspi_write()
1319 complete(&cqspi->rx_dma_complete); in cqspi_rx_dma_callback()
1325 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_direct_read_execute()
1326 struct device *dev = &cqspi->pdev->dev; in cqspi_direct_read_execute()
1328 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; in cqspi_direct_read_execute()
1335 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { in cqspi_direct_read_execute()
1336 memcpy_fromio(buf, cqspi->ahb_base + from, len); in cqspi_direct_read_execute()
1340 ddev = cqspi->rx_chan->device->dev; in cqspi_direct_read_execute()
1344 return -ENOMEM; in cqspi_direct_read_execute()
1346 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, in cqspi_direct_read_execute()
1350 ret = -EIO; in cqspi_direct_read_execute()
1354 tx->callback = cqspi_rx_dma_callback; in cqspi_direct_read_execute()
1355 tx->callback_param = cqspi; in cqspi_direct_read_execute()
1356 cookie = tx->tx_submit(tx); in cqspi_direct_read_execute()
1357 reinit_completion(&cqspi->rx_dma_complete); in cqspi_direct_read_execute()
1362 ret = -EIO; in cqspi_direct_read_execute()
1366 dma_async_issue_pending(cqspi->rx_chan); in cqspi_direct_read_execute()
1367 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, in cqspi_direct_read_execute()
1369 dmaengine_terminate_sync(cqspi->rx_chan); in cqspi_direct_read_execute()
1371 ret = -ETIMEDOUT; in cqspi_direct_read_execute()
1384 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read()
1385 const struct cqspi_driver_platdata *ddata = cqspi->ddata; in cqspi_read()
1386 loff_t from = op->addr.val; in cqspi_read()
1387 size_t len = op->data.nbytes; in cqspi_read()
1388 u_char *buf = op->data.buf.in; in cqspi_read()
1396 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) in cqspi_read()
1399 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && in cqspi_read()
1401 return ddata->indirect_read_dma(f_pdata, buf, from, len); in cqspi_read()
1408 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_mem_process()
1411 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; in cqspi_mem_process()
1412 cqspi_configure(f_pdata, mem->spi->max_speed_hz); in cqspi_mem_process()
1414 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { in cqspi_mem_process()
1420 if (!op->addr.nbytes || in cqspi_mem_process()
1421 (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX && in cqspi_mem_process()
1422 !cqspi->disable_stig_mode)) in cqspi_mem_process()
1428 if (!op->addr.nbytes || !op->data.buf.out) in cqspi_mem_process()
1437 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_exec_mem_op()
1438 struct device *dev = &cqspi->pdev->dev; in cqspi_exec_mem_op()
1442 dev_err(&mem->spi->dev, "resume failed with %d\n", ret); in cqspi_exec_mem_op()
1452 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); in cqspi_exec_mem_op()
1463 * op->dummy.dtr is required for converting nbytes into ncycles. in cqspi_supports_mem_op()
1466 all_true = op->cmd.dtr && in cqspi_supports_mem_op()
1467 (!op->addr.nbytes || op->addr.dtr) && in cqspi_supports_mem_op()
1468 (!op->dummy.nbytes || op->dummy.dtr) && in cqspi_supports_mem_op()
1469 (!op->data.nbytes || op->data.dtr); in cqspi_supports_mem_op()
1471 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && in cqspi_supports_mem_op()
1472 !op->data.dtr; in cqspi_supports_mem_op()
1475 /* Right now we only support 8-8-8 DTR mode. */ in cqspi_supports_mem_op()
1476 if (op->cmd.nbytes && op->cmd.buswidth != 8) in cqspi_supports_mem_op()
1478 if (op->addr.nbytes && op->addr.buswidth != 8) in cqspi_supports_mem_op()
1480 if (op->data.nbytes && op->data.buswidth != 8) in cqspi_supports_mem_op()
1483 /* Mixed DTR modes are not supported. */ in cqspi_supports_mem_op()
1494 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { in cqspi_of_get_flash_pdata()
1495 dev_err(&pdev->dev, "couldn't determine read-delay\n"); in cqspi_of_get_flash_pdata()
1496 return -ENXIO; in cqspi_of_get_flash_pdata()
1499 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { in cqspi_of_get_flash_pdata()
1500 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); in cqspi_of_get_flash_pdata()
1501 return -ENXIO; in cqspi_of_get_flash_pdata()
1504 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { in cqspi_of_get_flash_pdata()
1505 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); in cqspi_of_get_flash_pdata()
1506 return -ENXIO; in cqspi_of_get_flash_pdata()
1509 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { in cqspi_of_get_flash_pdata()
1510 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); in cqspi_of_get_flash_pdata()
1511 return -ENXIO; in cqspi_of_get_flash_pdata()
1514 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { in cqspi_of_get_flash_pdata()
1515 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); in cqspi_of_get_flash_pdata()
1516 return -ENXIO; in cqspi_of_get_flash_pdata()
1519 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { in cqspi_of_get_flash_pdata()
1520 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); in cqspi_of_get_flash_pdata()
1521 return -ENXIO; in cqspi_of_get_flash_pdata()
1529 struct device *dev = &cqspi->pdev->dev; in cqspi_of_get_pdata()
1530 struct device_node *np = dev->of_node; in cqspi_of_get_pdata()
1533 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); in cqspi_of_get_pdata()
1535 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { in cqspi_of_get_pdata()
1536 /* Zero signals FIFO depth should be runtime detected. */ in cqspi_of_get_pdata()
1537 cqspi->fifo_depth = 0; in cqspi_of_get_pdata()
1540 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { in cqspi_of_get_pdata()
1541 dev_err(dev, "couldn't determine fifo-width\n"); in cqspi_of_get_pdata()
1542 return -ENXIO; in cqspi_of_get_pdata()
1545 if (of_property_read_u32(np, "cdns,trigger-address", in cqspi_of_get_pdata()
1546 &cqspi->trigger_address)) { in cqspi_of_get_pdata()
1547 dev_err(dev, "couldn't determine trigger-address\n"); in cqspi_of_get_pdata()
1548 return -ENXIO; in cqspi_of_get_pdata()
1551 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) in cqspi_of_get_pdata()
1552 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; in cqspi_of_get_pdata()
1554 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); in cqspi_of_get_pdata()
1556 if (!of_property_read_u32_array(np, "power-domains", id, in cqspi_of_get_pdata()
1558 cqspi->pd_dev_id = id[1]; in cqspi_of_get_pdata()
1568 writel(0, cqspi->iobase + CQSPI_REG_REMAP); in cqspi_controller_init()
1571 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); in cqspi_controller_init()
1574 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_init()
1577 writel(cqspi->trigger_address, in cqspi_controller_init()
1578 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); in cqspi_controller_init()
1580 /* Program read watermark -- 1/2 of the FIFO. */ in cqspi_controller_init()
1581 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, in cqspi_controller_init()
1582 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); in cqspi_controller_init()
1583 /* Program write watermark -- 1/8 of the FIFO. */ in cqspi_controller_init()
1584 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, in cqspi_controller_init()
1585 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); in cqspi_controller_init()
1588 if (!cqspi->use_direct_mode) { in cqspi_controller_init()
1589 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1591 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1595 if (cqspi->use_dma_read) { in cqspi_controller_init()
1596 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1598 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1604 struct device *dev = &cqspi->pdev->dev; in cqspi_controller_detect_fifo_depth()
1608 * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N in cqspi_controller_detect_fifo_depth()
1611 writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_detect_fifo_depth()
1612 reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_detect_fifo_depth()
1616 if (cqspi->fifo_depth == 0) { in cqspi_controller_detect_fifo_depth()
1617 cqspi->fifo_depth = fifo_depth; in cqspi_controller_detect_fifo_depth()
1619 } else if (fifo_depth != cqspi->fifo_depth) { in cqspi_controller_detect_fifo_depth()
1621 fifo_depth, cqspi->fifo_depth); in cqspi_controller_detect_fifo_depth()
1632 cqspi->rx_chan = dma_request_chan_by_mask(&mask); in cqspi_request_mmap_dma()
1633 if (IS_ERR(cqspi->rx_chan)) { in cqspi_request_mmap_dma()
1634 int ret = PTR_ERR(cqspi->rx_chan); in cqspi_request_mmap_dma()
1636 cqspi->rx_chan = NULL; in cqspi_request_mmap_dma()
1637 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); in cqspi_request_mmap_dma()
1639 init_completion(&cqspi->rx_dma_complete); in cqspi_request_mmap_dma()
1646 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_get_name()
1647 struct device *dev = &cqspi->pdev->dev; in cqspi_get_name()
1650 spi_get_chipselect(mem->spi, 0)); in cqspi_get_name()
1665 unsigned int max_cs = cqspi->num_chipselect - 1; in cqspi_setup_flash()
1666 struct platform_device *pdev = cqspi->pdev; in cqspi_setup_flash()
1667 struct device *dev = &pdev->dev; in cqspi_setup_flash()
1673 for_each_available_child_of_node_scoped(dev->of_node, np) { in cqspi_setup_flash()
1680 if (cs >= cqspi->num_chipselect) { in cqspi_setup_flash()
1682 return -EINVAL; in cqspi_setup_flash()
1687 f_pdata = &cqspi->f_pdata[cs]; in cqspi_setup_flash()
1688 f_pdata->cqspi = cqspi; in cqspi_setup_flash()
1689 f_pdata->cs = cs; in cqspi_setup_flash()
1696 cqspi->num_chipselect = max_cs + 1; in cqspi_setup_flash()
1709 ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); in cqspi_jh7110_clk_init()
1711 dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); in cqspi_jh7110_clk_init()
1715 cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk; in cqspi_jh7110_clk_init()
1716 cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk; in cqspi_jh7110_clk_init()
1718 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_clk_init()
1720 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); in cqspi_jh7110_clk_init()
1724 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); in cqspi_jh7110_clk_init()
1726 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); in cqspi_jh7110_clk_init()
1730 cqspi->is_jh7110 = true; in cqspi_jh7110_clk_init()
1735 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_clk_init()
1742 clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); in cqspi_jh7110_disable_clk()
1743 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_disable_clk()
1749 struct device *dev = &pdev->dev; in cqspi_probe()
1756 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); in cqspi_probe()
1758 return -ENOMEM; in cqspi_probe()
1760 host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; in cqspi_probe()
1761 host->mem_ops = &cqspi_mem_ops; in cqspi_probe()
1762 host->mem_caps = &cqspi_mem_caps; in cqspi_probe()
1763 host->dev.of_node = pdev->dev.of_node; in cqspi_probe()
1767 cqspi->pdev = pdev; in cqspi_probe()
1768 cqspi->host = host; in cqspi_probe()
1769 cqspi->is_jh7110 = false; in cqspi_probe()
1770 cqspi->ddata = ddata = of_device_get_match_data(dev); in cqspi_probe()
1777 return -ENODEV; in cqspi_probe()
1781 cqspi->clk = devm_clk_get(dev, NULL); in cqspi_probe()
1782 if (IS_ERR(cqspi->clk)) { in cqspi_probe()
1784 ret = PTR_ERR(cqspi->clk); in cqspi_probe()
1789 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); in cqspi_probe()
1790 if (IS_ERR(cqspi->iobase)) { in cqspi_probe()
1792 ret = PTR_ERR(cqspi->iobase); in cqspi_probe()
1797 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); in cqspi_probe()
1798 if (IS_ERR(cqspi->ahb_base)) { in cqspi_probe()
1800 ret = PTR_ERR(cqspi->ahb_base); in cqspi_probe()
1803 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; in cqspi_probe()
1804 cqspi->ahb_size = resource_size(res_ahb); in cqspi_probe()
1806 init_completion(&cqspi->transfer_complete); in cqspi_probe()
1811 return -ENXIO; in cqspi_probe()
1818 ret = clk_prepare_enable(cqspi->clk); in cqspi_probe()
1832 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); in cqspi_probe()
1839 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { in cqspi_probe()
1856 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); in cqspi_probe()
1857 host->max_speed_hz = cqspi->master_ref_clk_hz; in cqspi_probe()
1860 cqspi->wr_completion = true; in cqspi_probe()
1863 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) in cqspi_probe()
1864 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, in cqspi_probe()
1865 cqspi->master_ref_clk_hz); in cqspi_probe()
1866 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) in cqspi_probe()
1867 host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; in cqspi_probe()
1868 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { in cqspi_probe()
1869 cqspi->use_direct_mode = true; in cqspi_probe()
1870 cqspi->use_direct_mode_wr = true; in cqspi_probe()
1872 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) in cqspi_probe()
1873 cqspi->use_dma_read = true; in cqspi_probe()
1874 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) in cqspi_probe()
1875 cqspi->wr_completion = false; in cqspi_probe()
1876 if (ddata->quirks & CQSPI_SLOW_SRAM) in cqspi_probe()
1877 cqspi->slow_sram = true; in cqspi_probe()
1878 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) in cqspi_probe()
1879 cqspi->apb_ahb_hazard = true; in cqspi_probe()
1881 if (ddata->jh7110_clk_init) { in cqspi_probe()
1886 if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) in cqspi_probe()
1887 cqspi->disable_stig_mode = true; in cqspi_probe()
1889 if (of_device_is_compatible(pdev->dev.of_node, in cqspi_probe()
1890 "xlnx,versal-ospi-1.0")) { in cqspi_probe()
1891 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); in cqspi_probe()
1898 pdev->name, cqspi); in cqspi_probe()
1909 cqspi->current_cs = -1; in cqspi_probe()
1910 cqspi->sclk = 0; in cqspi_probe()
1918 host->num_chipselect = cqspi->num_chipselect; in cqspi_probe()
1920 if (cqspi->use_direct_mode) { in cqspi_probe()
1922 if (ret == -EPROBE_DEFER) in cqspi_probe()
1928 if (cqspi->rx_chan) in cqspi_probe()
1929 dma_release_channel(cqspi->rx_chan); in cqspi_probe()
1939 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); in cqspi_probe()
1950 if (cqspi->is_jh7110) in cqspi_probe()
1952 clk_disable_unprepare(cqspi->clk); in cqspi_probe()
1961 spi_unregister_controller(cqspi->host); in cqspi_remove()
1964 if (cqspi->rx_chan) in cqspi_remove()
1965 dma_release_channel(cqspi->rx_chan); in cqspi_remove()
1967 clk_disable_unprepare(cqspi->clk); in cqspi_remove()
1969 if (cqspi->is_jh7110) in cqspi_remove()
1972 pm_runtime_put_sync(&pdev->dev); in cqspi_remove()
1973 pm_runtime_disable(&pdev->dev); in cqspi_remove()
1981 clk_disable_unprepare(cqspi->clk); in cqspi_runtime_suspend()
1989 clk_prepare_enable(cqspi->clk); in cqspi_runtime_resume()
1995 cqspi->current_cs = -1; in cqspi_runtime_resume()
1996 cqspi->sclk = 0; in cqspi_runtime_resume()
2005 ret = spi_controller_suspend(cqspi->host); in cqspi_suspend()
2023 return spi_controller_resume(cqspi->host); in cqspi_resume()
2079 .compatible = "cdns,qspi-nor",
2083 .compatible = "ti,k2g-qspi",
2087 .compatible = "ti,am654-ospi",
2091 .compatible = "intel,lgm-qspi",
2095 .compatible = "xlnx,versal-ospi-1.0",
2099 .compatible = "intel,socfpga-qspi",
2103 .compatible = "starfive,jh7110-qspi",
2107 .compatible = "amd,pensando-elba-qspi",
2111 .compatible = "mobileye,eyeq5-ospi",