Lines Matching +full:lgm +full:- +full:io
1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
18 #include <linux/io.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
314 if (ret != -ETIMEDOUT) in cqspi_wait_for_bit()
317 timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US; in cqspi_wait_for_bit()
327 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
334 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); in cqspi_get_rd_sram_level()
344 dma_status = readl(cqspi->iobase + in cqspi_get_versal_dma_status()
346 writel(dma_status, cqspi->iobase + in cqspi_get_versal_dma_status()
355 const struct cqspi_driver_platdata *ddata = cqspi->ddata; in cqspi_irq_handler()
359 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
362 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
364 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { in cqspi_irq_handler()
365 if (ddata->get_dma_status(cqspi)) { in cqspi_irq_handler()
366 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
371 else if (!cqspi->slow_sram) in cqspi_irq_handler()
377 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
386 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; in cqspi_calc_rdreg()
387 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; in cqspi_calc_rdreg()
388 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; in cqspi_calc_rdreg()
397 if (!op->dummy.nbytes) in cqspi_calc_dummy()
400 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); in cqspi_calc_dummy()
401 if (op->cmd.dtr) in cqspi_calc_dummy()
430 dev_err(&cqspi->pdev->dev, in cqspi_wait_idle()
433 return -ETIMEDOUT; in cqspi_wait_idle()
442 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd()
452 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL, in cqspi_exec_flash_cmd()
455 dev_err(&cqspi->pdev->dev, in cqspi_exec_flash_cmd()
468 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_setup_opcode_ext()
469 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext()
473 if (op->cmd.nbytes != 2) in cqspi_setup_opcode_ext()
474 return -EINVAL; in cqspi_setup_opcode_ext()
477 ext = op->cmd.opcode & 0xff; in cqspi_setup_opcode_ext()
490 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_enable_dtr()
491 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr()
501 if (op->cmd.dtr) { in cqspi_enable_dtr()
525 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_read()
526 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read()
527 u8 *rxbuf = op->data.buf.in; in cqspi_command_read()
529 size_t n_rx = op->data.nbytes; in cqspi_command_read()
541 dev_err(&cqspi->pdev->dev, in cqspi_command_read()
544 return -EINVAL; in cqspi_command_read()
547 if (op->cmd.dtr) in cqspi_command_read()
548 opcode = op->cmd.opcode >> 8; in cqspi_command_read()
550 opcode = op->cmd.opcode; in cqspi_command_read()
559 return -EOPNOTSUPP; in cqspi_command_read()
568 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) in cqspi_command_read()
572 if (op->addr.nbytes) { in cqspi_command_read()
574 reg |= ((op->addr.nbytes - 1) & in cqspi_command_read()
578 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_read()
595 read_len = n_rx - read_len; in cqspi_command_read()
608 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_write()
609 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write()
611 const u8 *txbuf = op->data.buf.out; in cqspi_command_write()
612 size_t n_tx = op->data.nbytes; in cqspi_command_write()
623 dev_err(&cqspi->pdev->dev, in cqspi_command_write()
626 return -EINVAL; in cqspi_command_write()
632 if (op->cmd.dtr) in cqspi_command_write()
633 opcode = op->cmd.opcode >> 8; in cqspi_command_write()
635 opcode = op->cmd.opcode; in cqspi_command_write()
639 if (op->addr.nbytes) { in cqspi_command_write()
641 reg |= ((op->addr.nbytes - 1) & in cqspi_command_write()
645 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_write()
650 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) in cqspi_command_write()
660 write_len = n_tx - 4; in cqspi_command_write()
677 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read_setup()
678 void __iomem *reg_base = cqspi->iobase; in cqspi_read_setup()
688 if (op->cmd.dtr) in cqspi_read_setup()
689 opcode = op->cmd.opcode >> 8; in cqspi_read_setup()
691 opcode = op->cmd.opcode; in cqspi_read_setup()
700 return -EOPNOTSUPP; in cqspi_read_setup()
711 reg |= (op->addr.nbytes - 1); in cqspi_read_setup()
720 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_read_execute()
721 bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ); in cqspi_indirect_read_execute()
722 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_read_execute()
723 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_read_execute()
724 void __iomem *ahb_base = cqspi->ahb_base; in cqspi_indirect_read_execute()
745 if (use_irq && cqspi->slow_sram) in cqspi_indirect_read_execute()
752 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
758 !wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_read_execute()
760 ret = -ETIMEDOUT; in cqspi_indirect_read_execute()
766 if (cqspi->slow_sram) in cqspi_indirect_read_execute()
779 bytes_to_read *= cqspi->fifo_width; in cqspi_indirect_read_execute()
792 (rxbuf_end - rxbuf), in cqspi_indirect_read_execute()
796 remaining -= bytes_to_read; in cqspi_indirect_read_execute()
801 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
802 if (cqspi->slow_sram) in cqspi_indirect_read_execute()
808 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD, in cqspi_indirect_read_execute()
835 void __iomem *reg_base = cqspi->iobase; in cqspi_controller_enable()
852 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_versal_indirect_read_dma()
853 struct device *dev = &cqspi->pdev->dev; in cqspi_versal_indirect_read_dma()
854 void __iomem *reg_base = cqspi->iobase; in cqspi_versal_indirect_read_dma()
863 bytes_to_dma = (n_rx - bytes_rem); in cqspi_versal_indirect_read_dma()
868 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); in cqspi_versal_indirect_read_dma()
874 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
876 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
883 return -ENOMEM; in cqspi_versal_indirect_read_dma()
908 writel(cqspi->trigger_address, reg_base + in cqspi_versal_indirect_read_dma()
921 reinit_completion(&cqspi->transfer_complete); in cqspi_versal_indirect_read_dma()
923 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_versal_indirect_read_dma()
925 ret = -ETIMEDOUT; in cqspi_versal_indirect_read_dma()
930 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); in cqspi_versal_indirect_read_dma()
934 cqspi->iobase + CQSPI_REG_INDIRECTRD); in cqspi_versal_indirect_read_dma()
939 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
941 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
945 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, in cqspi_versal_indirect_read_dma()
972 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
974 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
976 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); in cqspi_versal_indirect_read_dma()
986 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write_setup()
987 void __iomem *reg_base = cqspi->iobase; in cqspi_write_setup()
994 if (op->cmd.dtr) in cqspi_write_setup()
995 opcode = op->cmd.opcode >> 8; in cqspi_write_setup()
997 opcode = op->cmd.opcode; in cqspi_write_setup()
1001 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; in cqspi_write_setup()
1002 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; in cqspi_write_setup()
1010 * cypress Semper flash expect a 4-byte dummy address in the Read SR in cqspi_write_setup()
1014 * command when doing auto-HW polling. So, disable write completion in cqspi_write_setup()
1015 * polling on the controller's side. spinand and spi-nor will take in cqspi_write_setup()
1018 if (cqspi->wr_completion) { in cqspi_write_setup()
1027 cqspi->use_direct_mode_wr = false; in cqspi_write_setup()
1032 reg |= (op->addr.nbytes - 1); in cqspi_write_setup()
1041 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_write_execute()
1042 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_write_execute()
1043 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_write_execute()
1056 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
1066 if (cqspi->wr_delay) in cqspi_indirect_write_execute()
1067 ndelay(cqspi->wr_delay); in cqspi_indirect_write_execute()
1073 if (cqspi->apb_ahb_hazard) in cqspi_indirect_write_execute()
1084 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); in cqspi_indirect_write_execute()
1091 iowrite32(temp, cqspi->ahb_base); in cqspi_indirect_write_execute()
1095 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_write_execute()
1098 ret = -ETIMEDOUT; in cqspi_indirect_write_execute()
1102 remaining -= write_bytes; in cqspi_indirect_write_execute()
1105 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
1109 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR, in cqspi_indirect_write_execute()
1138 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_chipselect()
1139 void __iomem *reg_base = cqspi->iobase; in cqspi_chipselect()
1140 unsigned int chip_select = f_pdata->cs; in cqspi_chipselect()
1144 if (cqspi->is_decoded_cs) { in cqspi_chipselect()
1178 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_delay()
1179 void __iomem *iobase = cqspi->iobase; in cqspi_delay()
1180 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_delay()
1186 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); in cqspi_delay()
1188 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); in cqspi_delay()
1193 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); in cqspi_delay()
1194 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); in cqspi_delay()
1195 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); in cqspi_delay()
1210 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_config_baudrate_div()
1211 void __iomem *reg_base = cqspi->iobase; in cqspi_config_baudrate_div()
1215 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; in cqspi_config_baudrate_div()
1220 dev_warn(&cqspi->pdev->dev, in cqspi_config_baudrate_div()
1222 cqspi->sclk, ref_clk_hz/((div+1)*2)); in cqspi_config_baudrate_div()
1235 void __iomem *reg_base = cqspi->iobase; in cqspi_readdata_capture()
1257 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_configure()
1258 int switch_cs = (cqspi->current_cs != f_pdata->cs); in cqspi_configure()
1259 int switch_ck = (cqspi->sclk != sclk); in cqspi_configure()
1266 cqspi->current_cs = f_pdata->cs; in cqspi_configure()
1272 cqspi->sclk = sclk; in cqspi_configure()
1275 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, in cqspi_configure()
1276 f_pdata->read_delay); in cqspi_configure()
1286 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write()
1287 loff_t to = op->addr.val; in cqspi_write()
1288 size_t len = op->data.nbytes; in cqspi_write()
1289 const u_char *buf = op->data.buf.out; in cqspi_write()
1297 * Some flashes like the Cypress Semper flash expect a dummy 4-byte in cqspi_write()
1304 if (!op->cmd.dtr && cqspi->use_direct_mode && in cqspi_write()
1305 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { in cqspi_write()
1306 memcpy_toio(cqspi->ahb_base + to, buf, len); in cqspi_write()
1317 complete(&cqspi->rx_dma_complete); in cqspi_rx_dma_callback()
1323 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_direct_read_execute()
1324 struct device *dev = &cqspi->pdev->dev; in cqspi_direct_read_execute()
1326 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; in cqspi_direct_read_execute()
1333 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { in cqspi_direct_read_execute()
1334 memcpy_fromio(buf, cqspi->ahb_base + from, len); in cqspi_direct_read_execute()
1338 ddev = cqspi->rx_chan->device->dev; in cqspi_direct_read_execute()
1342 return -ENOMEM; in cqspi_direct_read_execute()
1344 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, in cqspi_direct_read_execute()
1348 ret = -EIO; in cqspi_direct_read_execute()
1352 tx->callback = cqspi_rx_dma_callback; in cqspi_direct_read_execute()
1353 tx->callback_param = cqspi; in cqspi_direct_read_execute()
1354 cookie = tx->tx_submit(tx); in cqspi_direct_read_execute()
1355 reinit_completion(&cqspi->rx_dma_complete); in cqspi_direct_read_execute()
1360 ret = -EIO; in cqspi_direct_read_execute()
1364 dma_async_issue_pending(cqspi->rx_chan); in cqspi_direct_read_execute()
1365 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, in cqspi_direct_read_execute()
1367 dmaengine_terminate_sync(cqspi->rx_chan); in cqspi_direct_read_execute()
1369 ret = -ETIMEDOUT; in cqspi_direct_read_execute()
1382 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read()
1383 const struct cqspi_driver_platdata *ddata = cqspi->ddata; in cqspi_read()
1384 loff_t from = op->addr.val; in cqspi_read()
1385 size_t len = op->data.nbytes; in cqspi_read()
1386 u_char *buf = op->data.buf.in; in cqspi_read()
1394 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) in cqspi_read()
1397 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && in cqspi_read()
1399 return ddata->indirect_read_dma(f_pdata, buf, from, len); in cqspi_read()
1406 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_mem_process()
1409 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; in cqspi_mem_process()
1410 cqspi_configure(f_pdata, mem->spi->max_speed_hz); in cqspi_mem_process()
1412 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { in cqspi_mem_process()
1418 if (!op->addr.nbytes || in cqspi_mem_process()
1419 op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) in cqspi_mem_process()
1425 if (!op->addr.nbytes || !op->data.buf.out) in cqspi_mem_process()
1434 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_exec_mem_op()
1435 struct device *dev = &cqspi->pdev->dev; in cqspi_exec_mem_op()
1439 dev_err(&mem->spi->dev, "resume failed with %d\n", ret); in cqspi_exec_mem_op()
1449 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); in cqspi_exec_mem_op()
1460 * op->dummy.dtr is required for converting nbytes into ncycles. in cqspi_supports_mem_op()
1463 all_true = op->cmd.dtr && in cqspi_supports_mem_op()
1464 (!op->addr.nbytes || op->addr.dtr) && in cqspi_supports_mem_op()
1465 (!op->dummy.nbytes || op->dummy.dtr) && in cqspi_supports_mem_op()
1466 (!op->data.nbytes || op->data.dtr); in cqspi_supports_mem_op()
1468 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && in cqspi_supports_mem_op()
1469 !op->data.dtr; in cqspi_supports_mem_op()
1472 /* Right now we only support 8-8-8 DTR mode. */ in cqspi_supports_mem_op()
1473 if (op->cmd.nbytes && op->cmd.buswidth != 8) in cqspi_supports_mem_op()
1475 if (op->addr.nbytes && op->addr.buswidth != 8) in cqspi_supports_mem_op()
1477 if (op->data.nbytes && op->data.buswidth != 8) in cqspi_supports_mem_op()
1491 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { in cqspi_of_get_flash_pdata()
1492 dev_err(&pdev->dev, "couldn't determine read-delay\n"); in cqspi_of_get_flash_pdata()
1493 return -ENXIO; in cqspi_of_get_flash_pdata()
1496 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { in cqspi_of_get_flash_pdata()
1497 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); in cqspi_of_get_flash_pdata()
1498 return -ENXIO; in cqspi_of_get_flash_pdata()
1501 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { in cqspi_of_get_flash_pdata()
1502 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); in cqspi_of_get_flash_pdata()
1503 return -ENXIO; in cqspi_of_get_flash_pdata()
1506 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { in cqspi_of_get_flash_pdata()
1507 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); in cqspi_of_get_flash_pdata()
1508 return -ENXIO; in cqspi_of_get_flash_pdata()
1511 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { in cqspi_of_get_flash_pdata()
1512 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); in cqspi_of_get_flash_pdata()
1513 return -ENXIO; in cqspi_of_get_flash_pdata()
1516 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { in cqspi_of_get_flash_pdata()
1517 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); in cqspi_of_get_flash_pdata()
1518 return -ENXIO; in cqspi_of_get_flash_pdata()
1526 struct device *dev = &cqspi->pdev->dev; in cqspi_of_get_pdata()
1527 struct device_node *np = dev->of_node; in cqspi_of_get_pdata()
1530 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); in cqspi_of_get_pdata()
1532 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { in cqspi_of_get_pdata()
1534 cqspi->fifo_depth = 0; in cqspi_of_get_pdata()
1537 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { in cqspi_of_get_pdata()
1538 dev_err(dev, "couldn't determine fifo-width\n"); in cqspi_of_get_pdata()
1539 return -ENXIO; in cqspi_of_get_pdata()
1542 if (of_property_read_u32(np, "cdns,trigger-address", in cqspi_of_get_pdata()
1543 &cqspi->trigger_address)) { in cqspi_of_get_pdata()
1544 dev_err(dev, "couldn't determine trigger-address\n"); in cqspi_of_get_pdata()
1545 return -ENXIO; in cqspi_of_get_pdata()
1548 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) in cqspi_of_get_pdata()
1549 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; in cqspi_of_get_pdata()
1551 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); in cqspi_of_get_pdata()
1553 if (!of_property_read_u32_array(np, "power-domains", id, in cqspi_of_get_pdata()
1555 cqspi->pd_dev_id = id[1]; in cqspi_of_get_pdata()
1565 writel(0, cqspi->iobase + CQSPI_REG_REMAP); in cqspi_controller_init()
1568 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); in cqspi_controller_init()
1571 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_init()
1574 writel(cqspi->trigger_address, in cqspi_controller_init()
1575 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); in cqspi_controller_init()
1577 /* Program read watermark -- 1/2 of the FIFO. */ in cqspi_controller_init()
1578 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, in cqspi_controller_init()
1579 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); in cqspi_controller_init()
1580 /* Program write watermark -- 1/8 of the FIFO. */ in cqspi_controller_init()
1581 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, in cqspi_controller_init()
1582 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); in cqspi_controller_init()
1585 if (!cqspi->use_direct_mode) { in cqspi_controller_init()
1586 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1588 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1592 if (cqspi->use_dma_read) { in cqspi_controller_init()
1593 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1595 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1601 struct device *dev = &cqspi->pdev->dev; in cqspi_controller_detect_fifo_depth()
1605 * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N in cqspi_controller_detect_fifo_depth()
1608 writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_detect_fifo_depth()
1609 reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_detect_fifo_depth()
1613 if (cqspi->fifo_depth == 0) { in cqspi_controller_detect_fifo_depth()
1614 cqspi->fifo_depth = fifo_depth; in cqspi_controller_detect_fifo_depth()
1616 } else if (fifo_depth != cqspi->fifo_depth) { in cqspi_controller_detect_fifo_depth()
1618 fifo_depth, cqspi->fifo_depth); in cqspi_controller_detect_fifo_depth()
1629 cqspi->rx_chan = dma_request_chan_by_mask(&mask); in cqspi_request_mmap_dma()
1630 if (IS_ERR(cqspi->rx_chan)) { in cqspi_request_mmap_dma()
1631 int ret = PTR_ERR(cqspi->rx_chan); in cqspi_request_mmap_dma()
1633 cqspi->rx_chan = NULL; in cqspi_request_mmap_dma()
1634 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); in cqspi_request_mmap_dma()
1636 init_completion(&cqspi->rx_dma_complete); in cqspi_request_mmap_dma()
1643 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_get_name()
1644 struct device *dev = &cqspi->pdev->dev; in cqspi_get_name()
1647 spi_get_chipselect(mem->spi, 0)); in cqspi_get_name()
1662 unsigned int max_cs = cqspi->num_chipselect - 1; in cqspi_setup_flash()
1663 struct platform_device *pdev = cqspi->pdev; in cqspi_setup_flash()
1664 struct device *dev = &pdev->dev; in cqspi_setup_flash()
1670 for_each_available_child_of_node_scoped(dev->of_node, np) { in cqspi_setup_flash()
1677 if (cs >= cqspi->num_chipselect) { in cqspi_setup_flash()
1679 return -EINVAL; in cqspi_setup_flash()
1684 f_pdata = &cqspi->f_pdata[cs]; in cqspi_setup_flash()
1685 f_pdata->cqspi = cqspi; in cqspi_setup_flash()
1686 f_pdata->cs = cs; in cqspi_setup_flash()
1693 cqspi->num_chipselect = max_cs + 1; in cqspi_setup_flash()
1706 ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); in cqspi_jh7110_clk_init()
1708 dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); in cqspi_jh7110_clk_init()
1712 cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk; in cqspi_jh7110_clk_init()
1713 cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk; in cqspi_jh7110_clk_init()
1715 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_clk_init()
1717 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); in cqspi_jh7110_clk_init()
1721 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); in cqspi_jh7110_clk_init()
1723 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); in cqspi_jh7110_clk_init()
1727 cqspi->is_jh7110 = true; in cqspi_jh7110_clk_init()
1732 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_clk_init()
1739 clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); in cqspi_jh7110_disable_clk()
1740 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_disable_clk()
1746 struct device *dev = &pdev->dev; in cqspi_probe()
1753 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); in cqspi_probe()
1755 return -ENOMEM; in cqspi_probe()
1757 host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; in cqspi_probe()
1758 host->mem_ops = &cqspi_mem_ops; in cqspi_probe()
1759 host->mem_caps = &cqspi_mem_caps; in cqspi_probe()
1760 host->dev.of_node = pdev->dev.of_node; in cqspi_probe()
1764 cqspi->pdev = pdev; in cqspi_probe()
1765 cqspi->host = host; in cqspi_probe()
1766 cqspi->is_jh7110 = false; in cqspi_probe()
1767 cqspi->ddata = ddata = of_device_get_match_data(dev); in cqspi_probe()
1774 return -ENODEV; in cqspi_probe()
1778 cqspi->clk = devm_clk_get(dev, NULL); in cqspi_probe()
1779 if (IS_ERR(cqspi->clk)) { in cqspi_probe()
1781 ret = PTR_ERR(cqspi->clk); in cqspi_probe()
1786 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); in cqspi_probe()
1787 if (IS_ERR(cqspi->iobase)) { in cqspi_probe()
1789 ret = PTR_ERR(cqspi->iobase); in cqspi_probe()
1794 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); in cqspi_probe()
1795 if (IS_ERR(cqspi->ahb_base)) { in cqspi_probe()
1797 ret = PTR_ERR(cqspi->ahb_base); in cqspi_probe()
1800 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; in cqspi_probe()
1801 cqspi->ahb_size = resource_size(res_ahb); in cqspi_probe()
1803 init_completion(&cqspi->transfer_complete); in cqspi_probe()
1808 return -ENXIO; in cqspi_probe()
1815 ret = clk_prepare_enable(cqspi->clk); in cqspi_probe()
1829 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); in cqspi_probe()
1836 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { in cqspi_probe()
1853 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); in cqspi_probe()
1854 host->max_speed_hz = cqspi->master_ref_clk_hz; in cqspi_probe()
1857 cqspi->wr_completion = true; in cqspi_probe()
1860 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) in cqspi_probe()
1861 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, in cqspi_probe()
1862 cqspi->master_ref_clk_hz); in cqspi_probe()
1863 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) in cqspi_probe()
1864 host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; in cqspi_probe()
1865 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { in cqspi_probe()
1866 cqspi->use_direct_mode = true; in cqspi_probe()
1867 cqspi->use_direct_mode_wr = true; in cqspi_probe()
1869 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) in cqspi_probe()
1870 cqspi->use_dma_read = true; in cqspi_probe()
1871 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) in cqspi_probe()
1872 cqspi->wr_completion = false; in cqspi_probe()
1873 if (ddata->quirks & CQSPI_SLOW_SRAM) in cqspi_probe()
1874 cqspi->slow_sram = true; in cqspi_probe()
1875 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) in cqspi_probe()
1876 cqspi->apb_ahb_hazard = true; in cqspi_probe()
1878 if (ddata->jh7110_clk_init) { in cqspi_probe()
1884 if (of_device_is_compatible(pdev->dev.of_node, in cqspi_probe()
1885 "xlnx,versal-ospi-1.0")) { in cqspi_probe()
1886 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); in cqspi_probe()
1893 pdev->name, cqspi); in cqspi_probe()
1904 cqspi->current_cs = -1; in cqspi_probe()
1905 cqspi->sclk = 0; in cqspi_probe()
1913 host->num_chipselect = cqspi->num_chipselect; in cqspi_probe()
1915 if (cqspi->use_direct_mode) { in cqspi_probe()
1917 if (ret == -EPROBE_DEFER) in cqspi_probe()
1923 if (cqspi->rx_chan) in cqspi_probe()
1924 dma_release_channel(cqspi->rx_chan); in cqspi_probe()
1934 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); in cqspi_probe()
1945 if (cqspi->is_jh7110) in cqspi_probe()
1947 clk_disable_unprepare(cqspi->clk); in cqspi_probe()
1956 spi_unregister_controller(cqspi->host); in cqspi_remove()
1959 if (cqspi->rx_chan) in cqspi_remove()
1960 dma_release_channel(cqspi->rx_chan); in cqspi_remove()
1962 clk_disable_unprepare(cqspi->clk); in cqspi_remove()
1964 if (cqspi->is_jh7110) in cqspi_remove()
1967 pm_runtime_put_sync(&pdev->dev); in cqspi_remove()
1968 pm_runtime_disable(&pdev->dev); in cqspi_remove()
1976 clk_disable_unprepare(cqspi->clk); in cqspi_runtime_suspend()
1984 clk_prepare_enable(cqspi->clk); in cqspi_runtime_resume()
1990 cqspi->current_cs = -1; in cqspi_runtime_resume()
1991 cqspi->sclk = 0; in cqspi_runtime_resume()
2000 ret = spi_controller_suspend(cqspi->host); in cqspi_suspend()
2018 return spi_controller_resume(cqspi->host); in cqspi_resume()
2073 .compatible = "cdns,qspi-nor",
2077 .compatible = "ti,k2g-qspi",
2081 .compatible = "ti,am654-ospi",
2085 .compatible = "intel,lgm-qspi",
2089 .compatible = "xlnx,versal-ospi-1.0",
2093 .compatible = "intel,socfpga-qspi",
2097 .compatible = "starfive,jh7110-qspi",
2101 .compatible = "amd,pensando-elba-qspi",
2105 .compatible = "mobileye,eyeq5-ospi",