303 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,  in bcm_qspi_read()  function
323 		if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))  in bcm_qspi_bspi_busy_poll()
350 	return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &  in bcm_qspi_bspi_lr_is_fifo_empty()
356 	u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);  in bcm_qspi_bspi_lr_read_fifo()
468 	u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);  in bcm_qspi_bspi_set_override()
521 		val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);  in bcm_qspi_bspi_set_mode()
560 	if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)  in bcm_qspi_enable_bspi()
575 	if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))  in bcm_qspi_disable_bspi()
589 		rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);  in bcm_qspi_chip_select()
784 	return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;  in read_rxram_slot_u8()
793 	return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |  in read_rxram_slot_u16()
794 		((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);  in read_rxram_slot_u16()
803 	val = bcm_qspi_read(qspi, MSPI, offset);  in read_rxram_slot_u32()
816 	msb = bcm_qspi_read(qspi, MSPI, msb_offset);  in read_rxram_slot_u64()
818 	lsb = bcm_qspi_read(qspi, MSPI, lsb_offset);  in read_rxram_slot_u64()
927 	return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));  in read_cdram_slot()
1249 	u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);  in bcm_qspi_mspi_l2_isr()
1391 	val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);  in bcm_qspi_bspi_init()
1426 	u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);  in bcm_qspi_hw_uninit()
1597 		rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);  in bcm_qspi_probe()
1701 			bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);  in bcm_qspi_suspend()