Lines Matching refs:val
128 u32 val; in a3700_spi_auto_cs_unset() local
130 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_auto_cs_unset()
131 val &= ~A3700_SPI_AUTO_CS; in a3700_spi_auto_cs_unset()
132 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_auto_cs_unset()
137 u32 val; in a3700_spi_activate_cs() local
139 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_spi_activate_cs()
140 val |= (A3700_SPI_EN << cs); in a3700_spi_activate_cs()
141 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); in a3700_spi_activate_cs()
147 u32 val; in a3700_spi_deactivate_cs() local
149 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_spi_deactivate_cs()
150 val &= ~(A3700_SPI_EN << cs); in a3700_spi_deactivate_cs()
151 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); in a3700_spi_deactivate_cs()
157 u32 val; in a3700_spi_pin_mode_set() local
159 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_pin_mode_set()
160 val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN); in a3700_spi_pin_mode_set()
161 val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); in a3700_spi_pin_mode_set()
167 val |= A3700_SPI_DATA_PIN0; in a3700_spi_pin_mode_set()
170 val |= A3700_SPI_DATA_PIN1; in a3700_spi_pin_mode_set()
173 val |= A3700_SPI_ADDR_PIN; in a3700_spi_pin_mode_set()
180 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_pin_mode_set()
187 u32 val; in a3700_spi_fifo_mode_set() local
189 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_fifo_mode_set()
191 val |= A3700_SPI_FIFO_MODE; in a3700_spi_fifo_mode_set()
193 val &= ~A3700_SPI_FIFO_MODE; in a3700_spi_fifo_mode_set()
194 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_fifo_mode_set()
200 u32 val; in a3700_spi_mode_set() local
202 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_mode_set()
205 val |= A3700_SPI_CLK_POL; in a3700_spi_mode_set()
207 val &= ~A3700_SPI_CLK_POL; in a3700_spi_mode_set()
210 val |= A3700_SPI_CLK_PHA; in a3700_spi_mode_set()
212 val &= ~A3700_SPI_CLK_PHA; in a3700_spi_mode_set()
214 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_mode_set()
220 u32 val; in a3700_spi_clock_set() local
232 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_clock_set()
233 val = val & ~A3700_SPI_CLK_PRESCALE_MASK; in a3700_spi_clock_set()
235 val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK); in a3700_spi_clock_set()
236 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_clock_set()
239 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); in a3700_spi_clock_set()
240 val |= A3700_SPI_CLK_CAPT_EDGE; in a3700_spi_clock_set()
241 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); in a3700_spi_clock_set()
247 u32 val; in a3700_spi_bytelen_set() local
249 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_bytelen_set()
251 val |= A3700_SPI_BYTE_LEN; in a3700_spi_bytelen_set()
253 val &= ~A3700_SPI_BYTE_LEN; in a3700_spi_bytelen_set()
254 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_bytelen_set()
262 u32 val; in a3700_spi_fifo_flush() local
264 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_fifo_flush()
265 val |= A3700_SPI_FIFO_FLUSH; in a3700_spi_fifo_flush()
266 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_fifo_flush()
269 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_fifo_flush()
270 if (!(val & A3700_SPI_FIFO_FLUSH)) in a3700_spi_fifo_flush()
281 u32 val; in a3700_spi_init() local
285 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_init()
286 val |= A3700_SPI_SRST; in a3700_spi_init()
287 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_init()
291 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_init()
292 val &= ~A3700_SPI_SRST; in a3700_spi_init()
293 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_init()
404 u32 val; in a3700_spi_fifo_thres_set() local
406 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_fifo_thres_set()
407 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT); in a3700_spi_fifo_thres_set()
408 val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT; in a3700_spi_fifo_thres_set()
409 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT); in a3700_spi_fifo_thres_set()
410 val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT; in a3700_spi_fifo_thres_set()
411 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_fifo_thres_set()
447 u32 val = 0; in a3700_spi_header_set() local
467 val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK) in a3700_spi_header_set()
469 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); in a3700_spi_header_set()
475 val = 0; in a3700_spi_header_set()
477 val = (val << 8) | a3700_spi->tx_buf[0]; in a3700_spi_header_set()
480 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); in a3700_spi_header_set()
487 u32 val; in a3700_is_wfifo_full() local
489 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_is_wfifo_full()
490 return (val & A3700_SPI_WFIFO_FULL); in a3700_is_wfifo_full()
495 u32 val; in a3700_spi_fifo_write() local
498 val = *(u32 *)a3700_spi->tx_buf; in a3700_spi_fifo_write()
499 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, cpu_to_le32(val)); in a3700_spi_fifo_write()
509 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_is_rfifo_empty() local
511 return (val & A3700_SPI_RFIFO_EMPTY); in a3700_is_rfifo_empty()
516 u32 val; in a3700_spi_fifo_read() local
519 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); in a3700_spi_fifo_read()
521 val = le32_to_cpu(val); in a3700_spi_fifo_read()
522 memcpy(a3700_spi->rx_buf, &val, 4); in a3700_spi_fifo_read()
533 *a3700_spi->rx_buf = val & 0xff; in a3700_spi_fifo_read()
534 val >>= 8; in a3700_spi_fifo_read()
548 u32 val; in a3700_spi_transfer_abort_fifo() local
550 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_abort_fifo()
551 val |= A3700_SPI_XFER_STOP; in a3700_spi_transfer_abort_fifo()
552 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_abort_fifo()
555 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_abort_fifo()
556 if (!(val & A3700_SPI_XFER_START)) in a3700_spi_transfer_abort_fifo()
563 val &= ~A3700_SPI_XFER_STOP; in a3700_spi_transfer_abort_fifo()
564 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_abort_fifo()
597 u32 val; in a3700_spi_transfer_one_fifo() local
629 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_one_fifo()
630 val &= ~A3700_SPI_RW_EN; in a3700_spi_transfer_one_fifo()
631 val |= A3700_SPI_XFER_START; in a3700_spi_transfer_one_fifo()
632 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_one_fifo()
635 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_one_fifo()
636 val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN); in a3700_spi_transfer_one_fifo()
637 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_one_fifo()
709 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_one_fifo()
710 val |= A3700_SPI_XFER_STOP; in a3700_spi_transfer_one_fifo()
711 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_one_fifo()
715 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_one_fifo()
716 if (!(val & A3700_SPI_XFER_START)) in a3700_spi_transfer_one_fifo()
727 val &= ~A3700_SPI_XFER_STOP; in a3700_spi_transfer_one_fifo()
728 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_one_fifo()
744 u32 val; in a3700_spi_transfer_one_full_duplex() local
758 val = *a3700_spi->tx_buf; in a3700_spi_transfer_one_full_duplex()
760 val = *(u32 *)a3700_spi->tx_buf; in a3700_spi_transfer_one_full_duplex()
762 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); in a3700_spi_transfer_one_full_duplex()
769 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); in a3700_spi_transfer_one_full_duplex()
771 memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len); in a3700_spi_transfer_one_full_duplex()