Lines Matching +full:sama5d2 +full:- +full:qspi
1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Atmel QSPI Controller
11 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
17 #include <linux/dma-mapping.h>
29 #include <linux/spi/spi-mem.h>
31 /* QSPI register offsets */
91 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
236 * struct atmel_qspi_pcal - Pad Calibration Clock Division
393 u32 value = readl_relaxed(aq->regs + offset); in atmel_qspi_read()
398 dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value, in atmel_qspi_read()
410 dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value, in atmel_qspi_write()
414 writel_relaxed(value, aq->regs + offset); in atmel_qspi_write()
422 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, in atmel_qspi_reg_sync()
442 if (op->cmd.buswidth != mode->cmd_buswidth) in atmel_qspi_is_compatible()
445 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth) in atmel_qspi_is_compatible()
448 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth) in atmel_qspi_is_compatible()
462 return -EOPNOTSUPP; in atmel_qspi_find_mode()
473 return -EOPNOTSUPP; in atmel_qspi_sama7g5_find_mode()
479 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller); in atmel_qspi_supports_op()
483 if (aq->caps->octal) { in atmel_qspi_supports_op()
494 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth && in atmel_qspi_supports_op()
495 op->dummy.nbytes == 0) in atmel_qspi_supports_op()
502 * If the QSPI controller is set in regular SPI mode, set it in
509 if (!(aq->mr & QSPI_MR_SMM)) { in atmel_qspi_set_serial_memory_mode()
510 aq->mr |= QSPI_MR_SMM; in atmel_qspi_set_serial_memory_mode()
511 atmel_qspi_write(aq->mr, aq, QSPI_MR); in atmel_qspi_set_serial_memory_mode()
513 if (aq->caps->has_gclk) in atmel_qspi_set_serial_memory_mode()
528 icr = QSPI_ICR_INST(op->cmd.opcode); in atmel_qspi_set_cfg()
536 if (op->dummy.nbytes) in atmel_qspi_set_cfg()
537 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth; in atmel_qspi_set_cfg()
540 * The controller allows 24 and 32-bit addressing while NAND-flash in atmel_qspi_set_cfg()
541 * requires 16-bit long. Handling 8-bit long addresses is done using in atmel_qspi_set_cfg()
542 * the option field. For the 16-bit addresses, the workaround depends in atmel_qspi_set_cfg()
547 * use the same buswidth). The limitation is when the 16-bit address is in atmel_qspi_set_cfg()
551 if (op->addr.buswidth) { in atmel_qspi_set_cfg()
552 switch (op->addr.nbytes) { in atmel_qspi_set_cfg()
557 icr |= QSPI_ICR_OPT(op->addr.val & 0xff); in atmel_qspi_set_cfg()
560 if (dummy_cycles < 8 / op->addr.buswidth) { in atmel_qspi_set_cfg()
563 iar = (op->cmd.opcode << 16) | in atmel_qspi_set_cfg()
564 (op->addr.val & 0xffff); in atmel_qspi_set_cfg()
567 iar = (op->addr.val << 8) & 0xffffff; in atmel_qspi_set_cfg()
568 dummy_cycles -= 8 / op->addr.buswidth; in atmel_qspi_set_cfg()
573 iar = op->addr.val & 0xffffff; in atmel_qspi_set_cfg()
577 iar = op->addr.val & 0x7ffffff; in atmel_qspi_set_cfg()
580 return -ENOTSUPP; in atmel_qspi_set_cfg()
584 /* offset of the data access in the QSPI memory space */ in atmel_qspi_set_cfg()
592 if (op->data.nbytes) { in atmel_qspi_set_cfg()
595 if (op->addr.nbytes) in atmel_qspi_set_cfg()
606 /* Set QSPI Instruction Frame registers. */ in atmel_qspi_set_cfg()
607 if (op->addr.nbytes && !op->data.nbytes) in atmel_qspi_set_cfg()
610 if (aq->caps->has_ricr) { in atmel_qspi_set_cfg()
611 if (op->data.dir == SPI_MEM_DATA_IN) in atmel_qspi_set_cfg()
616 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) in atmel_qspi_set_cfg()
638 reinit_completion(&aq->cmd_completion); in atmel_qspi_wait_for_completion()
639 aq->pending = sr & irq_mask; in atmel_qspi_wait_for_completion()
640 aq->irq_mask = irq_mask; in atmel_qspi_wait_for_completion()
642 if (!wait_for_completion_timeout(&aq->cmd_completion, in atmel_qspi_wait_for_completion()
644 err = -ETIMEDOUT; in atmel_qspi_wait_for_completion()
653 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller); in atmel_qspi_transfer()
656 if (!op->data.nbytes) in atmel_qspi_transfer()
664 if (op->data.dir == SPI_MEM_DATA_IN) { in atmel_qspi_transfer()
665 memcpy_fromio(op->data.buf.in, aq->mem + offset, in atmel_qspi_transfer()
666 op->data.nbytes); in atmel_qspi_transfer()
671 memcpy_toio(aq->mem + offset, op->data.buf.out, in atmel_qspi_transfer()
672 op->data.nbytes); in atmel_qspi_transfer()
678 /* Release the chip-select */ in atmel_qspi_transfer()
691 icr = FIELD_PREP(QSPI_ICR_INST_MASK_SAMA7G5, op->cmd.opcode); in atmel_qspi_sama7g5_set_cfg()
699 if (op->dummy.buswidth && op->dummy.nbytes) { in atmel_qspi_sama7g5_set_cfg()
700 if (op->addr.dtr && op->dummy.dtr && op->data.dtr) in atmel_qspi_sama7g5_set_cfg()
701 ifr |= QSPI_IFR_NBDUM(op->dummy.nbytes * 8 / in atmel_qspi_sama7g5_set_cfg()
702 (2 * op->dummy.buswidth)); in atmel_qspi_sama7g5_set_cfg()
704 ifr |= QSPI_IFR_NBDUM(op->dummy.nbytes * 8 / in atmel_qspi_sama7g5_set_cfg()
705 op->dummy.buswidth); in atmel_qspi_sama7g5_set_cfg()
708 if (op->addr.buswidth && op->addr.nbytes) { in atmel_qspi_sama7g5_set_cfg()
709 ifr |= FIELD_PREP(QSPI_IFR_ADDRL_SAMA7G5, op->addr.nbytes - 1) | in atmel_qspi_sama7g5_set_cfg()
711 iar = FIELD_PREP(QSPI_IAR_ADDR, op->addr.val); in atmel_qspi_sama7g5_set_cfg()
714 if (op->addr.dtr && op->dummy.dtr && op->data.dtr) { in atmel_qspi_sama7g5_set_cfg()
716 if (op->cmd.dtr) in atmel_qspi_sama7g5_set_cfg()
722 if (op->cmd.buswidth == 8 || op->addr.buswidth == 8 || in atmel_qspi_sama7g5_set_cfg()
723 op->data.buswidth == 8) in atmel_qspi_sama7g5_set_cfg()
726 /* offset of the data access in the QSPI memory space */ in atmel_qspi_sama7g5_set_cfg()
730 if (op->data.nbytes) { in atmel_qspi_sama7g5_set_cfg()
733 if (op->addr.nbytes) in atmel_qspi_sama7g5_set_cfg()
744 /* Set QSPI Instruction Frame registers */ in atmel_qspi_sama7g5_set_cfg()
745 if (op->addr.nbytes && !op->data.nbytes) in atmel_qspi_sama7g5_set_cfg()
748 if (op->data.dir == SPI_MEM_DATA_IN) { in atmel_qspi_sama7g5_set_cfg()
752 if (op->data.nbytes) in atmel_qspi_sama7g5_set_cfg()
754 op->data.nbytes), in atmel_qspi_sama7g5_set_cfg()
767 complete(&aq->dma_completion); in atmel_qspi_dma_callback()
781 dev_err(&aq->pdev->dev, "device_prep_dma_memcpy error\n"); in atmel_qspi_dma_xfer()
782 return -EIO; in atmel_qspi_dma_xfer()
785 reinit_completion(&aq->dma_completion); in atmel_qspi_dma_xfer()
786 tx->callback = atmel_qspi_dma_callback; in atmel_qspi_dma_xfer()
787 tx->callback_param = aq; in atmel_qspi_dma_xfer()
788 cookie = tx->tx_submit(tx); in atmel_qspi_dma_xfer()
791 dev_err(&aq->pdev->dev, "dma_submit_error %d\n", cookie); in atmel_qspi_dma_xfer()
796 ret = wait_for_completion_timeout(&aq->dma_completion, in atmel_qspi_dma_xfer()
800 dev_err(&aq->pdev->dev, "DMA wait_for_completion_timeout\n"); in atmel_qspi_dma_xfer()
801 return -ETIMEDOUT; in atmel_qspi_dma_xfer()
812 spi_controller_get_devdata(mem->spi->controller); in atmel_qspi_dma_rx_xfer()
818 dma_src = aq->mmap_phys_base + loff; in atmel_qspi_dma_rx_xfer()
820 for_each_sg(sgt->sgl, sg, sgt->nents, i) { in atmel_qspi_dma_rx_xfer()
822 ret = atmel_qspi_dma_xfer(aq, aq->rx_chan, sg_dma_address(sg), in atmel_qspi_dma_rx_xfer()
837 spi_controller_get_devdata(mem->spi->controller); in atmel_qspi_dma_tx_xfer()
843 dma_dst = aq->mmap_phys_base + loff; in atmel_qspi_dma_tx_xfer()
845 for_each_sg(sgt->sgl, sg, sgt->nents, i) { in atmel_qspi_dma_tx_xfer()
847 ret = atmel_qspi_dma_xfer(aq, aq->tx_chan, dma_dst, in atmel_qspi_dma_tx_xfer()
863 ret = spi_controller_dma_map_mem_op_data(mem->spi->controller, op, in atmel_qspi_dma_transfer()
868 if (op->data.dir == SPI_MEM_DATA_IN) in atmel_qspi_dma_transfer()
873 spi_controller_dma_unmap_mem_op_data(mem->spi->controller, op, &sgt); in atmel_qspi_dma_transfer()
882 spi_controller_get_devdata(mem->spi->controller); in atmel_qspi_sama7g5_transfer()
886 if (!op->data.nbytes) { in atmel_qspi_sama7g5_transfer()
897 if (op->data.dir == SPI_MEM_DATA_IN) { in atmel_qspi_sama7g5_transfer()
898 if (aq->rx_chan && op->addr.nbytes && in atmel_qspi_sama7g5_transfer()
899 op->data.nbytes > ATMEL_QSPI_DMA_MIN_BYTES) { in atmel_qspi_sama7g5_transfer()
904 memcpy_fromio(op->data.buf.in, aq->mem + offset, in atmel_qspi_sama7g5_transfer()
905 op->data.nbytes); in atmel_qspi_sama7g5_transfer()
908 if (op->addr.nbytes) { in atmel_qspi_sama7g5_transfer()
909 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, in atmel_qspi_sama7g5_transfer()
916 if (aq->tx_chan && op->addr.nbytes && in atmel_qspi_sama7g5_transfer()
917 op->data.nbytes > ATMEL_QSPI_DMA_MIN_BYTES) { in atmel_qspi_sama7g5_transfer()
922 memcpy_toio(aq->mem + offset, op->data.buf.out, in atmel_qspi_sama7g5_transfer()
923 op->data.nbytes); in atmel_qspi_sama7g5_transfer()
931 /* Release the chip-select. */ in atmel_qspi_sama7g5_transfer()
942 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller); in atmel_qspi_exec_op()
951 if (op->addr.val + op->data.nbytes > aq->mmap_size) in atmel_qspi_exec_op()
952 return -EOPNOTSUPP; in atmel_qspi_exec_op()
954 if (op->addr.nbytes > 4) in atmel_qspi_exec_op()
955 return -EOPNOTSUPP; in atmel_qspi_exec_op()
957 err = pm_runtime_resume_and_get(&aq->pdev->dev); in atmel_qspi_exec_op()
961 err = aq->ops->set_cfg(aq, op, &offset); in atmel_qspi_exec_op()
965 err = aq->ops->transfer(mem, op, offset); in atmel_qspi_exec_op()
968 pm_runtime_mark_last_busy(&aq->pdev->dev); in atmel_qspi_exec_op()
969 pm_runtime_put_autosuspend(&aq->pdev->dev); in atmel_qspi_exec_op()
975 return dev_name(spimem->spi->dev.parent); in atmel_qspi_get_name()
991 pclk_rate = clk_get_rate(aq->pclk); in atmel_qspi_set_pad_calibration()
993 return -EINVAL; in atmel_qspi_set_pad_calibration()
1006 if (pclk_rate > pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE - 1].pclk_rate) in atmel_qspi_set_pad_calibration()
1007 pclk_div = pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE - 1].pclk_div; in atmel_qspi_set_pad_calibration()
1009 /* Disable QSPI while configuring the pad calibration. */ in atmel_qspi_set_pad_calibration()
1020 * and the start-up time is only required for the first calibration in atmel_qspi_set_pad_calibration()
1034 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, in atmel_qspi_set_pad_calibration()
1041 aq->target_max_speed_hz / 1000), in atmel_qspi_set_pad_calibration()
1057 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, in atmel_qspi_set_gclk()
1064 if (aq->target_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) in atmel_qspi_set_gclk()
1069 ret = clk_set_rate(aq->gclk, aq->target_max_speed_hz); in atmel_qspi_set_gclk()
1071 dev_err(&aq->pdev->dev, "Failed to set generic clock rate.\n"); in atmel_qspi_set_gclk()
1075 /* Enable the QSPI generic clock */ in atmel_qspi_set_gclk()
1076 ret = clk_prepare_enable(aq->gclk); in atmel_qspi_set_gclk()
1078 dev_err(&aq->pdev->dev, "Failed to enable generic clock.\n"); in atmel_qspi_set_gclk()
1092 if (aq->caps->octal) { in atmel_qspi_sama7g5_init()
1098 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, in atmel_qspi_sama7g5_init()
1103 /* Set the QSPI controller by default in Serial Memory Mode */ in atmel_qspi_sama7g5_init()
1104 aq->mr |= QSPI_MR_DQSDLYEN; in atmel_qspi_sama7g5_init()
1109 /* Enable the QSPI controller. */ in atmel_qspi_sama7g5_init()
1111 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, in atmel_qspi_sama7g5_init()
1117 if (aq->caps->octal) { in atmel_qspi_sama7g5_init()
1118 ret = readl_poll_timeout(aq->regs + QSPI_SR, val, in atmel_qspi_sama7g5_init()
1129 struct atmel_qspi *aq = spi_controller_get_devdata(spi->controller); in atmel_qspi_sama7g5_setup()
1132 aq->target_max_speed_hz = spi->max_speed_hz; in atmel_qspi_sama7g5_setup()
1139 struct spi_controller *ctrl = spi->controller; in atmel_qspi_setup()
1145 if (ctrl->busy) in atmel_qspi_setup()
1146 return -EBUSY; in atmel_qspi_setup()
1148 if (!spi->max_speed_hz) in atmel_qspi_setup()
1149 return -EINVAL; in atmel_qspi_setup()
1151 if (aq->caps->has_gclk) in atmel_qspi_setup()
1154 src_rate = clk_get_rate(aq->pclk); in atmel_qspi_setup()
1156 return -EINVAL; in atmel_qspi_setup()
1158 /* Compute the QSPI baudrate */ in atmel_qspi_setup()
1159 scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz); in atmel_qspi_setup()
1161 scbr--; in atmel_qspi_setup()
1163 ret = pm_runtime_resume_and_get(ctrl->dev.parent); in atmel_qspi_setup()
1167 aq->scr &= ~QSPI_SCR_SCBR_MASK; in atmel_qspi_setup()
1168 aq->scr |= QSPI_SCR_SCBR(scbr); in atmel_qspi_setup()
1169 atmel_qspi_write(aq->scr, aq, QSPI_SCR); in atmel_qspi_setup()
1171 pm_runtime_mark_last_busy(ctrl->dev.parent); in atmel_qspi_setup()
1172 pm_runtime_put_autosuspend(ctrl->dev.parent); in atmel_qspi_setup()
1179 struct spi_controller *ctrl = spi->controller; in atmel_qspi_set_cs_timing()
1188 clk_rate = clk_get_rate(aq->pclk); in atmel_qspi_set_cs_timing()
1190 return -EINVAL; in atmel_qspi_set_cs_timing()
1193 delay = spi_delay_to_ns(&spi->cs_hold, NULL); in atmel_qspi_set_cs_timing()
1194 if (aq->mr & QSPI_MR_SMM) { in atmel_qspi_set_cs_timing()
1196 dev_warn(&aq->pdev->dev, in atmel_qspi_set_cs_timing()
1200 delay = spi_delay_to_ns(&spi->cs_hold, NULL); in atmel_qspi_set_cs_timing()
1208 delay = spi_delay_to_ns(&spi->cs_setup, NULL); in atmel_qspi_set_cs_timing()
1216 delay = spi_delay_to_ns(&spi->cs_inactive, NULL); in atmel_qspi_set_cs_timing()
1221 ret = pm_runtime_resume_and_get(ctrl->dev.parent); in atmel_qspi_set_cs_timing()
1225 aq->scr &= ~QSPI_SCR_DLYBS_MASK; in atmel_qspi_set_cs_timing()
1226 aq->scr |= QSPI_SCR_DLYBS(cs_setup); in atmel_qspi_set_cs_timing()
1227 atmel_qspi_write(aq->scr, aq, QSPI_SCR); in atmel_qspi_set_cs_timing()
1229 aq->mr &= ~(QSPI_MR_DLYBCT_MASK | QSPI_MR_DLYCS_MASK); in atmel_qspi_set_cs_timing()
1230 aq->mr |= QSPI_MR_DLYBCT(cs_hold) | QSPI_MR_DLYCS(cs_inactive); in atmel_qspi_set_cs_timing()
1231 atmel_qspi_write(aq->mr, aq, QSPI_MR); in atmel_qspi_set_cs_timing()
1233 pm_runtime_mark_last_busy(ctrl->dev.parent); in atmel_qspi_set_cs_timing()
1234 pm_runtime_put_autosuspend(ctrl->dev.parent); in atmel_qspi_set_cs_timing()
1243 if (aq->caps->has_gclk) { in atmel_qspi_init()
1251 /* Reset the QSPI controller */ in atmel_qspi_init()
1254 /* Set the QSPI controller by default in Serial Memory Mode */ in atmel_qspi_init()
1259 /* Enable the QSPI controller */ in atmel_qspi_init()
1276 aq->pending |= pending; in atmel_qspi_interrupt()
1277 if ((aq->pending & aq->irq_mask) == aq->irq_mask) in atmel_qspi_interrupt()
1278 complete(&aq->cmd_completion); in atmel_qspi_interrupt()
1288 aq->rx_chan = dma_request_chan(&aq->pdev->dev, "rx"); in atmel_qspi_dma_init()
1289 if (IS_ERR(aq->rx_chan)) { in atmel_qspi_dma_init()
1290 aq->rx_chan = NULL; in atmel_qspi_dma_init()
1291 return dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->rx_chan), in atmel_qspi_dma_init()
1295 aq->tx_chan = dma_request_chan(&aq->pdev->dev, "tx"); in atmel_qspi_dma_init()
1296 if (IS_ERR(aq->tx_chan)) { in atmel_qspi_dma_init()
1297 ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->tx_chan), in atmel_qspi_dma_init()
1302 ctrl->dma_rx = aq->rx_chan; in atmel_qspi_dma_init()
1303 ctrl->dma_tx = aq->tx_chan; in atmel_qspi_dma_init()
1304 init_completion(&aq->dma_completion); in atmel_qspi_dma_init()
1306 dev_info(&aq->pdev->dev, "Using %s (tx) and %s (rx) for DMA transfers\n", in atmel_qspi_dma_init()
1307 dma_chan_name(aq->tx_chan), dma_chan_name(aq->rx_chan)); in atmel_qspi_dma_init()
1312 dma_release_channel(aq->rx_chan); in atmel_qspi_dma_init()
1313 aq->rx_chan = NULL; in atmel_qspi_dma_init()
1314 aq->tx_chan = NULL; in atmel_qspi_dma_init()
1320 if (aq->rx_chan) in atmel_qspi_dma_release()
1321 dma_release_channel(aq->rx_chan); in atmel_qspi_dma_release()
1322 if (aq->tx_chan) in atmel_qspi_dma_release()
1323 dma_release_channel(aq->tx_chan); in atmel_qspi_dma_release()
1343 ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(*aq)); in atmel_qspi_probe()
1345 return -ENOMEM; in atmel_qspi_probe()
1349 aq->caps = of_device_get_match_data(&pdev->dev); in atmel_qspi_probe()
1350 if (!aq->caps) { in atmel_qspi_probe()
1351 dev_err(&pdev->dev, "Could not retrieve QSPI caps\n"); in atmel_qspi_probe()
1352 return -EINVAL; in atmel_qspi_probe()
1355 init_completion(&aq->cmd_completion); in atmel_qspi_probe()
1356 aq->pdev = pdev; in atmel_qspi_probe()
1358 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; in atmel_qspi_probe()
1359 if (aq->caps->octal) in atmel_qspi_probe()
1360 ctrl->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; in atmel_qspi_probe()
1362 if (aq->caps->has_gclk) in atmel_qspi_probe()
1363 aq->ops = &atmel_qspi_sama7g5_ops; in atmel_qspi_probe()
1365 aq->ops = &atmel_qspi_ops; in atmel_qspi_probe()
1367 ctrl->max_speed_hz = aq->caps->max_speed_hz; in atmel_qspi_probe()
1368 ctrl->setup = atmel_qspi_setup; in atmel_qspi_probe()
1369 ctrl->set_cs_timing = atmel_qspi_set_cs_timing; in atmel_qspi_probe()
1370 ctrl->bus_num = -1; in atmel_qspi_probe()
1371 ctrl->mem_ops = &atmel_qspi_mem_ops; in atmel_qspi_probe()
1372 ctrl->num_chipselect = 1; in atmel_qspi_probe()
1373 ctrl->dev.of_node = pdev->dev.of_node; in atmel_qspi_probe()
1377 aq->regs = devm_platform_ioremap_resource_byname(pdev, "qspi_base"); in atmel_qspi_probe()
1378 if (IS_ERR(aq->regs)) in atmel_qspi_probe()
1379 return dev_err_probe(&pdev->dev, PTR_ERR(aq->regs), in atmel_qspi_probe()
1384 aq->mem = devm_ioremap_resource(&pdev->dev, res); in atmel_qspi_probe()
1385 if (IS_ERR(aq->mem)) in atmel_qspi_probe()
1386 return dev_err_probe(&pdev->dev, PTR_ERR(aq->mem), in atmel_qspi_probe()
1389 aq->mmap_size = resource_size(res); in atmel_qspi_probe()
1390 aq->mmap_phys_base = (dma_addr_t)res->start; in atmel_qspi_probe()
1393 aq->pclk = devm_clk_get_enabled(&pdev->dev, "pclk"); in atmel_qspi_probe()
1394 if (IS_ERR(aq->pclk)) in atmel_qspi_probe()
1395 aq->pclk = devm_clk_get_enabled(&pdev->dev, NULL); in atmel_qspi_probe()
1397 if (IS_ERR(aq->pclk)) in atmel_qspi_probe()
1398 return dev_err_probe(&pdev->dev, PTR_ERR(aq->pclk), in atmel_qspi_probe()
1401 if (aq->caps->has_qspick) { in atmel_qspi_probe()
1402 /* Get the QSPI system clock */ in atmel_qspi_probe()
1403 aq->qspick = devm_clk_get_enabled(&pdev->dev, "qspick"); in atmel_qspi_probe()
1404 if (IS_ERR(aq->qspick)) { in atmel_qspi_probe()
1405 dev_err(&pdev->dev, "missing system clock\n"); in atmel_qspi_probe()
1406 err = PTR_ERR(aq->qspick); in atmel_qspi_probe()
1410 } else if (aq->caps->has_gclk) { in atmel_qspi_probe()
1411 /* Get the QSPI generic clock */ in atmel_qspi_probe()
1412 aq->gclk = devm_clk_get(&pdev->dev, "gclk"); in atmel_qspi_probe()
1413 if (IS_ERR(aq->gclk)) { in atmel_qspi_probe()
1414 dev_err(&pdev->dev, "missing Generic clock\n"); in atmel_qspi_probe()
1415 err = PTR_ERR(aq->gclk); in atmel_qspi_probe()
1420 if (aq->caps->has_dma) { in atmel_qspi_probe()
1422 if (err == -EPROBE_DEFER) in atmel_qspi_probe()
1432 err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt, in atmel_qspi_probe()
1433 0, dev_name(&pdev->dev), aq); in atmel_qspi_probe()
1437 pm_runtime_set_autosuspend_delay(&pdev->dev, 500); in atmel_qspi_probe()
1438 pm_runtime_use_autosuspend(&pdev->dev); in atmel_qspi_probe()
1439 pm_runtime_set_active(&pdev->dev); in atmel_qspi_probe()
1440 pm_runtime_enable(&pdev->dev); in atmel_qspi_probe()
1441 pm_runtime_get_noresume(&pdev->dev); in atmel_qspi_probe()
1449 pm_runtime_put_noidle(&pdev->dev); in atmel_qspi_probe()
1450 pm_runtime_disable(&pdev->dev); in atmel_qspi_probe()
1451 pm_runtime_set_suspended(&pdev->dev); in atmel_qspi_probe()
1452 pm_runtime_dont_use_autosuspend(&pdev->dev); in atmel_qspi_probe()
1455 pm_runtime_mark_last_busy(&pdev->dev); in atmel_qspi_probe()
1456 pm_runtime_put_autosuspend(&pdev->dev); in atmel_qspi_probe()
1461 if (aq->caps->has_dma) in atmel_qspi_probe()
1472 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, in atmel_qspi_sama7g5_suspend()
1480 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, in atmel_qspi_sama7g5_suspend()
1486 clk_disable_unprepare(aq->gclk); in atmel_qspi_sama7g5_suspend()
1489 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, in atmel_qspi_sama7g5_suspend()
1495 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, in atmel_qspi_sama7g5_suspend()
1512 ret = pm_runtime_get_sync(&pdev->dev); in atmel_qspi_remove()
1514 if (aq->caps->has_dma) in atmel_qspi_remove()
1517 if (aq->caps->has_gclk) { in atmel_qspi_remove()
1520 dev_warn(&pdev->dev, "Failed to de-init device on remove: %d\n", ret); in atmel_qspi_remove()
1531 dev_warn(&pdev->dev, "Failed to resume device on remove\n"); in atmel_qspi_remove()
1534 pm_runtime_disable(&pdev->dev); in atmel_qspi_remove()
1535 pm_runtime_dont_use_autosuspend(&pdev->dev); in atmel_qspi_remove()
1536 pm_runtime_put_noidle(&pdev->dev); in atmel_qspi_remove()
1549 if (aq->caps->has_gclk) { in atmel_qspi_suspend()
1551 clk_disable_unprepare(aq->pclk); in atmel_qspi_suspend()
1560 clk_unprepare(aq->qspick); in atmel_qspi_suspend()
1561 clk_unprepare(aq->pclk); in atmel_qspi_suspend()
1572 ret = clk_prepare(aq->pclk); in atmel_qspi_resume()
1576 ret = clk_prepare(aq->qspick); in atmel_qspi_resume()
1578 clk_unprepare(aq->pclk); in atmel_qspi_resume()
1582 if (aq->caps->has_gclk) in atmel_qspi_resume()
1591 atmel_qspi_write(aq->scr, aq, QSPI_SCR); in atmel_qspi_resume()
1604 clk_disable(aq->qspick); in atmel_qspi_runtime_suspend()
1605 clk_disable(aq->pclk); in atmel_qspi_runtime_suspend()
1616 ret = clk_enable(aq->pclk); in atmel_qspi_runtime_resume()
1620 ret = clk_enable(aq->qspick); in atmel_qspi_runtime_resume()
1622 clk_disable(aq->pclk); in atmel_qspi_runtime_resume()
1655 .compatible = "atmel,sama5d2-qspi",
1659 .compatible = "microchip,sam9x60-qspi",
1663 .compatible = "microchip,sama7g5-ospi",
1667 .compatible = "microchip,sama7g5-qspi",
1689 MODULE_DESCRIPTION("Atmel QSPI Controller driver");