Lines Matching +full:op +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
11 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
17 #include <linux/dma-mapping.h>
29 #include <linux/spi/spi-mem.h>
33 #define QSPI_MR 0x0004 /* Mode Register */
49 #define QSPI_SMR 0x0040 /* Scrambling Mode Register */
59 #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
81 /* Bitfields in QSPI_MR (Mode Register) */
92 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
186 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
217 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
237 * struct atmel_qspi_pcal - Pad Calibration Clock Division
296 int (*set_cfg)(struct atmel_qspi *aq, const struct spi_mem_op *op,
298 int (*transfer)(struct spi_mem *mem, const struct spi_mem_op *op,
397 u32 value = readl_relaxed(aq->regs + offset);
402 dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value,
414 dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value,
418 writel_relaxed(value, aq->regs + offset);
426 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
443 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
444 const struct atmel_qspi_mode *mode)
446 if (op->cmd.buswidth != mode->cmd_buswidth)
449 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
452 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
458 static int atmel_qspi_find_mode(const struct spi_mem_op *op)
463 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
466 return -EOPNOTSUPP;
469 static int atmel_qspi_sama7g5_find_mode(const struct spi_mem_op *op)
474 if (atmel_qspi_is_compatible(op, &atmel_qspi_sama7g5_modes[i]))
477 return -EOPNOTSUPP;
481 const struct spi_mem_op *op)
483 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller);
484 if (!spi_mem_default_supports_op(mem, op))
487 if (aq->caps->octal) {
488 if (atmel_qspi_sama7g5_find_mode(op) < 0)
494 if (atmel_qspi_find_mode(op) < 0)
498 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
499 op->dummy.nbytes == 0)
506 * If the QSPI controller is set in regular SPI mode, set it in
507 * Serial Memory Mode (SMM).
513 if (!(aq->mr & QSPI_MR_SMM)) {
514 aq->mr |= QSPI_MR_SMM;
515 atmel_qspi_write(aq->mr, aq, QSPI_MR);
517 if (aq->caps->has_gclk)
525 const struct spi_mem_op *op, u32 *offset)
529 int mode;
532 icr = QSPI_ICR_INST(op->cmd.opcode);
535 mode = atmel_qspi_find_mode(op);
536 if (mode < 0)
537 return mode;
538 ifr |= atmel_qspi_modes[mode].config;
540 if (op->dummy.nbytes)
541 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
544 * The controller allows 24 and 32-bit addressing while NAND-flash
545 * requires 16-bit long. Handling 8-bit long addresses is done using
546 * the option field. For the 16-bit addresses, the workaround depends
551 * use the same buswidth). The limitation is when the 16-bit address is
555 if (op->addr.buswidth) {
556 switch (op->addr.nbytes) {
561 icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
564 if (dummy_cycles < 8 / op->addr.buswidth) {
567 iar = (op->cmd.opcode << 16) |
568 (op->addr.val & 0xffff);
571 iar = (op->addr.val << 8) & 0xffffff;
572 dummy_cycles -= 8 / op->addr.buswidth;
577 iar = op->addr.val & 0xffffff;
581 iar = op->addr.val & 0x7ffffff;
584 return -ENOTSUPP;
596 if (op->data.nbytes) {
599 if (op->addr.nbytes)
603 mode = atmel_qspi_set_serial_memory_mode(aq);
604 if (mode < 0)
605 return mode;
611 if (op->addr.nbytes && !op->data.nbytes)
614 if (aq->caps->has_ricr) {
615 if (op->data.dir == SPI_MEM_DATA_IN)
620 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
642 reinit_completion(&aq->cmd_completion);
643 aq->pending = sr & irq_mask;
644 aq->irq_mask = irq_mask;
646 if (!wait_for_completion_timeout(&aq->cmd_completion,
648 err = -ETIMEDOUT;
655 const struct spi_mem_op *op, u32 offset)
657 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller);
660 if (!op->data.nbytes)
668 if (op->data.dir == SPI_MEM_DATA_IN) {
669 memcpy_fromio(op->data.buf.in, aq->mem + offset,
670 op->data.nbytes);
675 memcpy_toio(aq->mem + offset, op->data.buf.out,
676 op->data.nbytes);
682 /* Release the chip-select */
689 const struct spi_mem_op *op, u32 *offset)
692 int mode, ret;
695 icr = FIELD_PREP(QSPI_ICR_INST_MASK_SAMA7G5, op->cmd.opcode);
698 mode = atmel_qspi_sama7g5_find_mode(op);
699 if (mode < 0)
700 return mode;
701 ifr |= atmel_qspi_sama7g5_modes[mode].config;
703 if (op->dummy.buswidth && op->dummy.nbytes) {
704 if (op->addr.dtr && op->dummy.dtr && op->data.dtr)
705 ifr |= QSPI_IFR_NBDUM(op->dummy.nbytes * 8 /
706 (2 * op->dummy.buswidth));
708 ifr |= QSPI_IFR_NBDUM(op->dummy.nbytes * 8 /
709 op->dummy.buswidth);
712 if (op->addr.buswidth && op->addr.nbytes) {
713 ifr |= FIELD_PREP(QSPI_IFR_ADDRL_SAMA7G5, op->addr.nbytes - 1) |
715 iar = FIELD_PREP(QSPI_IAR_ADDR, op->addr.val);
718 if (op->addr.dtr && op->dummy.dtr && op->data.dtr) {
720 if (op->cmd.dtr)
726 if (op->cmd.buswidth == 8 || op->addr.buswidth == 8 ||
727 op->data.buswidth == 8)
734 if (op->data.nbytes) {
737 if (op->addr.nbytes)
749 if (op->addr.nbytes && !op->data.nbytes)
752 if (op->data.dir == SPI_MEM_DATA_IN) {
756 if (op->data.nbytes)
758 op->data.nbytes),
771 complete(&aq->dma_completion);
785 dev_err(&aq->pdev->dev, "device_prep_dma_memcpy error\n");
786 return -EIO;
789 reinit_completion(&aq->dma_completion);
790 tx->callback = atmel_qspi_dma_callback;
791 tx->callback_param = aq;
792 cookie = tx->tx_submit(tx);
795 dev_err(&aq->pdev->dev, "dma_submit_error %d\n", cookie);
800 ret = wait_for_completion_timeout(&aq->dma_completion,
804 dev_err(&aq->pdev->dev, "DMA wait_for_completion_timeout\n");
805 return -ETIMEDOUT;
812 const struct spi_mem_op *op,
816 spi_controller_get_devdata(mem->spi->controller);
822 dma_src = aq->mmap_phys_base + loff;
824 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
826 ret = atmel_qspi_dma_xfer(aq, aq->rx_chan, sg_dma_address(sg),
837 const struct spi_mem_op *op,
841 spi_controller_get_devdata(mem->spi->controller);
847 dma_dst = aq->mmap_phys_base + loff;
849 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
851 ret = atmel_qspi_dma_xfer(aq, aq->tx_chan, dma_dst,
862 const struct spi_mem_op *op, loff_t loff)
867 ret = spi_controller_dma_map_mem_op_data(mem->spi->controller, op,
872 if (op->data.dir == SPI_MEM_DATA_IN)
873 ret = atmel_qspi_dma_rx_xfer(mem, op, &sgt, loff);
875 ret = atmel_qspi_dma_tx_xfer(mem, op, &sgt, loff);
877 spi_controller_dma_unmap_mem_op_data(mem->spi->controller, op, &sgt);
883 const struct spi_mem_op *op, u32 offset)
886 spi_controller_get_devdata(mem->spi->controller);
890 if (!op->data.nbytes) {
901 if (op->data.dir == SPI_MEM_DATA_IN) {
902 if (aq->rx_chan && op->addr.nbytes &&
903 op->data.nbytes > ATMEL_QSPI_DMA_MIN_BYTES) {
904 ret = atmel_qspi_dma_transfer(mem, op, offset);
908 memcpy_fromio(op->data.buf.in, aq->mem + offset,
909 op->data.nbytes);
912 if (op->addr.nbytes) {
913 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
920 if (aq->tx_chan && op->addr.nbytes &&
921 op->data.nbytes > ATMEL_QSPI_DMA_MIN_BYTES) {
922 ret = atmel_qspi_dma_transfer(mem, op, offset);
926 memcpy_toio(aq->mem + offset, op->data.buf.out,
927 op->data.nbytes);
935 /* Release the chip-select. */
944 static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
946 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller);
952 * would be to add support for regular SPI mode and fall back to it
955 if (op->addr.val + op->data.nbytes > aq->mmap_size)
956 return -EOPNOTSUPP;
958 if (op->addr.nbytes > 4)
959 return -EOPNOTSUPP;
961 err = pm_runtime_resume_and_get(&aq->pdev->dev);
965 err = aq->ops->set_cfg(aq, op, &offset);
969 err = aq->ops->transfer(mem, op, offset);
972 pm_runtime_put_autosuspend(&aq->pdev->dev);
978 return dev_name(spimem->spi->dev.parent);
994 pclk_rate = clk_get_rate(aq->pclk);
996 return -EINVAL;
1009 if (pclk_rate > pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE - 1].pclk_rate)
1010 pclk_div = pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE - 1].pclk_div;
1023 * and the start-up time is only required for the first calibration
1034 if (aq->caps->has_dllon)
1044 if (aq->caps->has_dllon)
1045 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
1050 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
1056 aq->target_max_speed_hz / 1000),
1068 if (aq->caps->has_dllon) {
1072 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
1079 if (aq->target_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ)
1085 if (aq->caps->has_2xgclk)
1086 ret = clk_set_rate(aq->gclk, 2 * aq->target_max_speed_hz);
1088 ret = clk_set_rate(aq->gclk, aq->target_max_speed_hz);
1091 dev_err(&aq->pdev->dev, "Failed to set generic clock rate.\n");
1096 ret = clk_prepare_enable(aq->gclk);
1098 dev_err(&aq->pdev->dev, "Failed to enable generic clock.\n");
1113 * Check if the SoC supports pad calibration in Octal SPI mode.
1116 if (aq->caps->octal && aq->caps->has_padcalib) {
1121 } else if (aq->caps->has_dllon) {
1123 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
1128 /* Set the QSPI controller by default in Serial Memory Mode */
1129 aq->mr |= QSPI_MR_DQSDLYEN;
1136 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
1142 if (aq->caps->octal) {
1143 ret = readl_poll_timeout(aq->regs + QSPI_SR, val,
1154 struct atmel_qspi *aq = spi_controller_get_devdata(spi->controller);
1157 aq->target_max_speed_hz = spi->max_speed_hz;
1164 struct spi_controller *ctrl = spi->controller;
1170 if (ctrl->busy)
1171 return -EBUSY;
1173 if (!spi->max_speed_hz)
1174 return -EINVAL;
1176 if (aq->caps->has_gclk)
1179 src_rate = clk_get_rate(aq->pclk);
1181 return -EINVAL;
1184 scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
1186 scbr--;
1188 ret = pm_runtime_resume_and_get(ctrl->dev.parent);
1192 aq->scr &= ~QSPI_SCR_SCBR_MASK;
1193 aq->scr |= QSPI_SCR_SCBR(scbr);
1194 atmel_qspi_write(aq->scr, aq, QSPI_SCR);
1196 pm_runtime_put_autosuspend(ctrl->dev.parent);
1203 struct spi_controller *ctrl = spi->controller;
1212 clk_rate = clk_get_rate(aq->pclk);
1214 return -EINVAL;
1217 delay = spi_delay_to_ns(&spi->cs_hold, NULL);
1218 if (aq->mr & QSPI_MR_SMM) {
1220 dev_warn(&aq->pdev->dev,
1221 "Ignoring cs_hold, must be 0 in Serial Memory Mode.\n");
1224 delay = spi_delay_to_ns(&spi->cs_hold, NULL);
1232 delay = spi_delay_to_ns(&spi->cs_setup, NULL);
1240 delay = spi_delay_to_ns(&spi->cs_inactive, NULL);
1245 ret = pm_runtime_resume_and_get(ctrl->dev.parent);
1249 aq->scr &= ~QSPI_SCR_DLYBS_MASK;
1250 aq->scr |= QSPI_SCR_DLYBS(cs_setup);
1251 atmel_qspi_write(aq->scr, aq, QSPI_SCR);
1253 aq->mr &= ~(QSPI_MR_DLYBCT_MASK | QSPI_MR_DLYCS_MASK);
1254 aq->mr |= QSPI_MR_DLYBCT(cs_hold) | QSPI_MR_DLYCS(cs_inactive);
1255 atmel_qspi_write(aq->mr, aq, QSPI_MR);
1257 pm_runtime_put_autosuspend(ctrl->dev.parent);
1266 if (aq->caps->has_gclk) {
1277 /* Set the QSPI controller by default in Serial Memory Mode */
1299 aq->pending |= pending;
1300 if ((aq->pending & aq->irq_mask) == aq->irq_mask)
1301 complete(&aq->cmd_completion);
1311 aq->rx_chan = devm_dma_request_chan(&aq->pdev->dev, "rx");
1312 if (IS_ERR(aq->rx_chan)) {
1313 ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->rx_chan),
1315 aq->rx_chan = NULL;
1319 aq->tx_chan = devm_dma_request_chan(&aq->pdev->dev, "tx");
1320 if (IS_ERR(aq->tx_chan)) {
1321 ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->tx_chan),
1323 aq->rx_chan = NULL;
1324 aq->tx_chan = NULL;
1328 ctrl->dma_rx = aq->rx_chan;
1329 ctrl->dma_tx = aq->tx_chan;
1330 init_completion(&aq->dma_completion);
1332 dev_info(&aq->pdev->dev, "Using %s (tx) and %s (rx) for DMA transfers\n",
1333 dma_chan_name(aq->tx_chan), dma_chan_name(aq->rx_chan));
1355 ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(*aq));
1357 return -ENOMEM;
1361 aq->caps = of_device_get_match_data(&pdev->dev);
1362 if (!aq->caps) {
1363 dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
1364 return -EINVAL;
1367 init_completion(&aq->cmd_completion);
1368 aq->pdev = pdev;
1370 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
1371 if (aq->caps->octal)
1372 ctrl->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1374 if (aq->caps->has_gclk)
1375 aq->ops = &atmel_qspi_sama7g5_ops;
1377 aq->ops = &atmel_qspi_ops;
1379 ctrl->max_speed_hz = aq->caps->max_speed_hz;
1380 ctrl->setup = atmel_qspi_setup;
1381 ctrl->set_cs_timing = atmel_qspi_set_cs_timing;
1382 ctrl->bus_num = -1;
1383 ctrl->mem_ops = &atmel_qspi_mem_ops;
1384 ctrl->num_chipselect = 1;
1385 ctrl->dev.of_node = pdev->dev.of_node;
1389 aq->regs = devm_platform_ioremap_resource_byname(pdev, "qspi_base");
1390 if (IS_ERR(aq->regs))
1391 return dev_err_probe(&pdev->dev, PTR_ERR(aq->regs),
1396 aq->mem = devm_ioremap_resource(&pdev->dev, res);
1397 if (IS_ERR(aq->mem))
1398 return dev_err_probe(&pdev->dev, PTR_ERR(aq->mem),
1401 aq->mmap_size = resource_size(res);
1402 aq->mmap_phys_base = (dma_addr_t)res->start;
1405 aq->pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
1406 if (IS_ERR(aq->pclk))
1407 aq->pclk = devm_clk_get_enabled(&pdev->dev, NULL);
1409 if (IS_ERR(aq->pclk))
1410 return dev_err_probe(&pdev->dev, PTR_ERR(aq->pclk),
1413 if (aq->caps->has_qspick) {
1415 aq->qspick = devm_clk_get_enabled(&pdev->dev, "qspick");
1416 if (IS_ERR(aq->qspick)) {
1417 dev_err(&pdev->dev, "missing system clock\n");
1418 err = PTR_ERR(aq->qspick);
1422 } else if (aq->caps->has_gclk) {
1424 aq->gclk = devm_clk_get(&pdev->dev, "gclk");
1425 if (IS_ERR(aq->gclk)) {
1426 dev_err(&pdev->dev, "missing Generic clock\n");
1427 err = PTR_ERR(aq->gclk);
1432 if (aq->caps->has_dma) {
1434 if (err == -EPROBE_DEFER)
1443 err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
1444 0, dev_name(&pdev->dev), aq);
1448 pm_runtime_set_autosuspend_delay(&pdev->dev, 500);
1449 pm_runtime_use_autosuspend(&pdev->dev);
1450 devm_pm_runtime_set_active_enabled(&pdev->dev);
1451 devm_pm_runtime_get_noresume(&pdev->dev);
1461 pm_runtime_put_autosuspend(&pdev->dev);
1471 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
1479 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
1485 clk_disable_unprepare(aq->gclk);
1487 if (aq->caps->has_dllon) {
1489 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
1496 if (aq->caps->has_padcalib)
1497 return readl_poll_timeout(aq->regs + QSPI_SR2, val,
1511 ret = pm_runtime_get_sync(&pdev->dev);
1513 if (aq->caps->has_gclk) {
1516 dev_warn(&pdev->dev, "Failed to de-init device on remove: %d\n", ret);
1527 dev_warn(&pdev->dev, "Failed to resume device on remove\n");
1541 if (aq->caps->has_gclk) {
1543 clk_disable_unprepare(aq->pclk);
1552 clk_unprepare(aq->qspick);
1553 clk_unprepare(aq->pclk);
1564 ret = clk_prepare(aq->pclk);
1568 ret = clk_prepare(aq->qspick);
1570 clk_unprepare(aq->pclk);
1574 if (aq->caps->has_gclk)
1583 atmel_qspi_write(aq->scr, aq, QSPI_SCR);
1595 clk_disable(aq->qspick);
1596 clk_disable(aq->pclk);
1607 ret = clk_enable(aq->pclk);
1611 ret = clk_enable(aq->qspick);
1613 clk_disable(aq->pclk);
1677 .compatible = "atmel,sama5d2-qspi",
1681 .compatible = "microchip,sam9x60-qspi",
1685 .compatible = "microchip,sama7g5-ospi",
1689 .compatible = "microchip,sama7g5-qspi",
1693 .compatible = "microchip,sam9x7-ospi",
1697 .compatible = "microchip,sama7d65-ospi",
1701 .compatible = "microchip,sama7d65-qspi",