Lines Matching +full:write +full:- +full:0 +full:- +full:bps
1 // SPDX-License-Identifier: GPL-2.0
25 #define SWRM_COMP_SW_RESET 0x008
26 #define SWRM_COMP_STATUS 0x014
27 #define SWRM_LINK_MANAGER_EE 0x018
29 #define SWRM_FRM_GEN_ENABLED BIT(0)
30 #define SWRM_VERSION_1_3_0 0x01030000
31 #define SWRM_VERSION_1_5_1 0x01050001
32 #define SWRM_VERSION_1_7_0 0x01070000
33 #define SWRM_VERSION_2_0_0 0x02000000
34 #define SWRM_COMP_HW_VERSION 0x00
35 #define SWRM_COMP_CFG_ADDR 0x04
37 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
38 #define SWRM_COMP_PARAMS 0x100
41 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
43 #define SWRM_COMP_MASTER_ID 0x104
44 #define SWRM_V1_3_INTERRUPT_STATUS 0x200
45 #define SWRM_V2_0_INTERRUPT_STATUS 0x5000
46 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
47 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
65 #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204
66 #define SWRM_V1_3_INTERRUPT_CLEAR 0x208
67 #define SWRM_V2_0_INTERRUPT_CLEAR 0x5008
68 #define SWRM_V1_3_INTERRUPT_CPU_EN 0x210
69 #define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004
70 #define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300
71 #define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020
72 #define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304
73 #define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024
74 #define SWRM_CMD_FIFO_CMD 0x308
75 #define SWRM_CMD_FIFO_FLUSH 0x1
76 #define SWRM_V1_3_CMD_FIFO_STATUS 0x30C
77 #define SWRM_V2_0_CMD_FIFO_STATUS 0x5050
80 #define SWRM_CMD_FIFO_CFG_ADDR 0x314
82 #define SWRM_RD_WR_CMD_RETRIES 0x7
83 #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318
84 #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040
86 #define SWRM_ENUMERATOR_CFG_ADDR 0x500
87 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m))
88 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m))
89 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
90 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
92 #define SWRM_MCP_BUS_CTRL 0x1044
94 #define SWRM_MCP_CFG_ADDR 0x1048
96 #define SWRM_DEF_CMD_NO_PINGS 0x1f
97 #define SWRM_MCP_STATUS 0x104C
98 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
99 #define SWRM_MCP_SLV_STATUS 0x1090
100 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
102 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
103 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
104 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
105 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
106 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
107 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
108 #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m)
109 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
110 #define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740
111 #define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac
113 #define SWRM_V2_0_CLK_CTRL 0x5060
114 #define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0)
115 #define SWRM_V2_0_LINK_STATUS 0x5064
117 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
118 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
119 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
120 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
121 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
122 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
123 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
130 #define QCOM_SWRM_MAX_RD_LEN 0x1
133 #define SWRM_MAX_DAIS 0xF
134 #define SWR_INVALID_PARAM 0xFF
135 #define SWR_HSTOP_MAX_VAL 0xF
136 #define SWR_HSTART_MIN_VAL 0x0
137 #define SWR_BROADCAST_CMD_ID 0x0F
204 /* Port numbers are 1 - 14 */
261 [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
283 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_read()
289 if (ret < 0) in qcom_swrm_ahb_reg_read()
294 if (ret < 0) in qcom_swrm_ahb_reg_read()
303 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_write()
311 /* write address register */ in qcom_swrm_ahb_reg_write()
323 *val = readl(ctrl->mmio + reg); in qcom_swrm_cpu_reg_read()
330 writel(val, ctrl->mmio + reg); in qcom_swrm_cpu_reg_write()
344 id = 0; in swrm_get_packed_reg_val()
359 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_rd_fifo_avail()
364 if (fifo_outstanding_data > 0) in swrm_wait_for_rd_fifo_avail()
365 return 0; in swrm_wait_for_rd_fifo_avail()
368 } while (fifo_retry_count--); in swrm_wait_for_rd_fifo_avail()
370 if (fifo_outstanding_data == 0) { in swrm_wait_for_rd_fifo_avail()
371 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__); in swrm_wait_for_rd_fifo_avail()
372 return -EIO; in swrm_wait_for_rd_fifo_avail()
375 return 0; in swrm_wait_for_rd_fifo_avail()
384 /* Check for fifo overflow during write */ in swrm_wait_for_wr_fifo_avail()
385 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_wr_fifo_avail()
389 /* Check for space in write fifo before writing */ in swrm_wait_for_wr_fifo_avail()
390 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) in swrm_wait_for_wr_fifo_avail()
391 return 0; in swrm_wait_for_wr_fifo_avail()
394 } while (fifo_retry_count--); in swrm_wait_for_wr_fifo_avail()
396 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) { in swrm_wait_for_wr_fifo_avail()
397 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__); in swrm_wait_for_wr_fifo_avail()
398 return -EIO; in swrm_wait_for_wr_fifo_avail()
401 return 0; in swrm_wait_for_wr_fifo_avail()
409 /* Check for fifo overflow during write */ in swrm_wait_for_wr_fifo_done()
410 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
416 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
418 fifo_retry_count--; in swrm_wait_for_wr_fifo_done()
419 if (fifo_outstanding_cmds == 0) in swrm_wait_for_wr_fifo_done()
435 int ret = 0; in qcom_swrm_cmd_fifo_wr_cmd()
436 u8 cmd_id = 0x0; in qcom_swrm_cmd_fifo_wr_cmd()
443 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, in qcom_swrm_cmd_fifo_wr_cmd()
451 reinit_completion(&ctrl->broadcast); in qcom_swrm_cmd_fifo_wr_cmd()
453 /* Its assumed that write is okay as we do not get any status back */ in qcom_swrm_cmd_fifo_wr_cmd()
454 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); in qcom_swrm_cmd_fifo_wr_cmd()
456 if (ctrl->version <= SWRM_VERSION_1_3_0) in qcom_swrm_cmd_fifo_wr_cmd()
465 ret = wait_for_completion_timeout(&ctrl->broadcast, in qcom_swrm_cmd_fifo_wr_cmd()
482 u32 cmd_data, cmd_id, val, retry_attempt = 0; in qcom_swrm_cmd_fifo_rd_cmd()
484 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr); in qcom_swrm_cmd_fifo_rd_cmd()
487 * Check for outstanding cmd wrt. write fifo depth to avoid in qcom_swrm_cmd_fifo_rd_cmd()
488 * overflow as read will also increase write fifo cnt. in qcom_swrm_cmd_fifo_rd_cmd()
494 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); in qcom_swrm_cmd_fifo_rd_cmd()
502 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR], in qcom_swrm_cmd_fifo_rd_cmd()
504 rval[0] = cmd_data & 0xFF; in qcom_swrm_cmd_fifo_rd_cmd()
507 if (cmd_id != ctrl->rcmd_id) { in qcom_swrm_cmd_fifo_rd_cmd()
508 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { in qcom_swrm_cmd_fifo_rd_cmd()
511 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, in qcom_swrm_cmd_fifo_rd_cmd()
513 ctrl->reg_write(ctrl, in qcom_swrm_cmd_fifo_rd_cmd()
514 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], in qcom_swrm_cmd_fifo_rd_cmd()
524 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ in qcom_swrm_cmd_fifo_rd_cmd()
525 dev_num: 0x%x, cmd_data: 0x%x\n", in qcom_swrm_cmd_fifo_rd_cmd()
526 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data); in qcom_swrm_cmd_fifo_rd_cmd()
536 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_alert_slave_dev_num()
542 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK; in qcom_swrm_get_alert_slave_dev_num()
547 return -EINVAL; in qcom_swrm_get_alert_slave_dev_num()
555 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_device_status()
556 ctrl->slave_status = val; in qcom_swrm_get_device_status()
563 ctrl->status[i] = s; in qcom_swrm_get_device_status()
573 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); in qcom_swrm_set_slave_dev_num()
579 slave->dev_num = devnum; in qcom_swrm_set_slave_dev_num()
580 mutex_lock(&bus->bus_lock); in qcom_swrm_set_slave_dev_num()
581 set_bit(devnum, bus->assigned); in qcom_swrm_set_slave_dev_num()
582 mutex_unlock(&bus->bus_lock); in qcom_swrm_set_slave_dev_num()
599 if (!ctrl->status[i]) in qcom_swrm_enumerate()
602 /*SCP_Devid5 - Devid 4*/ in qcom_swrm_enumerate()
603 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); in qcom_swrm_enumerate()
605 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ in qcom_swrm_enumerate()
606 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); in qcom_swrm_enumerate()
611 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) | in qcom_swrm_enumerate()
613 ((u64)buf1[0] << 40); in qcom_swrm_enumerate()
617 ctrl->clock_stop_not_supported = false; in qcom_swrm_enumerate()
619 list_for_each_entry_safe(slave, _s, &bus->slaves, node) { in qcom_swrm_enumerate()
620 if (sdw_compare_devid(slave, id) == 0) { in qcom_swrm_enumerate()
622 if (slave->prop.clk_stop_mode1) in qcom_swrm_enumerate()
623 ctrl->clock_stop_not_supported = true; in qcom_swrm_enumerate()
636 complete(&ctrl->enumeration); in qcom_swrm_enumerate()
637 return 0; in qcom_swrm_enumerate()
645 ret = pm_runtime_get_sync(ctrl->dev); in qcom_swrm_wake_irq_handler()
646 if (ret < 0 && ret != -EACCES) { in qcom_swrm_wake_irq_handler()
647 dev_err_ratelimited(ctrl->dev, in qcom_swrm_wake_irq_handler()
650 pm_runtime_put_noidle(ctrl->dev); in qcom_swrm_wake_irq_handler()
654 if (ctrl->wake_irq > 0) { in qcom_swrm_wake_irq_handler()
655 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) in qcom_swrm_wake_irq_handler()
656 disable_irq_nosync(ctrl->wake_irq); in qcom_swrm_wake_irq_handler()
659 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_wake_irq_handler()
660 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_wake_irq_handler()
672 clk_prepare_enable(ctrl->hclk); in qcom_swrm_irq_handler()
674 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], in qcom_swrm_irq_handler()
676 intr_sts_masked = intr_sts & ctrl->intr_mask; in qcom_swrm_irq_handler()
679 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { in qcom_swrm_irq_handler()
687 if (devnum < 0) { in qcom_swrm_irq_handler()
688 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
691 sdw_handle_slave_status(&ctrl->bus, ctrl->status); in qcom_swrm_irq_handler()
697 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n"); in qcom_swrm_irq_handler()
698 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status); in qcom_swrm_irq_handler()
699 if (ctrl->slave_status == slave_status) { in qcom_swrm_irq_handler()
700 dev_dbg(ctrl->dev, "Slave status not changed %x\n", in qcom_swrm_irq_handler()
704 qcom_swrm_enumerate(&ctrl->bus); in qcom_swrm_irq_handler()
705 sdw_handle_slave_status(&ctrl->bus, ctrl->status); in qcom_swrm_irq_handler()
709 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
712 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; in qcom_swrm_irq_handler()
713 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
714 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
715 ctrl->intr_mask); in qcom_swrm_irq_handler()
718 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
719 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
721 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
722 "%s: SWR read FIFO overflow fifo status 0x%x\n", in qcom_swrm_irq_handler()
726 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
727 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
729 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
730 "%s: SWR read FIFO underflow fifo status 0x%x\n", in qcom_swrm_irq_handler()
734 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
735 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
737 dev_err(ctrl->dev, in qcom_swrm_irq_handler()
738 "%s: SWR write FIFO overflow fifo status %x\n", in qcom_swrm_irq_handler()
740 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
743 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
744 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
746 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
747 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", in qcom_swrm_irq_handler()
749 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
752 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
755 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; in qcom_swrm_irq_handler()
756 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
757 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
758 ctrl->intr_mask); in qcom_swrm_irq_handler()
761 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
764 ctrl->intr_mask &= in qcom_swrm_irq_handler()
766 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
767 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
768 ctrl->intr_mask); in qcom_swrm_irq_handler()
771 complete(&ctrl->broadcast); in qcom_swrm_irq_handler()
780 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
781 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
783 dev_err(ctrl->dev, in qcom_swrm_irq_handler()
791 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
798 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], in qcom_swrm_irq_handler()
800 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], in qcom_swrm_irq_handler()
802 intr_sts_masked = intr_sts & ctrl->intr_mask; in qcom_swrm_irq_handler()
805 clk_disable_unprepare(ctrl->hclk); in qcom_swrm_irq_handler()
815 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED], in swrm_wait_for_frame_gen_enabled()
821 } while (retry--); in swrm_wait_for_frame_gen_enabled()
823 dev_err(ctrl->dev, "%s: link status not %s\n", __func__, in swrm_wait_for_frame_gen_enabled()
834 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); in qcom_swrm_init()
835 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); in qcom_swrm_init()
837 reset_control_reset(ctrl->audio_cgcr); in qcom_swrm_init()
839 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); in qcom_swrm_init()
842 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); in qcom_swrm_init()
844 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; in qcom_swrm_init()
846 if (ctrl->version < SWRM_VERSION_2_0_0) in qcom_swrm_init()
847 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], in qcom_swrm_init()
851 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); in qcom_swrm_init()
853 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); in qcom_swrm_init()
855 if (ctrl->version == SWRM_VERSION_1_7_0) { in qcom_swrm_init()
856 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); in qcom_swrm_init()
857 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, in qcom_swrm_init()
859 } else if (ctrl->version >= SWRM_VERSION_2_0_0) { in qcom_swrm_init()
860 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); in qcom_swrm_init()
861 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, in qcom_swrm_init()
864 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); in qcom_swrm_init()
867 /* Configure number of retries of a read/write cmd */ in qcom_swrm_init()
868 if (ctrl->version >= SWRM_VERSION_1_5_1) { in qcom_swrm_init()
869 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
873 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
878 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK); in qcom_swrm_init()
881 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
884 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], in qcom_swrm_init()
885 0xFFFFFFFF); in qcom_swrm_init()
888 if (ctrl->mmio) { in qcom_swrm_init()
889 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_init()
894 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
899 ctrl->slave_status = 0; in qcom_swrm_init()
900 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_init()
901 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); in qcom_swrm_init()
902 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); in qcom_swrm_init()
904 return 0; in qcom_swrm_init()
911 if (ctrl->version >= SWRM_VERSION_2_0_0) { in qcom_swrm_read_prop()
912 bus->multi_link = true; in qcom_swrm_read_prop()
913 bus->hw_sync_min_links = 3; in qcom_swrm_read_prop()
916 return 0; in qcom_swrm_read_prop()
925 if (msg->flags == SDW_MSG_FLAG_READ) { in qcom_swrm_xfer_msg()
926 for (i = 0; i < msg->len;) { in qcom_swrm_xfer_msg()
927 len = min(msg->len - i, QCOM_SWRM_MAX_RD_LEN); in qcom_swrm_xfer_msg()
929 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, in qcom_swrm_xfer_msg()
930 msg->addr + i, len, in qcom_swrm_xfer_msg()
931 &msg->buf[i]); in qcom_swrm_xfer_msg()
937 } else if (msg->flags == SDW_MSG_FLAG_WRITE) { in qcom_swrm_xfer_msg()
938 for (i = 0; i < msg->len; i++) { in qcom_swrm_xfer_msg()
939 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], in qcom_swrm_xfer_msg()
940 msg->dev_num, in qcom_swrm_xfer_msg()
941 msg->addr + i); in qcom_swrm_xfer_msg()
952 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); in qcom_swrm_pre_bank_switch()
956 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_pre_bank_switch()
958 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
959 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
961 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_pre_bank_switch()
970 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), in qcom_swrm_port_params()
971 p_params->bps - 1); in qcom_swrm_port_params()
982 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); in qcom_swrm_transport_params()
985 pcfg = &ctrl->pconfig[params->port_num]; in qcom_swrm_transport_params()
987 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; in qcom_swrm_transport_params()
988 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; in qcom_swrm_transport_params()
989 value |= pcfg->si & 0xff; in qcom_swrm_transport_params()
991 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
995 if (pcfg->si > 0xff) { in qcom_swrm_transport_params()
996 value = (pcfg->si >> 8) & 0xff; in qcom_swrm_transport_params()
997 reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
998 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1003 if (pcfg->lane_control != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
1004 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1005 value = pcfg->lane_control; in qcom_swrm_transport_params()
1006 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1011 if (pcfg->blk_group_count != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
1012 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1013 value = pcfg->blk_group_count; in qcom_swrm_transport_params()
1014 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1019 if (pcfg->hstart != SWR_INVALID_PARAM in qcom_swrm_transport_params()
1020 && pcfg->hstop != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
1021 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1022 value = (pcfg->hstop << 4) | pcfg->hstart; in qcom_swrm_transport_params()
1023 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1025 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1027 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1033 if (pcfg->bp_mode != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
1034 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1035 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); in qcom_swrm_transport_params()
1046 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); in qcom_swrm_port_enable()
1050 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_port_enable()
1052 if (enable_ch->enable) in qcom_swrm_port_enable()
1053 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); in qcom_swrm_port_enable()
1055 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); in qcom_swrm_port_enable()
1057 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_port_enable()
1083 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in qcom_swrm_compute_params()
1084 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { in qcom_swrm_compute_params()
1085 pcfg = &ctrl->pconfig[p_rt->num]; in qcom_swrm_compute_params()
1086 p_rt->transport_params.port_num = p_rt->num; in qcom_swrm_compute_params()
1087 if (pcfg->word_length != SWR_INVALID_PARAM) { in qcom_swrm_compute_params()
1088 sdw_fill_port_params(&p_rt->port_params, in qcom_swrm_compute_params()
1089 p_rt->num, pcfg->word_length + 1, in qcom_swrm_compute_params()
1096 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in qcom_swrm_compute_params()
1097 slave = s_rt->slave; in qcom_swrm_compute_params()
1098 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in qcom_swrm_compute_params()
1099 m_port = slave->m_port_map[p_rt->num]; in qcom_swrm_compute_params()
1100 /* port config starts at offset 0 so -1 from actual port number */ in qcom_swrm_compute_params()
1102 pcfg = &ctrl->pconfig[m_port]; in qcom_swrm_compute_params()
1104 pcfg = &ctrl->pconfig[i]; in qcom_swrm_compute_params()
1105 p_rt->transport_params.port_num = p_rt->num; in qcom_swrm_compute_params()
1106 p_rt->transport_params.sample_interval = in qcom_swrm_compute_params()
1107 pcfg->si + 1; in qcom_swrm_compute_params()
1108 p_rt->transport_params.offset1 = pcfg->off1; in qcom_swrm_compute_params()
1109 p_rt->transport_params.offset2 = pcfg->off2; in qcom_swrm_compute_params()
1110 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; in qcom_swrm_compute_params()
1111 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; in qcom_swrm_compute_params()
1113 p_rt->transport_params.hstart = pcfg->hstart; in qcom_swrm_compute_params()
1114 p_rt->transport_params.hstop = pcfg->hstop; in qcom_swrm_compute_params()
1115 p_rt->transport_params.lane_ctrl = pcfg->lane_control; in qcom_swrm_compute_params()
1116 if (pcfg->word_length != SWR_INVALID_PARAM) { in qcom_swrm_compute_params()
1117 sdw_fill_port_params(&p_rt->port_params, in qcom_swrm_compute_params()
1118 p_rt->num, in qcom_swrm_compute_params()
1119 pcfg->word_length + 1, in qcom_swrm_compute_params()
1128 return 0; in qcom_swrm_compute_params()
1142 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
1144 list_for_each_entry(m_rt, &stream->master_list, stream_node) { in qcom_swrm_stream_free_ports()
1145 port_mask = &ctrl->port_mask; in qcom_swrm_stream_free_ports()
1146 list_for_each_entry(p_rt, &m_rt->port_list, port_node) in qcom_swrm_stream_free_ports()
1147 clear_bit(p_rt->num, port_mask); in qcom_swrm_stream_free_ports()
1150 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
1165 int maxport, pn, nports = 0, ret = 0; in qcom_swrm_stream_alloc_ports()
1176 sconfig.type = stream->type; in qcom_swrm_stream_alloc_ports()
1177 sconfig.bps = 1; in qcom_swrm_stream_alloc_ports()
1179 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
1180 list_for_each_entry(m_rt, &stream->master_list, stream_node) { in qcom_swrm_stream_alloc_ports()
1187 if (ctrl->bus.id != m_rt->bus->id) in qcom_swrm_stream_alloc_ports()
1190 port_mask = &ctrl->port_mask; in qcom_swrm_stream_alloc_ports()
1191 maxport = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_stream_alloc_ports()
1194 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in qcom_swrm_stream_alloc_ports()
1195 slave = s_rt->slave; in qcom_swrm_stream_alloc_ports()
1196 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in qcom_swrm_stream_alloc_ports()
1197 m_port = slave->m_port_map[p_rt->num]; in qcom_swrm_stream_alloc_ports()
1198 /* Port numbers start from 1 - 14*/ in qcom_swrm_stream_alloc_ports()
1205 dev_err(ctrl->dev, "All ports busy\n"); in qcom_swrm_stream_alloc_ports()
1206 ret = -EBUSY; in qcom_swrm_stream_alloc_ports()
1211 pconfig[nports].ch_mask = p_rt->ch_mask; in qcom_swrm_stream_alloc_ports()
1217 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, in qcom_swrm_stream_alloc_ports()
1220 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
1229 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_params()
1230 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_params()
1234 substream->stream); in qcom_swrm_hw_params()
1244 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_free()
1245 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_free()
1248 sdw_stream_remove_master(&ctrl->bus, sruntime); in qcom_swrm_hw_free()
1250 return 0; in qcom_swrm_hw_free()
1256 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_set_sdw_stream()
1258 ctrl->sruntime[dai->id] = stream; in qcom_swrm_set_sdw_stream()
1260 return 0; in qcom_swrm_set_sdw_stream()
1265 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_get_sdw_stream()
1267 return ctrl->sruntime[dai->id]; in qcom_swrm_get_sdw_stream()
1273 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_startup()
1276 ret = pm_runtime_get_sync(ctrl->dev); in qcom_swrm_startup()
1277 if (ret < 0 && ret != -EACCES) { in qcom_swrm_startup()
1278 dev_err_ratelimited(ctrl->dev, in qcom_swrm_startup()
1281 pm_runtime_put_noidle(ctrl->dev); in qcom_swrm_startup()
1285 return 0; in qcom_swrm_startup()
1291 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_shutdown()
1294 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_shutdown()
1295 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_shutdown()
1314 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_register_dais()
1317 struct device *dev = ctrl->dev; in qcom_swrm_register_dais()
1323 return -ENOMEM; in qcom_swrm_register_dais()
1325 for (i = 0; i < num_dais; i++) { in qcom_swrm_register_dais()
1328 return -ENOMEM; in qcom_swrm_register_dais()
1330 if (i < ctrl->num_dout_ports) in qcom_swrm_register_dais()
1335 stream->channels_min = 1; in qcom_swrm_register_dais()
1336 stream->channels_max = 1; in qcom_swrm_register_dais()
1337 stream->rates = SNDRV_PCM_RATE_48000; in qcom_swrm_register_dais()
1338 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; in qcom_swrm_register_dais()
1344 return devm_snd_soc_register_component(ctrl->dev, in qcom_swrm_register_dais()
1351 struct device_node *np = ctrl->dev->of_node; in qcom_swrm_get_port_config()
1355 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; in qcom_swrm_get_port_config()
1364 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_get_port_config()
1366 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); in qcom_swrm_get_port_config()
1367 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); in qcom_swrm_get_port_config()
1369 ret = of_property_read_u32(np, "qcom,din-ports", &val); in qcom_swrm_get_port_config()
1373 if (val > ctrl->num_din_ports) in qcom_swrm_get_port_config()
1374 return -EINVAL; in qcom_swrm_get_port_config()
1376 ctrl->num_din_ports = val; in qcom_swrm_get_port_config()
1378 ret = of_property_read_u32(np, "qcom,dout-ports", &val); in qcom_swrm_get_port_config()
1382 if (val > ctrl->num_dout_ports) in qcom_swrm_get_port_config()
1383 return -EINVAL; in qcom_swrm_get_port_config()
1385 ctrl->num_dout_ports = val; in qcom_swrm_get_port_config()
1387 nports = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_get_port_config()
1389 return -EINVAL; in qcom_swrm_get_port_config()
1391 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ in qcom_swrm_get_port_config()
1392 set_bit(0, &ctrl->port_mask); in qcom_swrm_get_port_config()
1394 ret = of_property_read_u8_array(np, "qcom,ports-offset1", in qcom_swrm_get_port_config()
1399 ret = of_property_read_u8_array(np, "qcom,ports-offset2", in qcom_swrm_get_port_config()
1404 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", in qcom_swrm_get_port_config()
1407 ret = of_property_read_u16_array(np, "qcom,ports-sinterval", in qcom_swrm_get_port_config()
1414 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", in qcom_swrm_get_port_config()
1417 if (ctrl->version <= SWRM_VERSION_1_3_0) in qcom_swrm_get_port_config()
1424 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); in qcom_swrm_get_port_config()
1427 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports); in qcom_swrm_get_port_config()
1430 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports); in qcom_swrm_get_port_config()
1433 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports); in qcom_swrm_get_port_config()
1436 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports); in qcom_swrm_get_port_config()
1438 for (i = 0; i < nports; i++) { in qcom_swrm_get_port_config()
1439 /* Valid port number range is from 1-14 */ in qcom_swrm_get_port_config()
1441 ctrl->pconfig[i + 1].si = si[i]; in qcom_swrm_get_port_config()
1443 ctrl->pconfig[i + 1].si = ((u8 *)si)[i]; in qcom_swrm_get_port_config()
1444 ctrl->pconfig[i + 1].off1 = off1[i]; in qcom_swrm_get_port_config()
1445 ctrl->pconfig[i + 1].off2 = off2[i]; in qcom_swrm_get_port_config()
1446 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; in qcom_swrm_get_port_config()
1447 ctrl->pconfig[i + 1].hstart = hstart[i]; in qcom_swrm_get_port_config()
1448 ctrl->pconfig[i + 1].hstop = hstop[i]; in qcom_swrm_get_port_config()
1449 ctrl->pconfig[i + 1].word_length = word_length[i]; in qcom_swrm_get_port_config()
1450 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; in qcom_swrm_get_port_config()
1451 ctrl->pconfig[i + 1].lane_control = lane_control[i]; in qcom_swrm_get_port_config()
1454 return 0; in qcom_swrm_get_port_config()
1460 struct qcom_swrm_ctrl *ctrl = s_file->private; in swrm_reg_show()
1463 ret = pm_runtime_get_sync(ctrl->dev); in swrm_reg_show()
1464 if (ret < 0 && ret != -EACCES) { in swrm_reg_show()
1465 dev_err_ratelimited(ctrl->dev, in swrm_reg_show()
1468 pm_runtime_put_noidle(ctrl->dev); in swrm_reg_show()
1472 for (reg = 0; reg <= ctrl->max_reg; reg += 4) { in swrm_reg_show()
1473 ctrl->reg_read(ctrl, reg, ®_val); in swrm_reg_show()
1474 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); in swrm_reg_show()
1476 pm_runtime_mark_last_busy(ctrl->dev); in swrm_reg_show()
1477 pm_runtime_put_autosuspend(ctrl->dev); in swrm_reg_show()
1480 return 0; in swrm_reg_show()
1487 struct device *dev = &pdev->dev;
1497 return -ENOMEM;
1500 ctrl->max_reg = data->max_reg;
1501 ctrl->reg_layout = data->reg_layout;
1502 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1503 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1505 if (dev->parent->bus == &slimbus_bus) {
1509 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1510 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1511 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1512 if (!ctrl->regmap)
1513 return -EINVAL;
1515 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1516 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1517 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1518 if (IS_ERR(ctrl->mmio))
1519 return PTR_ERR(ctrl->mmio);
1522 if (data->sw_clk_gate_required) {
1523 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1524 if (IS_ERR(ctrl->audio_cgcr)) {
1526 ret = PTR_ERR(ctrl->audio_cgcr);
1531 ctrl->irq = of_irq_get(dev->of_node, 0);
1532 if (ctrl->irq < 0) {
1533 ret = ctrl->irq;
1537 ctrl->hclk = devm_clk_get(dev, "iface");
1538 if (IS_ERR(ctrl->hclk)) {
1539 ret = dev_err_probe(dev, PTR_ERR(ctrl->hclk), "unable to get iface clock\n");
1543 clk_prepare_enable(ctrl->hclk);
1545 ctrl->dev = dev;
1546 dev_set_drvdata(&pdev->dev, ctrl);
1547 mutex_init(&ctrl->port_lock);
1548 init_completion(&ctrl->broadcast);
1549 init_completion(&ctrl->enumeration);
1551 ctrl->bus.ops = &qcom_swrm_ops;
1552 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1553 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1554 ctrl->bus.clk_stop_timeout = 300;
1560 params = &ctrl->bus.params;
1561 params->max_dr_freq = DEFAULT_CLK_FREQ;
1562 params->curr_dr_freq = DEFAULT_CLK_FREQ;
1563 params->col = data->default_cols;
1564 params->row = data->default_rows;
1565 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1566 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1567 params->next_bank = !params->curr_bank;
1569 prop = &ctrl->bus.prop;
1570 prop->max_clk_freq = DEFAULT_CLK_FREQ;
1571 prop->num_clk_gears = 0;
1572 prop->num_clk_freq = MAX_FREQ_NUM;
1573 prop->clk_freq = &qcom_swrm_freq_tbl[0];
1574 prop->default_col = data->default_cols;
1575 prop->default_row = data->default_rows;
1577 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1579 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1589 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1590 if (ctrl->wake_irq > 0) {
1591 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1601 ctrl->bus.controller_id = -1;
1603 if (ctrl->version > SWRM_VERSION_1_3_0) {
1604 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1605 ctrl->bus.controller_id = val;
1608 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1616 wait_for_completion_timeout(&ctrl->enumeration,
1623 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1624 ctrl->version & 0xffff);
1633 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1634 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1638 return 0;
1641 sdw_bus_master_delete(&ctrl->bus);
1643 clk_disable_unprepare(ctrl->hclk);
1650 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1652 sdw_bus_master_delete(&ctrl->bus);
1653 clk_disable_unprepare(ctrl->hclk);
1661 if (ctrl->wake_irq > 0) {
1662 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1663 disable_irq_nosync(ctrl->wake_irq);
1666 clk_prepare_enable(ctrl->hclk);
1668 if (ctrl->clock_stop_not_supported) {
1669 reinit_completion(&ctrl->enumeration);
1670 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1677 dev_err(ctrl->dev, "link failed to connect\n");
1680 wait_for_completion_timeout(&ctrl->enumeration,
1683 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1685 reset_control_reset(ctrl->audio_cgcr);
1687 if (ctrl->version == SWRM_VERSION_1_7_0) {
1688 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1689 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1691 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1692 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1693 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1696 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1698 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1701 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1702 if (ctrl->version < SWRM_VERSION_2_0_0)
1703 ctrl->reg_write(ctrl,
1704 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1705 ctrl->intr_mask);
1706 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1707 ctrl->intr_mask);
1711 dev_err(ctrl->dev, "link failed to connect\n");
1713 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1714 if (ret < 0)
1715 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1718 return 0;
1727 if (!ctrl->clock_stop_not_supported) {
1729 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1730 if (ctrl->version < SWRM_VERSION_2_0_0)
1731 ctrl->reg_write(ctrl,
1732 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1733 ctrl->intr_mask);
1734 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1735 ctrl->intr_mask);
1737 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1738 if (ret < 0 && ret != -ENODATA) {
1743 ret = sdw_bus_clk_stop(&ctrl->bus);
1744 if (ret < 0 && ret != -ENODATA) {
1750 clk_disable_unprepare(ctrl->hclk);
1754 if (ctrl->wake_irq > 0) {
1755 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1756 enable_irq(ctrl->wake_irq);
1759 return 0;
1767 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1768 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1769 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1770 { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1771 { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },
1781 .name = "qcom-soundwire",