Lines Matching full:ctrl
208 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
209 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
280 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, in qcom_swrm_ahb_reg_read() argument
283 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_read()
300 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_ahb_reg_write() argument
303 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_write()
320 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, in qcom_swrm_cpu_reg_read() argument
323 *val = readl(ctrl->mmio + reg); in qcom_swrm_cpu_reg_read()
327 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, in qcom_swrm_cpu_reg_write() argument
330 writel(val, ctrl->mmio + reg); in qcom_swrm_cpu_reg_write()
352 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl) in swrm_wait_for_rd_fifo_avail() argument
359 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_rd_fifo_avail()
371 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__); in swrm_wait_for_rd_fifo_avail()
378 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl) in swrm_wait_for_wr_fifo_avail() argument
385 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_wr_fifo_avail()
390 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) in swrm_wait_for_wr_fifo_avail()
396 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) { in swrm_wait_for_wr_fifo_avail()
397 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__); in swrm_wait_for_wr_fifo_avail()
404 static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl) in swrm_wait_for_wr_fifo_done() argument
410 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
416 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
430 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, in qcom_swrm_cmd_fifo_wr_cmd() argument
443 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, in qcom_swrm_cmd_fifo_wr_cmd()
447 if (swrm_wait_for_wr_fifo_avail(ctrl)) in qcom_swrm_cmd_fifo_wr_cmd()
451 reinit_completion(&ctrl->broadcast); in qcom_swrm_cmd_fifo_wr_cmd()
454 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); in qcom_swrm_cmd_fifo_wr_cmd()
456 if (ctrl->version <= SWRM_VERSION_1_3_0) in qcom_swrm_cmd_fifo_wr_cmd()
460 swrm_wait_for_wr_fifo_done(ctrl); in qcom_swrm_cmd_fifo_wr_cmd()
465 ret = wait_for_completion_timeout(&ctrl->broadcast, in qcom_swrm_cmd_fifo_wr_cmd()
478 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_cmd_fifo_rd_cmd() argument
484 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr); in qcom_swrm_cmd_fifo_rd_cmd()
490 swrm_wait_for_wr_fifo_avail(ctrl); in qcom_swrm_cmd_fifo_rd_cmd()
494 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); in qcom_swrm_cmd_fifo_rd_cmd()
498 if (swrm_wait_for_rd_fifo_avail(ctrl)) in qcom_swrm_cmd_fifo_rd_cmd()
502 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR], in qcom_swrm_cmd_fifo_rd_cmd()
507 if (cmd_id != ctrl->rcmd_id) { in qcom_swrm_cmd_fifo_rd_cmd()
511 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, in qcom_swrm_cmd_fifo_rd_cmd()
513 ctrl->reg_write(ctrl, in qcom_swrm_cmd_fifo_rd_cmd()
514 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], in qcom_swrm_cmd_fifo_rd_cmd()
524 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ in qcom_swrm_cmd_fifo_rd_cmd()
526 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data); in qcom_swrm_cmd_fifo_rd_cmd()
531 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_get_alert_slave_dev_num() argument
536 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_alert_slave_dev_num()
542 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK; in qcom_swrm_get_alert_slave_dev_num()
550 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_get_device_status() argument
555 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_device_status()
556 ctrl->slave_status = val; in qcom_swrm_get_device_status()
563 ctrl->status[i] = s; in qcom_swrm_get_device_status()
570 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_set_slave_dev_num() local
573 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); in qcom_swrm_set_slave_dev_num()
588 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_enumerate() local
599 if (!ctrl->status[i]) in qcom_swrm_enumerate()
603 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); in qcom_swrm_enumerate()
606 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); in qcom_swrm_enumerate()
617 ctrl->clock_stop_not_supported = false; in qcom_swrm_enumerate()
623 ctrl->clock_stop_not_supported = true; in qcom_swrm_enumerate()
636 complete(&ctrl->enumeration); in qcom_swrm_enumerate()
642 struct qcom_swrm_ctrl *ctrl = dev_id; in qcom_swrm_wake_irq_handler() local
645 ret = pm_runtime_get_sync(ctrl->dev); in qcom_swrm_wake_irq_handler()
647 dev_err_ratelimited(ctrl->dev, in qcom_swrm_wake_irq_handler()
650 pm_runtime_put_noidle(ctrl->dev); in qcom_swrm_wake_irq_handler()
654 if (ctrl->wake_irq > 0) { in qcom_swrm_wake_irq_handler()
655 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) in qcom_swrm_wake_irq_handler()
656 disable_irq_nosync(ctrl->wake_irq); in qcom_swrm_wake_irq_handler()
659 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_wake_irq_handler()
660 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_wake_irq_handler()
667 struct qcom_swrm_ctrl *ctrl = dev_id; in qcom_swrm_irq_handler() local
672 clk_prepare_enable(ctrl->hclk); in qcom_swrm_irq_handler()
674 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], in qcom_swrm_irq_handler()
676 intr_sts_masked = intr_sts & ctrl->intr_mask; in qcom_swrm_irq_handler()
686 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl); in qcom_swrm_irq_handler()
688 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
691 sdw_handle_slave_status(&ctrl->bus, ctrl->status); in qcom_swrm_irq_handler()
697 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n"); in qcom_swrm_irq_handler()
698 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status); in qcom_swrm_irq_handler()
699 if (ctrl->slave_status == slave_status) { in qcom_swrm_irq_handler()
700 dev_dbg(ctrl->dev, "Slave status not changed %x\n", in qcom_swrm_irq_handler()
703 qcom_swrm_get_device_status(ctrl); in qcom_swrm_irq_handler()
704 qcom_swrm_enumerate(&ctrl->bus); in qcom_swrm_irq_handler()
705 sdw_handle_slave_status(&ctrl->bus, ctrl->status); in qcom_swrm_irq_handler()
709 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
712 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; in qcom_swrm_irq_handler()
713 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
714 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
715 ctrl->intr_mask); in qcom_swrm_irq_handler()
718 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
719 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
721 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
726 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
727 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
729 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
734 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
735 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
737 dev_err(ctrl->dev, in qcom_swrm_irq_handler()
740 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
743 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
744 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
746 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
749 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
752 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
755 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; in qcom_swrm_irq_handler()
756 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
757 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
758 ctrl->intr_mask); in qcom_swrm_irq_handler()
761 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
764 ctrl->intr_mask &= in qcom_swrm_irq_handler()
766 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
767 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
768 ctrl->intr_mask); in qcom_swrm_irq_handler()
771 complete(&ctrl->broadcast); in qcom_swrm_irq_handler()
780 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
781 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
783 dev_err(ctrl->dev, in qcom_swrm_irq_handler()
791 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
798 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], in qcom_swrm_irq_handler()
800 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], in qcom_swrm_irq_handler()
802 intr_sts_masked = intr_sts & ctrl->intr_mask; in qcom_swrm_irq_handler()
805 clk_disable_unprepare(ctrl->hclk); in qcom_swrm_irq_handler()
809 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl) in swrm_wait_for_frame_gen_enabled() argument
815 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED], in swrm_wait_for_frame_gen_enabled()
823 dev_err(ctrl->dev, "%s: link status not %s\n", __func__, in swrm_wait_for_frame_gen_enabled()
829 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_init() argument
834 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); in qcom_swrm_init()
835 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); in qcom_swrm_init()
837 reset_control_reset(ctrl->audio_cgcr); in qcom_swrm_init()
839 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); in qcom_swrm_init()
842 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); in qcom_swrm_init()
844 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; in qcom_swrm_init()
846 if (ctrl->version < SWRM_VERSION_2_0_0) in qcom_swrm_init()
847 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], in qcom_swrm_init()
851 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); in qcom_swrm_init()
853 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); in qcom_swrm_init()
855 if (ctrl->version == SWRM_VERSION_1_7_0) { in qcom_swrm_init()
856 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); in qcom_swrm_init()
857 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, in qcom_swrm_init()
859 } else if (ctrl->version >= SWRM_VERSION_2_0_0) { in qcom_swrm_init()
860 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); in qcom_swrm_init()
861 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, in qcom_swrm_init()
864 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); in qcom_swrm_init()
868 if (ctrl->version >= SWRM_VERSION_1_5_1) { in qcom_swrm_init()
869 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
873 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
878 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK); in qcom_swrm_init()
881 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
884 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], in qcom_swrm_init()
888 if (ctrl->mmio) { in qcom_swrm_init()
889 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_init()
894 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
898 swrm_wait_for_frame_gen_enabled(ctrl); in qcom_swrm_init()
899 ctrl->slave_status = 0; in qcom_swrm_init()
900 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_init()
901 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); in qcom_swrm_init()
902 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); in qcom_swrm_init()
909 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_read_prop() local
911 if (ctrl->version >= SWRM_VERSION_2_0_0) { in qcom_swrm_read_prop()
922 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_xfer_msg() local
929 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, in qcom_swrm_xfer_msg()
939 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], in qcom_swrm_xfer_msg()
953 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_pre_bank_switch() local
956 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_pre_bank_switch()
958 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
959 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
961 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_pre_bank_switch()
968 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_port_params() local
970 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), in qcom_swrm_port_params()
979 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_transport_params() local
985 pcfg = &ctrl->pconfig[params->port_num]; in qcom_swrm_transport_params()
991 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
998 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1006 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1014 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1023 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1027 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1035 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); in qcom_swrm_transport_params()
1047 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_port_enable() local
1050 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_port_enable()
1057 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_port_enable()
1074 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_compute_params() local
1085 pcfg = &ctrl->pconfig[p_rt->num]; in qcom_swrm_compute_params()
1102 pcfg = &ctrl->pconfig[m_port]; in qcom_swrm_compute_params()
1104 pcfg = &ctrl->pconfig[i]; in qcom_swrm_compute_params()
1135 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_stream_free_ports() argument
1142 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
1145 port_mask = &ctrl->port_mask; in qcom_swrm_stream_free_ports()
1150 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
1153 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_stream_alloc_ports() argument
1179 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
1187 if (ctrl->bus.id != m_rt->bus->id) in qcom_swrm_stream_alloc_ports()
1190 port_mask = &ctrl->port_mask; in qcom_swrm_stream_alloc_ports()
1191 maxport = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_stream_alloc_ports()
1205 dev_err(ctrl->dev, "All ports busy\n"); in qcom_swrm_stream_alloc_ports()
1217 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, in qcom_swrm_stream_alloc_ports()
1220 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
1229 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_params() local
1230 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_params()
1233 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params, in qcom_swrm_hw_params()
1236 qcom_swrm_stream_free_ports(ctrl, sruntime); in qcom_swrm_hw_params()
1244 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_free() local
1245 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_free()
1247 qcom_swrm_stream_free_ports(ctrl, sruntime); in qcom_swrm_hw_free()
1248 sdw_stream_remove_master(&ctrl->bus, sruntime); in qcom_swrm_hw_free()
1256 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_set_sdw_stream() local
1258 ctrl->sruntime[dai->id] = stream; in qcom_swrm_set_sdw_stream()
1265 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_get_sdw_stream() local
1267 return ctrl->sruntime[dai->id]; in qcom_swrm_get_sdw_stream()
1273 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_startup() local
1276 ret = pm_runtime_get_sync(ctrl->dev); in qcom_swrm_startup()
1278 dev_err_ratelimited(ctrl->dev, in qcom_swrm_startup()
1281 pm_runtime_put_noidle(ctrl->dev); in qcom_swrm_startup()
1291 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_shutdown() local
1293 swrm_wait_for_wr_fifo_done(ctrl); in qcom_swrm_shutdown()
1294 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_shutdown()
1295 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_shutdown()
1312 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_register_dais() argument
1314 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_register_dais()
1317 struct device *dev = ctrl->dev; in qcom_swrm_register_dais()
1330 if (i < ctrl->num_dout_ports) in qcom_swrm_register_dais()
1344 return devm_snd_soc_register_component(ctrl->dev, in qcom_swrm_register_dais()
1349 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_get_port_config() argument
1351 struct device_node *np = ctrl->dev->of_node; in qcom_swrm_get_port_config()
1364 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_get_port_config()
1366 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); in qcom_swrm_get_port_config()
1367 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); in qcom_swrm_get_port_config()
1373 if (val > ctrl->num_din_ports) in qcom_swrm_get_port_config()
1376 ctrl->num_din_ports = val; in qcom_swrm_get_port_config()
1382 if (val > ctrl->num_dout_ports) in qcom_swrm_get_port_config()
1385 ctrl->num_dout_ports = val; in qcom_swrm_get_port_config()
1387 nports = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_get_port_config()
1392 set_bit(0, &ctrl->port_mask); in qcom_swrm_get_port_config()
1417 if (ctrl->version <= SWRM_VERSION_1_3_0) in qcom_swrm_get_port_config()
1441 ctrl->pconfig[i + 1].si = si[i]; in qcom_swrm_get_port_config()
1443 ctrl->pconfig[i + 1].si = ((u8 *)si)[i]; in qcom_swrm_get_port_config()
1444 ctrl->pconfig[i + 1].off1 = off1[i]; in qcom_swrm_get_port_config()
1445 ctrl->pconfig[i + 1].off2 = off2[i]; in qcom_swrm_get_port_config()
1446 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; in qcom_swrm_get_port_config()
1447 ctrl->pconfig[i + 1].hstart = hstart[i]; in qcom_swrm_get_port_config()
1448 ctrl->pconfig[i + 1].hstop = hstop[i]; in qcom_swrm_get_port_config()
1449 ctrl->pconfig[i + 1].word_length = word_length[i]; in qcom_swrm_get_port_config()
1450 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; in qcom_swrm_get_port_config()
1451 ctrl->pconfig[i + 1].lane_control = lane_control[i]; in qcom_swrm_get_port_config()
1460 struct qcom_swrm_ctrl *ctrl = s_file->private; in swrm_reg_show() local
1463 ret = pm_runtime_get_sync(ctrl->dev); in swrm_reg_show()
1465 dev_err_ratelimited(ctrl->dev, in swrm_reg_show()
1468 pm_runtime_put_noidle(ctrl->dev); in swrm_reg_show()
1472 for (reg = 0; reg <= ctrl->max_reg; reg += 4) { in swrm_reg_show()
1473 ctrl->reg_read(ctrl, reg, ®_val); in swrm_reg_show()
1476 pm_runtime_mark_last_busy(ctrl->dev); in swrm_reg_show()
1477 pm_runtime_put_autosuspend(ctrl->dev); in swrm_reg_show()
1490 struct qcom_swrm_ctrl *ctrl; local
1495 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1496 if (!ctrl)
1500 ctrl->max_reg = data->max_reg;
1501 ctrl->reg_layout = data->reg_layout;
1502 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1503 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1509 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1510 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1511 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1512 if (!ctrl->regmap)
1515 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1516 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1517 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1518 if (IS_ERR(ctrl->mmio))
1519 return PTR_ERR(ctrl->mmio);
1523 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1524 if (IS_ERR(ctrl->audio_cgcr)) {
1525 dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1526 ret = PTR_ERR(ctrl->audio_cgcr);
1531 ctrl->irq = of_irq_get(dev->of_node, 0);
1532 if (ctrl->irq < 0) {
1533 ret = ctrl->irq;
1537 ctrl->hclk = devm_clk_get(dev, "iface");
1538 if (IS_ERR(ctrl->hclk)) {
1539 ret = dev_err_probe(dev, PTR_ERR(ctrl->hclk), "unable to get iface clock\n");
1543 clk_prepare_enable(ctrl->hclk);
1545 ctrl->dev = dev;
1546 dev_set_drvdata(&pdev->dev, ctrl);
1547 mutex_init(&ctrl->port_lock);
1548 init_completion(&ctrl->broadcast);
1549 init_completion(&ctrl->enumeration);
1551 ctrl->bus.ops = &qcom_swrm_ops;
1552 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1553 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1554 ctrl->bus.clk_stop_timeout = 300;
1556 ret = qcom_swrm_get_port_config(ctrl);
1560 params = &ctrl->bus.params;
1565 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1569 prop = &ctrl->bus.prop;
1577 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1579 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1583 "soundwire", ctrl);
1589 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1590 if (ctrl->wake_irq > 0) {
1591 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1594 "swr_wake_irq", ctrl);
1601 ctrl->bus.controller_id = -1;
1603 if (ctrl->version > SWRM_VERSION_1_3_0) {
1604 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1605 ctrl->bus.controller_id = val;
1608 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1615 qcom_swrm_init(ctrl);
1616 wait_for_completion_timeout(&ctrl->enumeration,
1618 ret = qcom_swrm_register_dais(ctrl);
1623 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1624 ctrl->version & 0xffff);
1633 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1634 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1641 sdw_bus_master_delete(&ctrl->bus);
1643 clk_disable_unprepare(ctrl->hclk);
1650 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev); local
1652 sdw_bus_master_delete(&ctrl->bus);
1653 clk_disable_unprepare(ctrl->hclk);
1658 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); local
1661 if (ctrl->wake_irq > 0) {
1662 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1663 disable_irq_nosync(ctrl->wake_irq);
1666 clk_prepare_enable(ctrl->hclk);
1668 if (ctrl->clock_stop_not_supported) {
1669 reinit_completion(&ctrl->enumeration);
1670 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1673 qcom_swrm_init(ctrl);
1676 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1677 dev_err(ctrl->dev, "link failed to connect\n");
1680 wait_for_completion_timeout(&ctrl->enumeration,
1682 qcom_swrm_get_device_status(ctrl);
1683 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1685 reset_control_reset(ctrl->audio_cgcr);
1687 if (ctrl->version == SWRM_VERSION_1_7_0) {
1688 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1689 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1691 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1692 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1693 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1696 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1698 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1701 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1702 if (ctrl->version < SWRM_VERSION_2_0_0)
1703 ctrl->reg_write(ctrl,
1704 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1705 ctrl->intr_mask);
1706 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1707 ctrl->intr_mask);
1710 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1711 dev_err(ctrl->dev, "link failed to connect\n");
1713 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1715 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1723 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); local
1726 swrm_wait_for_wr_fifo_done(ctrl);
1727 if (!ctrl->clock_stop_not_supported) {
1729 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1730 if (ctrl->version < SWRM_VERSION_2_0_0)
1731 ctrl->reg_write(ctrl,
1732 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1733 ctrl->intr_mask);
1734 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1735 ctrl->intr_mask);
1737 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1743 ret = sdw_bus_clk_stop(&ctrl->bus);
1750 clk_disable_unprepare(ctrl->hclk);
1754 if (ctrl->wake_irq > 0) {
1755 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1756 enable_irq(ctrl->wake_irq);