Lines Matching +full:lanes +full:- +full:per +full:- +full:direction
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2015-2020 Intel Corporation.
31 unsigned int *lanes; member
42 struct sdw_bus_params *b_params = &m_rt->bus->params; in sdw_compute_slave_ports()
44 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
46 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in sdw_compute_slave_ports()
47 rate = m_rt->stream->params.rate; in sdw_compute_slave_ports()
48 bps = m_rt->stream->params.bps; in sdw_compute_slave_ports()
49 sample_int = (m_rt->bus->params.curr_dr_freq / rate); in sdw_compute_slave_ports()
52 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in sdw_compute_slave_ports()
53 if (p_rt->lane != t_data->lane) in sdw_compute_slave_ports()
56 ch = hweight32(p_rt->ch_mask); in sdw_compute_slave_ports()
58 sdw_fill_xport_params(&p_rt->transport_params, in sdw_compute_slave_ports()
59 p_rt->num, false, in sdw_compute_slave_ports()
62 t_data->hstart, in sdw_compute_slave_ports()
63 t_data->hstop, in sdw_compute_slave_ports()
64 SDW_BLK_PKG_PER_PORT, p_rt->lane); in sdw_compute_slave_ports()
66 sdw_fill_port_params(&p_rt->port_params, in sdw_compute_slave_ports()
67 p_rt->num, bps, in sdw_compute_slave_ports()
69 b_params->s_data_mode); in sdw_compute_slave_ports()
75 if (m_rt->direction == SDW_DATA_DIR_TX && in sdw_compute_slave_ports()
76 m_rt->ch_count == slave_total_ch) { in sdw_compute_slave_ports()
83 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
91 struct sdw_bus *bus = m_rt->bus; in sdw_compute_dp0_slave_ports()
95 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in sdw_compute_dp0_slave_ports()
96 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in sdw_compute_dp0_slave_ports()
97 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num, false, in sdw_compute_dp0_slave_ports()
98 SDW_BLK_GRP_CNT_1, bus->params.col, 0, 0, 1, in sdw_compute_dp0_slave_ports()
99 bus->params.col - 1, SDW_BLK_PKG_PER_PORT, 0x0); in sdw_compute_dp0_slave_ports()
101 sdw_fill_port_params(&p_rt->port_params, p_rt->num, bus->params.col - 1, in sdw_compute_dp0_slave_ports()
110 struct sdw_bus *bus = m_rt->bus; in sdw_compute_dp0_master_ports()
112 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { in sdw_compute_dp0_master_ports()
113 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num, false, in sdw_compute_dp0_master_ports()
114 SDW_BLK_GRP_CNT_1, bus->params.col, 0, 0, 1, in sdw_compute_dp0_master_ports()
115 bus->params.col - 1, SDW_BLK_PKG_PER_PORT, 0x0); in sdw_compute_dp0_master_ports()
117 sdw_fill_port_params(&p_rt->port_params, p_rt->num, bus->params.col - 1, in sdw_compute_dp0_master_ports()
126 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in sdw_compute_dp0_port_params()
138 struct sdw_bus *bus = m_rt->bus; in sdw_compute_master_ports()
139 struct sdw_bus_params *b_params = &bus->params; in sdw_compute_master_ports()
143 rate = m_rt->stream->params.rate; in sdw_compute_master_ports()
144 bps = m_rt->stream->params.bps; in sdw_compute_master_ports()
145 ch = m_rt->ch_count; in sdw_compute_master_ports()
146 sample_int = (bus->params.curr_dr_freq / rate); in sdw_compute_master_ports()
148 if (rate != params->rate) in sdw_compute_master_ports()
152 hstart = hstop - params->hwidth + 1; in sdw_compute_master_ports()
155 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { in sdw_compute_master_ports()
156 if (p_rt->lane != params->lane) in sdw_compute_master_ports()
159 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num, in sdw_compute_master_ports()
162 SDW_BLK_PKG_PER_PORT, p_rt->lane); in sdw_compute_master_ports()
164 sdw_fill_port_params(&p_rt->port_params, in sdw_compute_master_ports()
165 p_rt->num, bps, in sdw_compute_master_ports()
167 b_params->m_data_mode); in sdw_compute_master_ports()
170 if (!(p_rt == list_first_entry(&m_rt->port_list, in sdw_compute_master_ports()
184 t_data.lane = params->lane; in sdw_compute_master_ports()
197 if (l > 0 && !bus->lane_used_bandwidth[l]) in _sdw_compute_port_params()
200 hstop = bus->params.col - 1; in _sdw_compute_port_params()
206 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in _sdw_compute_port_params()
211 if (m_rt->stream->state > SDW_STREAM_DISABLED || in _sdw_compute_port_params()
212 m_rt->stream->state < SDW_STREAM_CONFIGURED) in _sdw_compute_port_params()
217 hstop = hstop - params[i].hwidth; in _sdw_compute_port_params()
229 int sel_col = bus->params.col; in sdw_compute_group_params()
233 /* Calculate bandwidth per group */ in sdw_compute_group_params()
234 for (i = 0; i < group->count; i++) { in sdw_compute_group_params()
235 params[i].rate = group->rates[i]; in sdw_compute_group_params()
236 params[i].lane = group->lanes[i]; in sdw_compute_group_params()
237 params[i].full_bw = bus->params.curr_dr_freq / params[i].rate; in sdw_compute_group_params()
240 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in sdw_compute_group_params()
241 if (m_rt->stream == stream) { in sdw_compute_group_params()
243 if (stream->state != SDW_STREAM_CONFIGURED) in sdw_compute_group_params()
250 if (m_rt->stream->state != SDW_STREAM_ENABLED && in sdw_compute_group_params()
251 m_rt->stream->state != SDW_STREAM_PREPARED && in sdw_compute_group_params()
252 m_rt->stream->state != SDW_STREAM_DISABLED) in sdw_compute_group_params()
255 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { in sdw_compute_group_params()
256 rate = m_rt->stream->params.rate; in sdw_compute_group_params()
257 bps = m_rt->stream->params.bps; in sdw_compute_group_params()
258 ch = hweight32(p_rt->ch_mask); in sdw_compute_group_params()
260 for (i = 0; i < group->count; i++) { in sdw_compute_group_params()
261 if (rate == params[i].rate && p_rt->lane == params[i].lane) in sdw_compute_group_params()
268 if (l > 0 && !bus->lane_used_bandwidth[l]) in sdw_compute_group_params()
272 for (i = 0; i < group->count; i++) { in sdw_compute_group_params()
277 params[i].full_bw - 1) / params[i].full_bw; in sdw_compute_group_params()
282 return -EINVAL; in sdw_compute_group_params()
284 if (params[i].lane == 0 && column_needed > sel_col - 1) in sdw_compute_group_params()
285 return -EINVAL; in sdw_compute_group_params()
296 int num = group->count; in sdw_add_element_group_count()
300 if (rate == group->rates[i] && lane == group->lanes[i]) in sdw_add_element_group_count()
306 if (group->count >= group->max_size) { in sdw_add_element_group_count()
308 unsigned int *lanes; in sdw_add_element_group_count() local
310 group->max_size += 1; in sdw_add_element_group_count()
311 rates = krealloc(group->rates, in sdw_add_element_group_count()
312 (sizeof(int) * group->max_size), in sdw_add_element_group_count()
315 return -ENOMEM; in sdw_add_element_group_count()
317 group->rates = rates; in sdw_add_element_group_count()
319 lanes = krealloc(group->lanes, in sdw_add_element_group_count()
320 (sizeof(int) * group->max_size), in sdw_add_element_group_count()
322 if (!lanes) in sdw_add_element_group_count()
323 return -ENOMEM; in sdw_add_element_group_count()
325 group->lanes = lanes; in sdw_add_element_group_count()
328 group->rates[group->count] = rate; in sdw_add_element_group_count()
329 group->lanes[group->count++] = lane; in sdw_add_element_group_count()
343 group->count = 0; in sdw_get_group_count()
344 group->max_size = SDW_STRM_RATE_GROUPING; in sdw_get_group_count()
345 group->rates = kcalloc(group->max_size, sizeof(int), GFP_KERNEL); in sdw_get_group_count()
346 if (!group->rates) in sdw_get_group_count()
347 return -ENOMEM; in sdw_get_group_count()
349 group->lanes = kcalloc(group->max_size, sizeof(int), GFP_KERNEL); in sdw_get_group_count()
350 if (!group->lanes) { in sdw_get_group_count()
351 kfree(group->rates); in sdw_get_group_count()
352 group->rates = NULL; in sdw_get_group_count()
353 return -ENOMEM; in sdw_get_group_count()
356 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in sdw_get_group_count()
357 if (m_rt->stream->state == SDW_STREAM_DEPREPARED) in sdw_get_group_count()
360 rate = m_rt->stream->params.rate; in sdw_get_group_count()
361 if (m_rt == list_first_entry(&bus->m_rt_list, in sdw_get_group_count()
364 group->rates[group->count++] = rate; in sdw_get_group_count()
370 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { in sdw_get_group_count()
371 ret = sdw_add_element_group_count(group, rate, p_rt->lane); in sdw_get_group_count()
373 kfree(group->rates); in sdw_get_group_count()
374 kfree(group->lanes); in sdw_get_group_count()
404 ret = -ENOMEM; in sdw_compute_port_params()
419 kfree(group.lanes); in sdw_compute_port_params()
426 struct sdw_master_prop *prop = &bus->prop; in sdw_select_row_col()
431 if (sdw_rows[r] != prop->default_row || in sdw_select_row_col()
432 sdw_cols[c] != prop->default_col) in sdw_select_row_col()
435 if (clk_freq * (sdw_cols[c] - 1) < in sdw_select_row_col()
436 bus->params.bandwidth * sdw_cols[c]) in sdw_select_row_col()
439 bus->params.row = sdw_rows[r]; in sdw_select_row_col()
440 bus->params.col = sdw_cols[c]; in sdw_select_row_col()
445 return -EINVAL; in sdw_select_row_col()
453 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) in is_clock_scaling_supported()
454 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) in is_clock_scaling_supported()
455 if (!is_clock_scaling_supported_by_slave(s_rt->slave)) in is_clock_scaling_supported()
474 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in is_lane_connected_to_all_peripherals()
475 slave_prop = &s_rt->slave->prop; in is_lane_connected_to_all_peripherals()
477 if (slave_prop->lane_maps[i] == lane) { in is_lane_connected_to_all_peripherals()
478 dev_dbg(&s_rt->slave->dev, in is_lane_connected_to_all_peripherals()
485 dev_dbg(&s_rt->slave->dev, "M lane %d is not connected\n", lane); in is_lane_connected_to_all_peripherals()
495 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop; in get_manager_lane()
502 if (!slave_prop->lane_maps[l]) in get_manager_lane()
506 list_for_each_entry(m_p_rt, &m_rt->port_list, port_node) { in get_manager_lane()
507 required_bandwidth += m_rt->stream->params.rate * in get_manager_lane()
508 hweight32(m_p_rt->ch_mask) * in get_manager_lane()
509 m_rt->stream->params.bps; in get_manager_lane()
512 curr_dr_freq - bus->lane_used_bandwidth[l]) { in get_manager_lane()
515 slave_prop->lane_maps[l])) { in get_manager_lane()
516 dev_dbg(bus->dev, in get_manager_lane()
518 slave_prop->lane_maps[l]); in get_manager_lane()
521 m_lane = slave_prop->lane_maps[l]; in get_manager_lane()
522 dev_dbg(&s_rt->slave->dev, "M lane %d is used\n", m_lane); in get_manager_lane()
523 bus->lane_used_bandwidth[l] += required_bandwidth; in get_manager_lane()
525 * Use non-zero manager lane, subtract the lane 0 in get_manager_lane()
528 bus->params.bandwidth -= required_bandwidth; in get_manager_lane()
544 struct sdw_master_prop *mstr_prop = &bus->prop; in sdw_compute_bus_params()
556 if (mstr_prop->num_clk_gears) { in sdw_compute_bus_params()
557 clk_values = mstr_prop->num_clk_gears; in sdw_compute_bus_params()
558 clk_buf = mstr_prop->clk_gears; in sdw_compute_bus_params()
560 } else if (mstr_prop->num_clk_freq) { in sdw_compute_bus_params()
561 clk_values = mstr_prop->num_clk_freq; in sdw_compute_bus_params()
562 clk_buf = mstr_prop->clk_freq; in sdw_compute_bus_params()
574 curr_dr_freq = bus->params.max_dr_freq; in sdw_compute_bus_params()
577 (bus->params.max_dr_freq >> clk_buf[i]) : in sdw_compute_bus_params()
580 if (curr_dr_freq * (mstr_prop->default_col - 1) >= in sdw_compute_bus_params()
581 bus->params.bandwidth * mstr_prop->default_col) in sdw_compute_bus_params()
584 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in sdw_compute_bus_params()
588 * multi-lane if we can't find any available lane for the first Peripheral. in sdw_compute_bus_params()
590 s_rt = list_first_entry(&m_rt->slave_rt_list, in sdw_compute_bus_params()
609 dev_err(bus->dev, "%s: could not find clock value for bandwidth %d\n", in sdw_compute_bus_params()
610 __func__, bus->params.bandwidth); in sdw_compute_bus_params()
611 return -EINVAL; in sdw_compute_bus_params()
616 /* Set Peripheral lanes */ in sdw_compute_bus_params()
617 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in sdw_compute_bus_params()
618 slave_prop = &s_rt->slave->prop; in sdw_compute_bus_params()
620 if (slave_prop->lane_maps[l] == m_lane) { in sdw_compute_bus_params()
621 list_for_each_entry(s_p_rt, &s_rt->port_list, port_node) { in sdw_compute_bus_params()
622 s_p_rt->lane = l; in sdw_compute_bus_params()
623 dev_dbg(&s_rt->slave->dev, in sdw_compute_bus_params()
625 l, s_p_rt->num); in sdw_compute_bus_params()
632 * Set Manager lanes. Configure the last m_rt in bus->m_rt_list only since in sdw_compute_bus_params()
635 list_for_each_entry(m_p_rt, &m_rt->port_list, port_node) { in sdw_compute_bus_params()
636 m_p_rt->lane = m_lane; in sdw_compute_bus_params()
640 if (!mstr_prop->default_frame_rate || !mstr_prop->default_row) in sdw_compute_bus_params()
641 return -EINVAL; in sdw_compute_bus_params()
643 mstr_prop->default_col = curr_dr_freq / mstr_prop->default_frame_rate / in sdw_compute_bus_params()
644 mstr_prop->default_row; in sdw_compute_bus_params()
648 dev_err(bus->dev, "%s: could not find frame configuration for bus dr_freq %d\n", in sdw_compute_bus_params()
650 return -EINVAL; in sdw_compute_bus_params()
653 bus->params.curr_dr_freq = curr_dr_freq; in sdw_compute_bus_params()
672 if (stream->type == SDW_STREAM_BPT) { in sdw_compute_params()
680 dev_err(bus->dev, "Compute transport params failed: %d\n", ret); in sdw_compute_params()